{"exp_name": "mode-0-gt-cv-switch-4", "metadata": {}, "start_time": 1620303610.1942809, "end_time": 1620323332.7234075, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.0.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.0.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9401842560", "    m_axis_ctrl_dma_read_desc_ram_addr = 1152", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 9", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516186656", "    m_axis_ctrl_dma_write_desc_ram_addr = 352", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 11", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 5", "    m_axis_data_dma_write_desc_dma_addr = 9179287552", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 17", "    s_axil_rdata = 2147483661", "    m_axil_csr_awaddr = 7345580", "    m_axil_csr_wdata = 2147483661", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7345580", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231173096000"], "stderr": []}, "nic.server.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.1.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.1.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9406282464", "    m_axis_ctrl_dma_read_desc_ram_addr = 128", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 1", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515848288", "    m_axis_ctrl_dma_write_desc_ram_addr = 192", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 6", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 21", "    m_axis_data_dma_write_desc_dma_addr = 8971862016", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 30", "    s_axil_rdata = 2147483650", "    m_axil_csr_awaddr = 7343180", "    m_axil_csr_wdata = 2147483650", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7343180", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231173084000"], "stderr": []}, "nic.server.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.2.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.2.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9396110288", "    m_axis_ctrl_dma_read_desc_ram_addr = 1920", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 15", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516081600", "    m_axis_ctrl_dma_write_desc_ram_addr = 416", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 13", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 2", "    m_axis_data_dma_write_desc_dma_addr = 9112481792", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 1", "    s_axil_rdata = 2147483655", "    m_axil_csr_awaddr = 7347436", "    m_axil_csr_wdata = 2147483655", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7347436", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231173272000"], "stderr": []}, "nic.server.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.3.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.3.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9410591456", "    m_axis_ctrl_dma_read_desc_ram_addr = 1536", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 12", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516247936", "    m_axis_ctrl_dma_write_desc_ram_addr = 800", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 25", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 8", "    m_axis_data_dma_write_desc_dma_addr = 8415174656", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 24", "    s_axil_rdata = 2147483663", "    m_axil_csr_awaddr = 7340524", "    m_axil_csr_wdata = 2147483663", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7340524", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231173272000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.0.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.0.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9483054656", "    m_axis_ctrl_dma_read_desc_ram_addr = 1280", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 10", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516040864", "    m_axis_ctrl_dma_write_desc_ram_addr = 64", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 2", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 14", "    m_axis_data_dma_write_desc_dma_addr = 8910307328", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 26", "    s_axil_rdata = 2147483655", "    m_axil_csr_awaddr = 4196588", "    m_axil_csr_wdata = 2147483655", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4196588", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231172936000"], "stderr": []}, "nic.client.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.1.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.1.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9459657664", "    m_axis_ctrl_dma_read_desc_ram_addr = 256", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 2", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516750176", "    m_axis_ctrl_dma_write_desc_ram_addr = 672", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 21", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 30", "    m_axis_data_dma_write_desc_dma_addr = 9296818176", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 5", "    s_axil_rdata = 2147483679", "    m_axil_csr_awaddr = 4198380", "    m_axil_csr_wdata = 2147483679", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4198380", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231173256000"], "stderr": []}, "nic.client.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.2.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.2.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9450295168", "    m_axis_ctrl_dma_read_desc_ram_addr = 2048", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 16", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516490208", "    m_axis_ctrl_dma_write_desc_ram_addr = 928", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 29", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 1", "    m_axis_data_dma_write_desc_dma_addr = 9095249920", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 16", "    s_axil_rdata = 2147483668", "    m_axil_csr_awaddr = 4199052", "    m_axil_csr_wdata = 2147483668", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4199052", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231173036000"], "stderr": []}, "nic.client.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.3.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.3.", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9493932992", "    m_axis_ctrl_dma_read_desc_ram_addr = 1664", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 13", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516588768", "    m_axis_ctrl_dma_write_desc_ram_addr = 256", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 8", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 11", "    m_axis_data_dma_write_desc_dma_addr = 8554278912", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 22", "    s_axil_rdata = 2147483674", "    m_axil_csr_awaddr = 4195148", "    m_axil_csr_wdata = 2147483674", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4195148", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15231172372000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/net/switch/net_switch", "-m", "0", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.1.", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.2.", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.server.3.", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.0.", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.1.", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.2.", "-s", "/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.eth.client.3."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.0", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.0", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.0.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.0.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31820", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.0 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.0 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.0. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.0. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1302341064634", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.752931] mqnic: loading out-of-tree module taints kernel.\r", "[    0.754931] mqnic 0000:00:02.0: mqnic probe\r", "[    0.754931] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.754931] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.754931] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.754931] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.754931] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.754931] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.754931] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.754931] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.754931] mqnic 0000:00:02.0: IF count: 1\r", "[    0.754931] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.754931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.754931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.754931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.754931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.760930] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.760930] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.760930] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.760930] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.760930] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.760930] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.760930] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.760930] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.760930] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.760930] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.760930] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.760930] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.760930] mqnic 0000:00:02.0: Port count: 1\r", "[    0.760930] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.760930] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.760930] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.760930] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.985896] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.985896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.985896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.055885] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  6] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 54876\r", "[  5] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 54874\r", "[    5.368230] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.1 sec   832 MBytes   694 Mbits/sec\r", "[  6]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1302341054634.  Starting simulation...", "info: Entering event queue @ 1302341064634.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1302341064957.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.1": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.1", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.1", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.1.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.1.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31822", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.1 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.1 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.1. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.1. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1305148720834", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.755931] mqnic: loading out-of-tree module taints kernel.\r", "[    0.756931] mqnic 0000:00:02.0: mqnic probe\r", "[    0.756931] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.756931] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.756931] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.756931] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.756931] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.756931] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.756931] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.756931] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.756931] mqnic 0000:00:02.0: IF count: 1\r", "[    0.756931] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.756931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.757931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.757931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.757931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.761930] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.761930] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.761930] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.761930] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.761930] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.761930] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.761930] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.761930] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.762930] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.762930] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.762930] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.762930] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.762930] mqnic 0000:00:02.0: Port count: 1\r", "[    0.762930] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.762930] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.762930] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.762930] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.986896] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.986896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.986896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.986896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.986896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.986896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.986896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.057886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 37114\r", "[  6] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 37116\r", "[    5.331236] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.1 sec   832 MBytes   688 Mbits/sec\r", "[  6]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1305148710834.  Starting simulation...", "info: Entering event queue @ 1305148720834.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1305148721157.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.2": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.2", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.2", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.2.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.2.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31823", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.2 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.2 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.2. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.2. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1313380236412", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.762932] mqnic: loading out-of-tree module taints kernel.\r", "[    0.763932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.763932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.763932] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.763932] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.763932] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.763932] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.763932] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.763932] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.763932] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.763932] mqnic 0000:00:02.0: IF count: 1\r", "[    0.763932] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.764931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.764931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.764931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.764931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.768931] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.768931] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.768931] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.768931] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.768931] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.768931] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.768931] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.769931] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.769931] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.769931] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.769931] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.769931] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.769931] mqnic 0000:00:02.0: Port count: 1\r", "[    0.769931] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.769931] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.769931] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.769931] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.993897] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.993897] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.993897] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.993897] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.993897] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.993897] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.993897] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.064886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.3/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  6] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 47656\r", "[  5] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 47654\r", "[    5.349235] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  6]  0.0-10.1 sec   832 MBytes   692 Mbits/sec\r", "[  5]  0.0-10.1 sec   832 MBytes   690 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1313380226412.  Starting simulation...", "info: Entering event queue @ 1313380236412.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1313380236735.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.3": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.3", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.3", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.3.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.3.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31824", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.server.3 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.server.3 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.server.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.server.3. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.server.3. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1315052121187", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.755931] mqnic: loading out-of-tree module taints kernel.\r", "[    0.757931] mqnic 0000:00:02.0: mqnic probe\r", "[    0.757931] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.757931] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.757931] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.757931] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.757931] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.757931] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.757931] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.757931] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.757931] mqnic 0000:00:02.0: IF count: 1\r", "[    0.757931] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.757931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.757931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.757931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.757931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.763930] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.763930] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.763930] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.763930] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.763930] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.763930] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.763930] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.763930] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.763930] mqnic 0000:00:02.0: Port count: 1\r", "[    0.763930] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.763930] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.763930] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.763930] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.988896] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.988896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.988896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.058885] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.4/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 49860\r", "[  6] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 49862\r", "[    5.304240] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[  6]  0.0-10.1 sec   832 MBytes   688 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1315052111187.  Starting simulation...", "info: Entering event queue @ 1315052121187.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1315052121510.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14", "warn: PowerState: More than one power state change request encountered within the same simulation tick"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.0", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.0", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.0.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.0.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31825", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.0 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.0 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.0. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.0. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1309659759613", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.757931] mqnic: loading out-of-tree module taints kernel.\r", "[    0.758931] mqnic 0000:00:02.0: mqnic probe\r", "[    0.758931] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.759931] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.759931] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.759931] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.759931] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.759931] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.759931] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.759931] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.759931] mqnic 0000:00:02.0: IF count: 1\r", "[    0.759931] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.759931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.759931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.759931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.759931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.764930] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.764930] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.764930] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.764930] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.764930] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.764930] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.764930] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.764930] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.764930] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.764930] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.764930] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.764930] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.764930] mqnic 0000:00:02.0: Port count: 1\r", "[    0.764930] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.764930] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.764930] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.764930] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.988896] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.988896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.989896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.989896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.989896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.989896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.989896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.061885] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.5/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.5 port 54876 connected with 10.0.0.1 port 5001\r", "[  4] local 10.0.0.5 port 54874 connected with 10.0.0.1 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.293242] random: crng init done\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  5.0- 6.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  0.0-10.1 sec   832 MBytes   694 Mbits/sec\r", "[  5]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r", "+ sleep 10\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1309659749613.  Starting simulation...", "info: Entering event queue @ 1309659759613.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1309659759936.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.1": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.1", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.1", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.1.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.1.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31826", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.1 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.1 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.1. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.1. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1304435399536", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.752932] mqnic: loading out-of-tree module taints kernel.\r", "[    0.753932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.753932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.753932] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.753932] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.753932] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.753932] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.753932] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.753932] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.754932] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.754932] mqnic 0000:00:02.0: IF count: 1\r", "[    0.754932] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.754932] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.754932] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.754932] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.754932] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.758931] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.758931] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.758931] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.758931] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.758931] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.759931] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.759931] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.759931] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.759931] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.759931] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.759931] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.759931] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.759931] mqnic 0000:00:02.0: Port count: 1\r", "[    0.759931] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.759931] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.759931] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.759931] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.983897] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.983897] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.983897] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.983897] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.983897] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.983897] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.983897] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.054886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.6/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.2 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.2, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.6 port 37114 connected with 10.0.0.2 port 5001\r", "[  5] local 10.0.0.6 port 37116 connected with 10.0.0.2 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.300241] random: crng init done\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[  5]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep 10\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1304435389536.  Starting simulation...", "info: Entering event queue @ 1304435399536.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1304435399859.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.2": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.2", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.2", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.2.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.2.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31827", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.2 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.2 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.2. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.2. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1301614033726", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.744933] mqnic: loading out-of-tree module taints kernel.\r", "[    0.745932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.746932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.746932] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.746932] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.746932] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.746932] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.746932] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.746932] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.746932] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.746932] mqnic 0000:00:02.0: IF count: 1\r", "[    0.746932] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.746932] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.746932] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.746932] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.746932] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.751932] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.751932] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.751932] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.751932] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.751932] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.751932] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.751932] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.751932] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.751932] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.751932] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.751932] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.751932] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.751932] mqnic 0000:00:02.0: Port count: 1\r", "[    0.751932] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.751932] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.751932] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.751932] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.975898] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.976897] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.976897] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.976897] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.976897] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.976897] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.976897] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.046887] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.7/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.3 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.3, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.7 port 47656 connected with 10.0.0.3 port 5001\r", "[  4] local 10.0.0.7 port 47654 connected with 10.0.0.3 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.246248] random: crng init done\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  5.0- 6.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.1 sec   832 MBytes   692 Mbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  9.0-10.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  0.0-10.1 sec   832 MBytes   690 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r", "+ sleep 10\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1301614023726.  Starting simulation...", "info: Entering event queue @ 1301614033726.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1301614034049.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.3": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.3", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.3", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.3.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.3.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder07, pid 31828", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/gem5-out.client.3 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-0-gt-cv-switch-4/0/gem5-cp.client.3 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/cfg.client.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.pci.client.3. --simbricks-shm=/local/var/tmp/hejing-work/mode-0-gt-cv-switch-4/1/nic.shm.client.3. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1309018507174", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.753933] mqnic: loading out-of-tree module taints kernel.\r", "[    0.754933] mqnic 0000:00:02.0: mqnic probe\r", "[    0.754933] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.755933] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.755933] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.755933] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.755933] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.755933] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.755933] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.755933] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.755933] mqnic 0000:00:02.0: IF count: 1\r", "[    0.755933] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.755933] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.755933] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.755933] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.755933] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.760932] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.760932] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.760932] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.760932] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.760932] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.760932] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.760932] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.760932] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.760932] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.760932] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.760932] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.760932] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.760932] mqnic 0000:00:02.0: Port count: 1\r", "[    0.760932] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.760932] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.760932] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.760932] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.984898] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.985898] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.985898] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.985898] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.985898] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.985898] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.985898] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.055887] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.8/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.4 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.4, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.8 port 49860 connected with 10.0.0.4 port 5001\r", "[  5] local 10.0.0.8 port 49862 connected with 10.0.0.4 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.247250] random: crng init done\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  9.0-10.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  0.0-10.1 sec   832 MBytes   688 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r", "+ sleep 0.5\r", "+ m5 exit\r", "Exiting @ tick 15231172015899 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1309018497174.  Starting simulation...", "info: Entering event queue @ 1309018507174.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1309018507497.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}