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Commit f60e7264 authored by Hejing Li's avatar Hejing Li
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result: add sync_mode 1 tcp test data

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results/paper_data/modetcp/modetcp-0-gt-cb-switch-1-0.json 0 → 100644
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results/paper_data/modetcp/modetcp-0-gt-cv-switch-1-1.json 0 → 100644
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{"exp_name": "CdmTCP-gt-cv-switch-1", "metadata": {}, "start_time": 1607494444.284776, "end_time": 1607526420.5633893, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.pci.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.eth.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.shm.server.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9405153536", " m_axis_ctrl_dma_read_desc_ram_addr = 896", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 7", " m_axis_ctrl_dma_write_desc_dma_addr = 9515889984", " m_axis_ctrl_dma_write_desc_ram_addr = 928", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 29", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_write_desc_dma_addr = 8696041472", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 25", " s_axil_rdata = 2147483660", " m_axil_csr_awaddr = 7342476", " m_axil_csr_wdata = 2147483660", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7342476", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19288469176000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.pci.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.eth.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.shm.client.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9499640896", " m_axis_ctrl_dma_read_desc_ram_addr = 1024", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 8", " m_axis_ctrl_dma_write_desc_dma_addr = 9516064096", " m_axis_ctrl_dma_write_desc_ram_addr = 800", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 25", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 27", " m_axis_data_dma_write_desc_dma_addr = 9019768832", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 13", " s_axil_rdata = 2147483667", " m_axil_csr_awaddr = 4194924", " m_axil_csr_wdata = 2147483667", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4194924", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19288468476000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "0", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.eth.client.0."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-1/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62802", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-1/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1866625933915", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.860920] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.862920] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.862920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.862920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.862920] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.862920] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.862920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.862920] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.862920] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.862920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.862920] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.862920] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.862920] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.862920] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.862920] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.862920] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.868919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.868919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.868919] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.868919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.868919] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.868919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.868919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.868919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.868919] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.868919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.868919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.868919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.868919] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.868919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.868919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.868919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.869919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.093885] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.093885] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.093885] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.093885] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.093885] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.093885] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.093885] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.162874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 50054\r", "[ 5] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 50052\r", "[ 5.424226] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.1 sec 832 MBytes 693 Mbits/sec\r", "[ 6] 0.0-10.1 sec 832 MBytes 689 Mbits/sec\r", "[SUM] 0.0-10.1 sec 1.62 GBytes 1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1866625923915. Starting simulation...", "info: Entering event queue @ 1866625933915. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1866625934238. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-1/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62803", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-1/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-1/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1884055277791", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.854921] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.855921] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.855921] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.855921] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.855921] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.855921] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.856920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.856920] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.856920] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.856920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.856920] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.856920] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.856920] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.856920] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.856920] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.856920] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.860920] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.861920] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.861920] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.861920] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.861920] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.861920] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.861920] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.861920] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.861920] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.861920] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.861920] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.861920] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.861920] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.861920] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.861920] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.861920] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.861920] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.085886] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.085886] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.086886] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.086886] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.086886] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.086886] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.086886] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.155875] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.2 port 50054 connected with 10.0.0.1 port 5001\r", "[ 4] local 10.0.0.2 port 50052 connected with 10.0.0.1 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.337239] random: crng init done\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 0.0-10.1 sec 832 MBytes 693 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 689 Mbits/sec\r", "[SUM] 0.0-10.1 sec 1.62 GBytes 1.38 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19288468160397 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1884055267791. Starting simulation...", "info: Entering event queue @ 1884055277791. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1884055278114. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}
\ No newline at end of file
results/paper_data/modetcp/modetcp-0-gt-cv-switch-4-0.json 0 → 100644
View file @ f60e7264
This source diff could not be displayed because it is too large. You can view the blob instead.
results/paper_data/modetcp/modetcp-0-gt-cv-switch-4-1.json 0 → 100644
View file @ f60e7264
{"exp_name": "CdmTCP-gt-cv-switch-4", "metadata": {}, "start_time": 1607494444.3093116, "end_time": 1607530093.916104, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9400745728", " m_axis_ctrl_dma_read_desc_ram_addr = 1664", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 13", " m_axis_ctrl_dma_write_desc_dma_addr = 9516447392", " m_axis_ctrl_dma_write_desc_ram_addr = 896", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 28", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 13", " m_axis_data_dma_write_desc_dma_addr = 8740786176", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 6", " s_axil_rdata = 2147483675", " m_axil_csr_awaddr = 7345004", " m_axil_csr_wdata = 2147483675", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7345004", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356787352000"], "stderr": []}, "nic.server.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9404881456", " m_axis_ctrl_dma_read_desc_ram_addr = 3840", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 30", " m_axis_ctrl_dma_write_desc_dma_addr = 9515843872", " m_axis_ctrl_dma_write_desc_ram_addr = 736", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 23", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 8", " m_axis_data_dma_write_desc_dma_addr = 9073459200", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 1", " s_axil_rdata = 2147483658", " m_axil_csr_awaddr = 7342412", " m_axil_csr_wdata = 2147483658", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7342412", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356787400000"], "stderr": []}, "nic.server.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9399960352", " m_axis_ctrl_dma_read_desc_ram_addr = 2688", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 21", " m_axis_ctrl_dma_write_desc_dma_addr = 9516063328", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 14", " m_axis_data_dma_write_desc_dma_addr = 9158647808", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 19", " s_axil_rdata = 2147483664", " m_axil_csr_awaddr = 7344652", " m_axil_csr_wdata = 2147483664", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7344652", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356787392000"], "stderr": []}, "nic.server.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9406022288", " m_axis_ctrl_dma_read_desc_ram_addr = 3200", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 25", " m_axis_ctrl_dma_write_desc_dma_addr = 9516425216", " m_axis_ctrl_dma_write_desc_ram_addr = 896", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 28", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 6", " m_axis_data_dma_write_desc_dma_addr = 8624656384", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 24", " s_axil_rdata = 2147483677", " m_axil_csr_awaddr = 7343020", " m_axil_csr_wdata = 2147483677", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7343020", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356787508000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9473753152", " m_axis_ctrl_dma_read_desc_ram_addr = 1792", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 14", " m_axis_ctrl_dma_write_desc_dma_addr = 9516548096", " m_axis_ctrl_dma_write_desc_ram_addr = 160", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 5", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 4", " m_axis_data_dma_write_desc_dma_addr = 9326256128", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 9", " s_axil_rdata = 2147483678", " m_axil_csr_awaddr = 4197324", " m_axil_csr_wdata = 2147483678", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4197324", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356787036000"], "stderr": []}, "nic.client.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9485052160", " m_axis_ctrl_dma_read_desc_ram_addr = 3968", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 31", " m_axis_ctrl_dma_write_desc_dma_addr = 9516096928", " m_axis_ctrl_dma_write_desc_ram_addr = 128", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 4", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 27", " m_axis_data_dma_write_desc_dma_addr = 8865484800", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 31", " s_axil_rdata = 2147483668", " m_axil_csr_awaddr = 4195980", " m_axil_csr_wdata = 2147483668", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4195980", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356787336000"], "stderr": []}, "nic.client.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9502461120", " m_axis_ctrl_dma_read_desc_ram_addr = 2816", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 22", " m_axis_ctrl_dma_write_desc_dma_addr = 9514999488", " m_axis_ctrl_dma_write_desc_ram_addr = 96", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 3", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 20", " m_axis_data_dma_write_desc_dma_addr = 9529102336", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 4", " s_axil_rdata = 2147483649", " m_axil_csr_awaddr = 4194348", " m_axil_csr_wdata = 2147483649", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4194348", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356787084000"], "stderr": []}, "nic.client.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9444002432", " m_axis_ctrl_dma_read_desc_ram_addr = 3328", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 26", " m_axis_ctrl_dma_write_desc_dma_addr = 9516171264", " m_axis_ctrl_dma_write_desc_ram_addr = 640", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 20", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 6", " m_axis_data_dma_write_desc_dma_addr = 8785838080", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 3", " s_axil_rdata = 2147483669", " m_axil_csr_awaddr = 4200108", " m_axil_csr_wdata = 2147483669", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4200108", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19356786588000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "0", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.1.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.2.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.server.3.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.0.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.1.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.2.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.eth.client.3."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62808", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1957300999750", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.861920] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.862919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.862919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.862919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.862919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.862919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.862919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.863919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.863919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.863919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.863919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.863919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.863919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.863919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.863919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.863919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.867919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.867919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.868918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.868918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.868918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.868918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.868918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.868918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.868918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.868918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.868918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.868918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.868918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.868918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.868918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.868918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.868918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.092884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.092884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.092884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.092884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.093884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.093884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.093884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.162874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 36030\r", "[ 6] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 36032\r", "[ 5.363235] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 684 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1957300989750. Starting simulation...", "info: Entering event queue @ 1957300999750. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1957301000073. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.1.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.1.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62810", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.1. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.1. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1991946510226", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.882917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.884917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.884917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.884917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.884917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.884917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.884917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.884917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.884917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.884917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.884917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.884917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.884917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.884917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.885916] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.885916] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.890916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.890916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.890916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.890916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.890916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.890916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.890916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.890916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.890916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.890916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.890916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.891915] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.891915] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.891915] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.891915] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.891915] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.891915] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.115881] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.115881] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.115881] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.115881] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.115881] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.115881] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.115881] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.184871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 53688\r", "[ 6] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 53686\r", "[ 5.342239] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.3 sec 832 MBytes 678 Mbits/sec\r", "[ 5] 0.0-10.3 sec 864 MBytes 701 Mbits/sec\r", "[SUM] 0.0-10.3 sec 1.66 GBytes 1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1991946500226. Starting simulation...", "info: Entering event queue @ 1991946510226. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1991946510549. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.2.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.2.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62812", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.2. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.2. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1916139572047", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.850920] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.852920] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.852920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.852920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.852920] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.852920] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.852920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.852920] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.852920] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.852920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.852920] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.852920] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.852920] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.852920] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.853919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.853919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.857919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.857919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.857919] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.857919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.857919] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.857919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.857919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.857919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.857919] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.857919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.857919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.857919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.857919] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.858919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.858919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.858919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.858919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.082885] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.082885] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.082885] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.082885] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.082885] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.082885] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.082885] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.151874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.3/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 34582\r", "[ 6] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 34584\r", "[ 5.355235] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.2 sec 832 MBytes 686 Mbits/sec\r", "[ 6] 0.0-10.2 sec 832 MBytes 682 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1916139562047. Starting simulation...", "info: Entering event queue @ 1916139572047. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1916139572370. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.3.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.3.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62813", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.server.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.server.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.server.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.server.3. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.server.3. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1955210164678", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.874918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.875918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.875918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.875918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.875918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.875918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.875918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.875918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.875918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.875918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.875918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.875918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.875918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.876918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.876918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.876918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.880917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.880917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.880917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.880917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.880917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.880917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.880917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.880917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.880917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.881917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.881917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.881917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.881917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.881917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.881917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.881917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.881917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.105883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.105883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.105883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.105883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.105883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.105883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.105883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.174873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.4/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 59774\r", "[ 5] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 59772\r", "[ 5.410229] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.0 sec 832 MBytes 697 Mbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 689 Mbits/sec\r", "[SUM] 0.0-10.1 sec 1.62 GBytes 1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1955210154678. Starting simulation...", "info: Entering event queue @ 1955210164678. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1955210165001. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62815", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1943368517512", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.872917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.874917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.874917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.874917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.874917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.874917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.874917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.874917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.874917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.874917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.874917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.874917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.874917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.874917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.874917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.874917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.880916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.880916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.880916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.880916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.880916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.880916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.880916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.880916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.880916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.880916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.880916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.880916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.880916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.880916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.880916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.880916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.880916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.105882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.105882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.105882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.105882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.105882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.105882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.105882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.174871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.5/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.5 port 36030 connected with 10.0.0.1 port 5001\r", "[ 5] local 10.0.0.5 port 36032 connected with 10.0.0.1 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.344238] random: crng init done\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 686 Mbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 684 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1943368507512. Starting simulation...", "info: Entering event queue @ 1943368517512. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1943368517835. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.1.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.1.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62816", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.1. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.1. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1891647062407", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.863919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.865919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.865919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.865919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.865919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.865919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.865919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.865919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.865919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.865919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.865919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.865919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.865919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.865919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.865919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.865919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.871918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.871918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.871918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.871918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.871918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.871918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.871918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.871918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.871918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.871918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.871918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.871918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.871918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.871918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.871918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.871918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.871918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.096884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.096884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.096884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.096884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.096884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.096884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.096884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.165873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.6/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.2 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.2, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.6 port 53686 connected with 10.0.0.2 port 5001\r", "[ 5] local 10.0.0.6 port 53688 connected with 10.0.0.2 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.346238] random: crng init done\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 5.0- 6.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0-10.3 sec 832 MBytes 679 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 0.0-10.3 sec 864 MBytes 701 Mbits/sec\r", "[SUM] 0.0-10.3 sec 1.66 GBytes 1.38 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1891647052407. Starting simulation...", "info: Entering event queue @ 1891647062407. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1891647062730. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.2.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.2.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62818", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.2. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.2. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1935850958929", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.870919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.872918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.872918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.872918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.872918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.872918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.872918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.872918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.872918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.872918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.872918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.872918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.872918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.872918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.873918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.873918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.878917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.878917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.878917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.878917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.878917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.878917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.878917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.878917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.878917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.878917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.878917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.879917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.879917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.879917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.879917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.879917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.879917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.103883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.103883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.103883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.173873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.7/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.3 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.3, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.7 port 34582 connected with 10.0.0.3 port 5001\r", "[ 5] local 10.0.0.7 port 34584 connected with 10.0.0.3 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.331241] random: crng init done\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 686 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 682 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.36 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1935850948929. Starting simulation...", "info: Entering event queue @ 1935850958929. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1935850959252. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.3.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.3.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62820", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/gem5-out.client.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-4/0/gem5-cp.client.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/cfg.client.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.pci.client.3. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-4/1/nic.shm.client.3. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1949083223752", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.858919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.860919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.860919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.860919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.860919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.860919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.860919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.860919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.860919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.860919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.860919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.860919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.860919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.860919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.861918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.861918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.866918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.866918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.866918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.866918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.866918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.866918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.866918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.866918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.866918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.866918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.867918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.867918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.867918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.867918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.867918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.867918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.867918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.091884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.091884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.091884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.091884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.091884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.091884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.091884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.162873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.8/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.4 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.4, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.8 port 59774 connected with 10.0.0.4 port 5001\r", "[ 4] local 10.0.0.8 port 59772 connected with 10.0.0.4 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.352236] random: crng init done\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 5.0- 6.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.0 sec 832 MBytes 697 Mbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 0.0-10.1 sec 832 MBytes 689 Mbits/sec\r", "[SUM] 0.0-10.1 sec 1.62 GBytes 1.38 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19356786377460 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1949083213752. Starting simulation...", "info: Entering event queue @ 1949083223752. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1949083224075. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}
\ No newline at end of file
results/paper_data/modetcp/modetcp-1-gt-cb-switch-1-0.json 0 → 100644
View file @ f60e7264
This source diff could not be displayed because it is too large. You can view the blob instead.
results/paper_data/modetcp/modetcp-1-gt-cb-switch-1-1.json 0 → 100644
View file @ f60e7264
{"exp_name": "modetcp-1-gt-cb-switch-1", "metadata": {}, "start_time": 1607541231.1002765, "end_time": 1607562128.1041777, "sims": {"nic.server.0.": {"class": "CorundumBMNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum_bm/corundum_bm", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.pci.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.eth.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.shm.server.0.", "1", "0", "500", "500", "500"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received"], "stderr": ["31f04bb4728c", "sync_pci=1 sync_eth=1", "warn: nicsim_sync failed (t=185053500000)", "warn: nicsim_sync failed (t=185053500000)", "warn: nicsim_sync failed (t=185053500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=676400500000)", "warn: nicsim_sync failed (t=1004120000000)", "warn: nicsim_sync failed (t=1004120000000)", "warn: nicsim_sync failed (t=1004120000000)", "warn: nicsim_sync failed (t=1004120000000)", "warn: nicsim_sync failed (t=1004120000000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1495995500000)", "warn: nicsim_sync failed (t=1822806000000)", "warn: nicsim_sync failed (t=1822806000000)", "warn: nicsim_sync failed (t=1822806000000)", "warn: nicsim_sync failed (t=1822806000000)", "warn: nicsim_sync failed (t=1822806000000)", "exit main_time: 19165978000000"]}, "nic.client.0.": {"class": "CorundumBMNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum_bm/corundum_bm", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.pci.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.eth.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.shm.client.0.", "1", "0", "500", "500", "500"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received"], "stderr": ["74163c9e5dbc", "sync_pci=1 sync_eth=1", "warn: nicsim_sync failed (t=176080000000)", "warn: nicsim_sync failed (t=176080000000)", "warn: nicsim_sync failed (t=176080000000)", "warn: nicsim_sync failed (t=176080000000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=667646500000)", "warn: nicsim_sync failed (t=995119500000)", "warn: nicsim_sync failed (t=995119500000)", "warn: nicsim_sync failed (t=995119500000)", "warn: nicsim_sync failed (t=995119500000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1487299000000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "warn: nicsim_sync failed (t=1814558500000)", "exit main_time: 19165977179675"]}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "1", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.eth.client.0."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cb-switch-1/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65298", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cb-switch-1/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1936345754638", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.874918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.876917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.876917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.876917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.876917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.876917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.876917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.876917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.876917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.876917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.876917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.876917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.876917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.876917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.877917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.877917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.882916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.882916] mqnic 0000:00:02.0: IF features: 0x00000000\r", "[ 0.882916] mqnic 0000:00:02.0: Event queue count: 1\r", "[ 0.882916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.882916] mqnic 0000:00:02.0: TX queue count: 1\r", "[ 0.882916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.882916] mqnic 0000:00:02.0: TX completion queue count: 1\r", "[ 0.882916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.882916] mqnic 0000:00:02.0: RX queue count: 1\r", "[ 0.882916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.882916] mqnic 0000:00:02.0: RX completion queue count: 1\r", "[ 0.882916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.882916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.882916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.883916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.883916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.883916] mqnic 0000:00:02.0: Max desc block size: 1\r", "[ 0.883916] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 0.883916] mqnic 0000:00:02.0: Port features: 0x00000000\r", "[ 0.884916] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 0.884916] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 0.884916] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 0.884916] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 0.884916] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 0.896914] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 55534\r", "[ 6] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 55536\r", "[ 4.750328] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.4 sec 672 MBytes 543 Mbits/sec\r", "[ 5] 0.0-10.4 sec 672 MBytes 542 Mbits/sec\r", "[SUM] 0.0-10.4 sec 1.31 GBytes 1.08 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1936345744638. Starting simulation...", "info: Entering event queue @ 1936345754638. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1936345754961. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cb-switch-1/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65299", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cb-switch-1/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cb-switch-1/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1997257908844", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.871918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.872918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.872918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.872918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.872918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.872918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.872918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.872918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.873918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.873918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.873918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.873918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.873918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.873918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.873918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.873918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.877917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.877917] mqnic 0000:00:02.0: IF features: 0x00000000\r", "[ 0.877917] mqnic 0000:00:02.0: Event queue count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.878917] mqnic 0000:00:02.0: TX queue count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.878917] mqnic 0000:00:02.0: TX completion queue count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.878917] mqnic 0000:00:02.0: RX queue count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.878917] mqnic 0000:00:02.0: RX completion queue count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.878917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.878917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.878917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.878917] mqnic 0000:00:02.0: Max desc block size: 1\r", "[ 0.879917] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 0.879917] mqnic 0000:00:02.0: Port features: 0x00000000\r", "[ 0.879917] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 0.879917] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 0.879917] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 0.879917] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 0.879917] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 0.891915] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.2 port 55534 connected with 10.0.0.1 port 5001\r", "[ 5] local 10.0.0.2 port 55536 connected with 10.0.0.1 port 5001\r", "[ 4.939300] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 1.0- 2.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.4 sec 672 MBytes 544 Mbits/sec\r", "[ 4] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 9.0-10.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 0.0-10.4 sec 672 MBytes 543 Mbits/sec\r", "[SUM] 0.0-10.4 sec 1.31 GBytes 1.09 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19165976694477 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1997257898844. Starting simulation...", "info: Entering event queue @ 1997257908844. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1997257909167. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}
\ No newline at end of file
results/paper_data/modetcp/modetcp-1-gt-cb-switch-4-0.json 0 → 100644
View file @ f60e7264
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results/paper_data/modetcp/modetcp-1-gt-cb-switch-4-1.json 0 → 100644
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results/paper_data/modetcp/modetcp-1-gt-cv-switch-1-0.json 0 → 100644
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results/paper_data/modetcp/modetcp-1-gt-cv-switch-1-1.json 0 → 100644
View file @ f60e7264
{"exp_name": "modetcp-1-gt-cv-switch-1", "metadata": {}, "start_time": 1607541231.100774, "end_time": 1607571668.3146589, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.server.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9410462784", " m_axis_ctrl_dma_read_desc_ram_addr = 2688", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 21", " m_axis_ctrl_dma_write_desc_dma_addr = 9516095328", " m_axis_ctrl_dma_write_desc_ram_addr = 192", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 6", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 14", " m_axis_data_dma_write_desc_dma_addr = 9390698496", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 10", " s_axil_rdata = 2147483665", " m_axil_csr_awaddr = 7340588", " m_axil_csr_wdata = 2147483665", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7340588", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19502628504000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.client.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9502396736", " m_axis_ctrl_dma_read_desc_ram_addr = 2816", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 22", " m_axis_ctrl_dma_write_desc_dma_addr = 9515166240", " m_axis_ctrl_dma_write_desc_ram_addr = 736", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 23", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 29", " m_axis_data_dma_write_desc_dma_addr = 8542150656", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 10", " s_axil_rdata = 2147483651", " m_axil_csr_awaddr = 4194412", " m_axil_csr_wdata = 2147483651", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4194412", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19502627988000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "1", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.client.0."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65302", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 2014514851627", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.879917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.880917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.880917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.880917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.880917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.880917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.880917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.880917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.880917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.880917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.880917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.880917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.880917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.881917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.881917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.881917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.885916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.885916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.885916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.885916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.885916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.885916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.886916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.886916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.886916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.886916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.886916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.886916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.886916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.886916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.886916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.110882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.110882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.110882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.179871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 39476\r", "[ 5] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 39474\r", "[ 5.280248] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.2 sec 832 MBytes 681 Mbits/sec\r", "[ 6] 0.0-10.3 sec 832 MBytes 679 Mbits/sec\r", "[SUM] 0.0-10.3 sec 1.62 GBytes 1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 2014514841627. Starting simulation...", "info: Entering event queue @ 2014514851627. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 2014514851950. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65303", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1951406616034", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.877919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.878919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.879919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.879919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.879919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.879919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.879919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.879919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.879919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.879919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.879919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.879919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.879919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.879919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.879919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.879919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.884918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.884918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.884918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.884918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.884918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.884918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.884918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.884918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.884918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.884918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.884918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.884918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.884918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.109884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.109884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.109884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.178874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.2 port 39476 connected with 10.0.0.1 port 5001\r", "[ 4] local 10.0.0.2 port 39474 connected with 10.0.0.1 port 5001\r", "[ 4.614351] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 681 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 0.0-10.3 sec 832 MBytes 680 Mbits/sec\r", "[SUM] 0.0-10.3 sec 1.62 GBytes 1.36 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19502627973876 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1951406606034. Starting simulation...", "info: Entering event queue @ 1951406616034. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1951406616357. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}
\ No newline at end of file
results/paper_data/modetcp/modetcp-1-gt-cv-switch-4-0.json 0 → 100644
View file @ f60e7264
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