fixed import error + fixed name issue + fixed get unique latency method

experiments/simbricks/orchestration/simulation/base.py

@@ -106,9 +106,17 @@ class Simulator(utils_base.IdObj):
         sync_period = None
         run_sync = False
         for channel in channels:
-            sync_period = min(sync_period, channel.sync_period)
+            sync_period = (
+                min(sync_period, channel.sync_period)
+                if sync_period
+                else channel.sync_period
+            )
             run_sync = run_sync or channel._synchronized
-            latency = max(latency, channel.sys_channel.latency)
+            latency = (
+                max(latency, channel.sys_channel.latency)
+                if latency
+                else channel.sys_channel.latency
+            )
         if latency is None or sync_period is None:
             raise Exception("could not determine eth_latency and sync_period")
         return latency, sync_period, run_sync

experiments/simbricks/orchestration/simulation/host.py

@@ -60,12 +60,14 @@ class HostSim(sim_base.Simulator):
 class Gem5Sim(HostSim):
 
     def __init__(self, simulation: sim_base.Simulation):
-        super().__init__(simulation=simulation, executable="sims/external/gem5/build/X86/gem5", name=f"Gem5Sim-{self._id}")
+        super().__init__(simulation=simulation, executable="sims/external/gem5/build/X86/gem5")
+        self.name=f"Gem5Sim-{self._id}"
         self.cpu_type_cp = "X86KvmCPU"
         self.cpu_type = "TimingSimpleCPU"
-        self.extra_main_args: list[str] = []
-        self.extra_config_args: list[str] = []
-        self.variant = "fast"
+        self.extra_main_args: list[str] = [] # TODO
+        self.extra_config_args: list[str] = [] # TODO
+        self._variant: str = "fast"
+        self._sys_clock: str =  '1GHz' # TODO: move to system module
 
     def resreq_cores(self) -> int:
         return 1
@@ -97,19 +99,19 @@ class Gem5Sim(HostSim):
         if len(full_sys_hosts) != 1:
             raise Exception("Gem5Sim only supports simulating 1 FullSystemHost")
 
-        cmd = f"{inst.join_repo_base(f"{self._executable}.{self.variant}")} --outdir={inst.get_simmulator_output_dir(sim=self)} "
+        cmd = f"{inst.join_repo_base(f'{self._executable}.{self._variant}')} --outdir={inst.get_simmulator_output_dir(sim=self)} "
         cmd += " ".join(self.extra_main_args)
         cmd += (
-            f" {inst.join_repo_base("sims/external/gem5/configs/simbricks/simbricks.py")} --caches --l2cache "
+            f" {inst.join_repo_base('sims/external/gem5/configs/simbricks/simbricks.py')} --caches --l2cache "
             "--l1d_size=32kB --l1i_size=32kB --l2_size=32MB "
             "--l1d_assoc=8 --l1i_assoc=8 --l2_assoc=16 "
             f"--cacheline_size=64 --cpu-clock={full_sys_hosts[0].cpu_freq}"
-            f" --sys-clock={full_sys_hosts[0].sys_clock} " # TODO:FIXME
+            f" --sys-clock={self._sys_clock} "
             f"--checkpoint-dir={inst.cpdir_subdir(sim=self)} "
-            f"--kernel={inst.join_repo_base("images/vmlinux")} "
+            f"--kernel={inst.join_repo_base('images/vmlinux')} "
         )
         for disk in full_sys_hosts[0].disks:
-            cmd += f"--disk-image={disk.path(inst=inst, format="raw")} "
+            cmd += f"--disk-image={disk.path(inst=inst, format='raw')} "
         cmd += (
             f"--cpu-type={cpu_type} --mem-size={full_sys_hosts[0].memory}MB "
             f"--num-cpus={full_sys_hosts[0].cores} "

experiments/simbricks/orchestration/simulation/net/net_base.py

@@ -36,7 +36,7 @@ class NetSim(sim_base.Simulator):
         self,
         simulation: sim_base.Simulation,
         executable: str,
-        name: str,
+        name: str = "",
     ) -> None:
         super().__init__(simulation=simulation, executable=executable, name=name)
 
@@ -58,8 +58,8 @@ class WireNet(NetSim):
         super().__init__(
             simulation=simulation,
             executable="sims/net/wire/net_wire",
-            name=f"WireNet-{self._id}",
         )
+        self.name=f"WireNet-{self._id}"
         self._relative_pcap_file_path: str | None = relative_pcap_filepath
 
     def add(self, wire: eth.EthWire):
@@ -101,8 +101,8 @@ class SwitchNet(NetSim):
         super().__init__(
             simulation=simulation,
             executable=executable,
-            name=f"SwitchNet-{self._id}",
         )
+        self.name=f"SwitchNet-{self._id}"
         self._relative_pcap_file_path: str | None = relative_pcap_filepath
 
     def add(self, switch_spec: eth.EthSwitch):
@@ -151,7 +151,7 @@ class MemSwitchNet(SwitchNet):
             executable="sims/mem/memswitch/memswitch",
             relative_pcap_file_path=relative_pcap_file_path,
         )
-        self._name = f"MemSwitchNet-{self._id}"
+        self.name = f"MemSwitchNet-{self._id}"
         """AS_ID,VADDR_START,VADDR_END,MEMNODE_MAC,PHYS_START."""
         self.mem_map = []
 

experiments/simbricks/orchestration/simulation/pcidev.py

@@ -20,12 +20,14 @@
 # TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 # SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
-from simbricks.orchestration.system import base as sys_base
+from __future__ import annotations
+
+import typing as tp
 from simbricks.orchestration.system import pcie as sys_pcie
 from simbricks.orchestration.system import eth as sys_eth
 from simbricks.orchestration.system import nic as sys_nic
 from simbricks.orchestration.instantiation import base as inst_base
-from simbricks.orchestration.simulation import sim_base
+from simbricks.orchestration.simulation import base as sim_base
 
 
 class PCIDevSim(sim_base.Simulator):
@@ -50,7 +52,7 @@ class NICSim(PCIDevSim):
         return "nic." + self.name
 
     def __init__(
-        self, simulation: sim_base.Simulation, executable: str, name: str
+        self, simulation: sim_base.Simulation, executable: str, name: str = ""
     ) -> None:
         super().__init__(simulation=simulation, executable=executable, name=name)
 
@@ -97,8 +99,8 @@ class I40eNicSim(NICSim):
         super().__init__(
             simulation=simulation,
             executable="sims/nic/i40e_bm/i40e_bm",
-            name=f"NICSim-{self._id}",
         )
+        self.name=f"NICSim-{self._id}"
 
     def run_cmd(self, inst: inst_base.Instantiation) -> str:
         return super().run_cmd(inst=inst)
@@ -109,8 +111,8 @@ class CorundumBMNICSim(NICSim):
         super().__init__(
             simulation=simulation,
             executable="sims/nic/corundum_bm/corundum_bm",
-            name=f"CorundumBMNICSim-{self._id}",
         )
+        self.name=f"CorundumBMNICSim-{self._id}"
 
     def run_cmd(self, inst: inst_base.Instantiation) -> str:
         return super().run_cmd(inst=inst)
@@ -122,8 +124,8 @@ class CorundumVerilatorNICSim(NICSim):
         super().__init__(
             simulation=simulation,
             executable="sims/nic/corundum/corundum_verilator",
-            name=f"CorundumVerilatorNICSim-{self._id}",
         )
+        self.name=f"CorundumVerilatorNICSim-{self._id}"
         self.clock_freq = 250  # MHz
 
     def resreq_mem(self) -> int: