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"router/src/infer/v2/queue.rs" did not exist on "9b205d33cc349a96937204ad16ebc1a578ad619b"
Commit d4666c97 authored by Antoine Kaufmann's avatar Antoine Kaufmann
Browse files

Reformat closer to google style

parent eb125a88
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Showing with 3402 additions and 3685 deletions
lib/simbricks/netif/netsim.c
View file @ d4666c97
......@@ -22,21 +22,21 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <sys/socket.h>
#include <unistd.h>
#include <simbricks/netif/netsim.h>
#include "lib/simbricks/netif/internal.h"
static uint64_t current_epoch = 0;
int netsim_init(struct netsim_interface *nsif,
const char *eth_socket_path, int *sync_eth)
{
int netsim_init(struct netsim_interface *nsif, const char *eth_socket_path,
int *sync_eth) {
struct cosim_eth_proto_dev_intro di;
struct cosim_eth_proto_net_intro ni;
int cfd, shm_fd;
......@@ -72,8 +72,8 @@ int netsim_init(struct netsim_interface *nsif,
nsif->sync = *sync_eth;
}
nsif->d2n_queue = (uint8_t *) p + di.d2n_offset;
nsif->n2d_queue = (uint8_t *) p + di.n2d_offset;
nsif->d2n_queue = (uint8_t *)p + di.d2n_offset;
nsif->n2d_queue = (uint8_t *)p + di.n2d_offset;
nsif->d2n_elen = di.d2n_elen;
nsif->n2d_elen = di.n2d_elen;
nsif->d2n_enum = di.d2n_nentries;
......@@ -84,18 +84,16 @@ int netsim_init(struct netsim_interface *nsif,
return 0;
}
void netsim_cleanup(struct netsim_interface *nsif)
{
void netsim_cleanup(struct netsim_interface *nsif) {
fprintf(stderr, "netsim_cleanup: TODO\n");
abort();
}
volatile union cosim_eth_proto_d2n *netsim_d2n_poll(
struct netsim_interface *nsif, uint64_t timestamp)
{
struct netsim_interface *nsif, uint64_t timestamp) {
volatile union cosim_eth_proto_d2n *msg =
(volatile union cosim_eth_proto_d2n *)
(nsif->d2n_queue + nsif->d2n_pos * nsif->d2n_elen);
(volatile union cosim_eth_proto_d2n *)(nsif->d2n_queue +
nsif->d2n_pos * nsif->d2n_elen);
/* message not ready */
if ((msg->dummy.own_type & COSIM_ETH_PROTO_D2N_OWN_MASK) !=
......@@ -112,23 +110,19 @@ volatile union cosim_eth_proto_d2n *netsim_d2n_poll(
}
void netsim_d2n_done(struct netsim_interface *nsif,
volatile union cosim_eth_proto_d2n *msg)
{
msg->dummy.own_type = (msg->dummy.own_type & COSIM_ETH_PROTO_D2N_MSG_MASK)
| COSIM_ETH_PROTO_D2N_OWN_DEV;
volatile union cosim_eth_proto_d2n *msg) {
msg->dummy.own_type = (msg->dummy.own_type & COSIM_ETH_PROTO_D2N_MSG_MASK) |
COSIM_ETH_PROTO_D2N_OWN_DEV;
}
volatile union cosim_eth_proto_n2d *netsim_n2d_alloc(
struct netsim_interface *nsif, uint64_t timestamp,
uint64_t latency)
{
struct netsim_interface *nsif, uint64_t timestamp, uint64_t latency) {
volatile union cosim_eth_proto_n2d *msg =
(volatile union cosim_eth_proto_n2d *)
(nsif->n2d_queue + nsif->n2d_pos * nsif->n2d_elen);
(volatile union cosim_eth_proto_n2d *)(nsif->n2d_queue +
nsif->n2d_pos * nsif->n2d_elen);
if ((msg->dummy.own_type & COSIM_ETH_PROTO_N2D_OWN_MASK) !=
COSIM_ETH_PROTO_N2D_OWN_NET)
{
COSIM_ETH_PROTO_N2D_OWN_NET) {
return NULL;
}
......@@ -140,8 +134,7 @@ volatile union cosim_eth_proto_n2d *netsim_n2d_alloc(
}
int netsim_n2d_sync(struct netsim_interface *nsif, uint64_t timestamp,
uint64_t latency, uint64_t sync_delay, int sync_mode)
{
uint64_t latency, uint64_t sync_delay, int sync_mode) {
volatile union cosim_eth_proto_n2d *msg;
volatile struct cosim_eth_proto_n2d_sync *sync;
int do_sync;
......@@ -155,8 +148,7 @@ int netsim_n2d_sync(struct netsim_interface *nsif, uint64_t timestamp,
timestamp - nsif->n2d_timestamp >= sync_delay;
break;
case SYNC_BARRIER:
do_sync = current_epoch == 0 ||
timestamp - current_epoch >= sync_delay;
do_sync = current_epoch == 0 || timestamp - current_epoch >= sync_delay;
break;
default:
fprintf(stderr, "unsupported sync mode=%u\n", sync_mode);
......@@ -179,8 +171,7 @@ int netsim_n2d_sync(struct netsim_interface *nsif, uint64_t timestamp,
}
void netsim_advance_epoch(uint64_t timestamp, uint64_t sync_delay,
int sync_mode)
{
int sync_mode) {
if (sync_mode == SYNC_BARRIER) {
if (timestamp - current_epoch >= sync_delay) {
current_epoch = timestamp;
......@@ -189,14 +180,14 @@ void netsim_advance_epoch(uint64_t timestamp, uint64_t sync_delay,
}
uint64_t netsim_advance_time(uint64_t timestamp, uint64_t sync_delay,
int sync_mode)
{
int sync_mode) {
switch (sync_mode) {
case SYNC_MODES:
return timestamp;
case SYNC_BARRIER:
return timestamp < current_epoch + sync_delay ?
timestamp : current_epoch + sync_delay;
return timestamp < current_epoch + sync_delay
? timestamp
: current_epoch + sync_delay;
default:
fprintf(stderr, "unsupported sync mode=%u\n", sync_mode);
return timestamp;
......
lib/simbricks/netif/netsim.h
View file @ d4666c97
......@@ -27,6 +27,7 @@
#include <stddef.h>
#include <stdint.h>
#include <simbricks/proto/network.h>
#define SYNC_MODES 0
......@@ -48,22 +49,20 @@ struct netsim_interface {
int sync;
};
int netsim_init(struct netsim_interface *nsif,
const char *eth_socket_path, int *sync_eth);
int netsim_init(struct netsim_interface *nsif, const char *eth_socket_path,
int *sync_eth);
void netsim_cleanup(struct netsim_interface *nsif);
volatile union cosim_eth_proto_d2n *netsim_d2n_poll(
struct netsim_interface *nsif, uint64_t timestamp);
void netsim_d2n_done(struct netsim_interface *nsif,
volatile union cosim_eth_proto_d2n *msg);
static inline uint64_t netsim_d2n_timestamp(struct netsim_interface *nsif)
{
static inline uint64_t netsim_d2n_timestamp(struct netsim_interface *nsif) {
return nsif->d2n_timestamp;
}
volatile union cosim_eth_proto_n2d *netsim_n2d_alloc(
struct netsim_interface *nsif, uint64_t timestamp,
uint64_t latency);
struct netsim_interface *nsif, uint64_t timestamp, uint64_t latency);
int netsim_n2d_sync(struct netsim_interface *nsif, uint64_t timestamp,
uint64_t latency, uint64_t sync_delay, int sync_mode);
void netsim_advance_epoch(uint64_t timestamp, uint64_t sync_delay,
......
lib/simbricks/netif/utils.c
View file @ d4666c97
......@@ -24,20 +24,19 @@
#include <fcntl.h>
#include <pthread.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <sys/un.h>
#include <sys/socket.h>
#include <sys/stat.h>
#include <sys/un.h>
#include <unistd.h>
#include "lib/simbricks/netif/internal.h"
int uxsocket_connect(const char *path)
{
int uxsocket_connect(const char *path) {
int fd;
struct sockaddr_un saun;
......@@ -51,7 +50,7 @@ int uxsocket_connect(const char *path)
return -1;
}
if (connect(fd, (struct sockaddr *) &saun, sizeof(saun)) != 0) {
if (connect(fd, (struct sockaddr *)&saun, sizeof(saun)) != 0) {
perror("connect failed");
return -1;
}
......@@ -59,8 +58,7 @@ int uxsocket_connect(const char *path)
return fd;
}
int uxsocket_recv(int fd, void *data, size_t len, int *pfd)
{
int uxsocket_recv(int fd, void *data, size_t len, int *pfd) {
int *ppfd;
ssize_t ret;
struct cmsghdr *cmsg;
......@@ -82,13 +80,13 @@ int uxsocket_recv(int fd, void *data, size_t len, int *pfd)
.msg_flags = 0,
};
if ((ret = recvmsg(fd, &msg, 0)) != (ssize_t) len) {
if ((ret = recvmsg(fd, &msg, 0)) != (ssize_t)len) {
perror("recvmsg failed");
return -1;
}
cmsg = CMSG_FIRSTHDR(&msg);
ppfd = (int *) CMSG_DATA(cmsg);
ppfd = (int *)CMSG_DATA(cmsg);
if (msg.msg_controllen <= 0 || cmsg->cmsg_len != CMSG_LEN(sizeof(int))) {
fprintf(stderr, "accessing ancillary data failed\n");
return -1;
......@@ -98,8 +96,7 @@ int uxsocket_recv(int fd, void *data, size_t len, int *pfd)
return 0;
}
void *shm_map(int shm_fd)
{
void *shm_map(int shm_fd) {
void *p;
struct stat statbuf;
......
lib/simbricks/nicbm/nicbm.cc
View file @ d4666c97
......@@ -22,42 +22,38 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <simbricks/nicbm/nicbm.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <unistd.h>
#include <signal.h>
#include <cassert>
#include <ctime>
#include <iostream>
#include <simbricks/nicbm/nicbm.h>
// #define DEBUG_NICBM 1
#define DMA_MAX_PENDING 64
using namespace nicbm;
namespace nicbm {
static volatile int exiting = 0;
static uint64_t main_time = 0;
static void sigint_handler(int dummy)
{
static void sigint_handler(int dummy) {
exiting = 1;
}
static void sigusr1_handler(int dummy)
{
static void sigusr1_handler(int dummy) {
fprintf(stderr, "main_time = %lu\n", main_time);
}
volatile union cosim_pcie_proto_d2h *Runner::d2h_alloc(void)
{
volatile union cosim_pcie_proto_d2h *Runner::d2h_alloc(void) {
volatile union cosim_pcie_proto_d2h *msg;
while ((msg = nicsim_d2h_alloc(&nsparams, main_time)) == NULL) {
fprintf(stderr, "d2h_alloc: no entry available\n");
......@@ -65,8 +61,7 @@ volatile union cosim_pcie_proto_d2h *Runner::d2h_alloc(void)
return msg;
}
volatile union cosim_eth_proto_d2n *Runner::d2n_alloc(void)
{
volatile union cosim_eth_proto_d2n *Runner::d2n_alloc(void) {
volatile union cosim_eth_proto_d2n *msg;
while ((msg = nicsim_d2n_alloc(&nsparams, main_time)) == NULL) {
fprintf(stderr, "d2n_alloc: no entry available\n");
......@@ -74,8 +69,7 @@ volatile union cosim_eth_proto_d2n *Runner::d2n_alloc(void)
return msg;
}
void Runner::issue_dma(DMAOp &op)
{
void Runner::issue_dma(DMAOp &op) {
if (dma_pending < DMA_MAX_PENDING) {
// can directly issue
#ifdef DEBUG_NICBM
......@@ -92,8 +86,7 @@ void Runner::issue_dma(DMAOp &op)
}
}
void Runner::dma_trigger()
{
void Runner::dma_trigger() {
if (dma_queue.empty() || dma_pending == DMA_MAX_PENDING)
return;
......@@ -103,8 +96,7 @@ void Runner::dma_trigger()
dma_do(*op);
}
void Runner::dma_do(DMAOp &op)
{
void Runner::dma_do(DMAOp &op) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
dma_pending++;
#ifdef DEBUG_NICBM
......@@ -115,39 +107,42 @@ void Runner::dma_do(DMAOp &op)
if (op.write) {
volatile struct cosim_pcie_proto_d2h_write *write = &msg->write;
if (dintro.d2h_elen < sizeof(*write) + op.len) {
fprintf(stderr, "issue_dma: write too big (%zu), can only fit up "
"to (%zu)\n", op.len, dintro.d2h_elen - sizeof(*write));
fprintf(stderr,
"issue_dma: write too big (%zu), can only fit up "
"to (%zu)\n",
op.len, dintro.d2h_elen - sizeof(*write));
abort();
}
write->req_id = (uintptr_t) &op;
write->req_id = (uintptr_t)&op;
write->offset = op.dma_addr;
write->len = op.len;
memcpy((void *)write->data, (void *)op.data, op.len);
// WMB();
write->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITE |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
write->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITE | COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else {
volatile struct cosim_pcie_proto_d2h_read *read = &msg->read;
if (dintro.h2d_elen < sizeof(struct cosim_pcie_proto_h2d_readcomp) +
op.len) {
fprintf(stderr, "issue_dma: write too big (%zu), can only fit up "
"to (%zu)\n", op.len, dintro.h2d_elen -
sizeof(struct cosim_pcie_proto_h2d_readcomp));
if (dintro.h2d_elen <
sizeof(struct cosim_pcie_proto_h2d_readcomp) + op.len) {
fprintf(stderr,
"issue_dma: write too big (%zu), can only fit up "
"to (%zu)\n",
op.len,
dintro.h2d_elen - sizeof(struct cosim_pcie_proto_h2d_readcomp));
abort();
}
read->req_id = (uintptr_t) &op;
read->req_id = (uintptr_t)&op;
read->offset = op.dma_addr;
read->len = op.len;
// WMB();
read->own_type = COSIM_PCIE_PROTO_D2H_MSG_READ |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
read->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READ | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
}
void Runner::msi_issue(uint8_t vec)
{
void Runner::msi_issue(uint8_t vec) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
#ifdef DEBUG_NICBM
printf("nicbm: issue MSI interrupt vec %u\n", vec);
......@@ -157,12 +152,11 @@ void Runner::msi_issue(uint8_t vec)
intr->inttype = COSIM_PCIE_PROTO_INT_MSI;
// WMB();
intr->own_type = COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
intr->own_type =
COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
void Runner::msix_issue(uint8_t vec)
{
void Runner::msix_issue(uint8_t vec) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
#ifdef DEBUG_NICBM
printf("nicbm: issue MSI-X interrupt vec %u\n", vec);
......@@ -172,45 +166,41 @@ void Runner::msix_issue(uint8_t vec)
intr->inttype = COSIM_PCIE_PROTO_INT_MSIX;
// WMB();
intr->own_type = COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
intr->own_type =
COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
void Runner::event_schedule(TimedEvent &evt)
{
void Runner::event_schedule(TimedEvent &evt) {
events.insert(&evt);
}
void Runner::event_cancel(TimedEvent &evt)
{
void Runner::event_cancel(TimedEvent &evt) {
events.erase(&evt);
}
void Runner::h2d_read(volatile struct cosim_pcie_proto_h2d_read *read)
{
void Runner::h2d_read(volatile struct cosim_pcie_proto_h2d_read *read) {
volatile union cosim_pcie_proto_d2h *msg;
volatile struct cosim_pcie_proto_d2h_readcomp *rc;
msg = d2h_alloc();
rc = &msg->readcomp;
dev.reg_read(read->bar, read->offset, (void *) rc->data, read->len);
dev.reg_read(read->bar, read->offset, (void *)rc->data, read->len);
rc->req_id = read->req_id;
#ifdef DEBUG_NICBM
uint64_t dbg_val = 0;
memcpy(&dbg_val, (const void *) rc->data, read->len <= 8 ? read->len : 8);
printf("nicbm: read(off=0x%lx, len=%u, val=0x%lx)\n", read->offset,
read->len, dbg_val);
memcpy(&dbg_val, (const void *)rc->data, read->len <= 8 ? read->len : 8);
printf("nicbm: read(off=0x%lx, len=%u, val=0x%lx)\n", read->offset, read->len,
dbg_val);
#endif
// WMB();
rc->own_type = COSIM_PCIE_PROTO_D2H_MSG_READCOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
rc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READCOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
void Runner::h2d_write(volatile struct cosim_pcie_proto_h2d_write *write)
{
void Runner::h2d_write(volatile struct cosim_pcie_proto_h2d_write *write) {
volatile union cosim_pcie_proto_d2h *msg;
volatile struct cosim_pcie_proto_d2h_writecomp *wc;
......@@ -219,26 +209,24 @@ void Runner::h2d_write(volatile struct cosim_pcie_proto_h2d_write *write)
#ifdef DEBUG_NICBM
uint64_t dbg_val = 0;
memcpy(&dbg_val, (const void *) write->data, write->len <= 8 ? write->len :
8);
memcpy(&dbg_val, (const void *)write->data, write->len <= 8 ? write->len : 8);
printf("nicbm: write(off=0x%lx, len=%u, val=0x%lx)\n", write->offset,
write->len, dbg_val);
#endif
dev.reg_write(write->bar, write->offset, (void *) write->data, write->len);
dev.reg_write(write->bar, write->offset, (void *)write->data, write->len);
wc->req_id = write->req_id;
// WMB();
wc->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
wc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
void Runner::h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc)
{
void Runner::h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc) {
DMAOp *op = (DMAOp *)(uintptr_t)rc->req_id;
#ifdef DEBUG_NICBM
printf("nicbm: completed dma read op %p addr %lx len %zu\n", op,
op->dma_addr, op->len);
printf("nicbm: completed dma read op %p addr %lx len %zu\n", op, op->dma_addr,
op->len);
#endif
memcpy(op->data, (void *)rc->data, op->len);
......@@ -248,8 +236,7 @@ void Runner::h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc)
dma_trigger();
}
void Runner::h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc)
{
void Runner::h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc) {
DMAOp *op = (DMAOp *)(uintptr_t)wc->req_id;
#ifdef DEBUG_NICBM
......@@ -263,22 +250,19 @@ void Runner::h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc)
dma_trigger();
}
void Runner::h2d_devctrl(volatile struct cosim_pcie_proto_h2d_devctrl *dc)
{
dev.devctrl_update(*(struct cosim_pcie_proto_h2d_devctrl *) dc);
void Runner::h2d_devctrl(volatile struct cosim_pcie_proto_h2d_devctrl *dc) {
dev.devctrl_update(*(struct cosim_pcie_proto_h2d_devctrl *)dc);
}
void Runner::eth_recv(volatile struct cosim_eth_proto_n2d_recv *recv)
{
void Runner::eth_recv(volatile struct cosim_eth_proto_n2d_recv *recv) {
#ifdef DEBUG_NICBM
printf("nicbm: eth rx: port %u len %u\n", recv->port, recv->len);
#endif
dev.eth_rx(recv->port, (void *) recv->data, recv->len);
dev.eth_rx(recv->port, (void *)recv->data, recv->len);
}
void Runner::eth_send(const void *data, size_t len)
{
void Runner::eth_send(const void *data, size_t len) {
#ifdef DEBUG_NICBM
printf("nicbm: eth tx: len %zu\n", len);
#endif
......@@ -288,12 +272,10 @@ void Runner::eth_send(const void *data, size_t len)
send->port = 0; // single port
send->len = len;
memcpy((void *)send->data, data, len);
send->own_type = COSIM_ETH_PROTO_D2N_MSG_SEND |
COSIM_ETH_PROTO_D2N_OWN_NET;
send->own_type = COSIM_ETH_PROTO_D2N_MSG_SEND | COSIM_ETH_PROTO_D2N_OWN_NET;
}
void Runner::poll_h2d()
{
void Runner::poll_h2d() {
volatile union cosim_pcie_proto_h2d *msg =
nicif_h2d_poll(&nsparams, main_time);
uint8_t type;
......@@ -334,8 +316,7 @@ void Runner::poll_h2d()
nicif_h2d_next();
}
void Runner::poll_n2d()
{
void Runner::poll_n2d() {
volatile union cosim_eth_proto_n2d *msg =
nicif_n2d_poll(&nsparams, main_time);
uint8_t t;
......@@ -360,18 +341,15 @@ void Runner::poll_n2d()
nicif_n2d_next();
}
uint64_t Runner::time_ps() const
{
uint64_t Runner::time_ps() const {
return main_time;
}
uint64_t Runner::get_mac_addr() const
{
uint64_t Runner::get_mac_addr() const {
return mac_addr;
}
bool Runner::event_next(uint64_t &retval)
{
bool Runner::event_next(uint64_t &retval) {
if (events.empty())
return false;
......@@ -379,8 +357,7 @@ bool Runner::event_next(uint64_t &retval)
return true;
}
void Runner::event_trigger()
{
void Runner::event_trigger() {
auto it = events.begin();
if (it == events.end())
return;
......@@ -395,9 +372,7 @@ void Runner::event_trigger()
dev.timed_event(*ev);
}
Runner::Runner(Device &dev_)
: dev(dev_), events(event_cmp())
{
Runner::Runner(Device &dev_) : dev(dev_), events(event_cmp()) {
// mac_addr = lrand48() & ~(3ULL << 46);
dma_pending = 0;
srand48(time(NULL) ^ getpid());
......@@ -409,8 +384,7 @@ Runner::Runner(Device &dev_)
std::cerr << std::hex << mac_addr << std::endl;
}
int Runner::runMain(int argc, char *argv[])
{
int Runner::runMain(int argc, char *argv[]) {
uint64_t next_ts;
uint64_t max_step = 10000;
uint64_t sync_period = 100 * 1000ULL;
......@@ -419,7 +393,8 @@ int Runner::runMain(int argc, char *argv[])
int sync_mode = SYNC_MODES;
if (argc < 4 && argc > 9) {
fprintf(stderr, "Usage: corundum_bm PCI-SOCKET ETH-SOCKET "
fprintf(stderr,
"Usage: corundum_bm PCI-SOCKET ETH-SOCKET "
"SHM [SYNC-MODE] [START-TICK] [SYNC-PERIOD] [PCI-LATENCY] "
"[ETH-LATENCY]\n");
return EXIT_FAILURE;
......@@ -491,14 +466,14 @@ int Runner::runMain(int argc, char *argv[])
return 0;
}
void Runner::Device::timed_event(TimedEvent &te)
{
void Runner::Device::timed_event(TimedEvent &te) {
}
void Runner::Device::devctrl_update(
struct cosim_pcie_proto_h2d_devctrl &devctrl)
{
struct cosim_pcie_proto_h2d_devctrl &devctrl) {
int_intx_en = devctrl.flags & COSIM_PCIE_PROTO_CTRL_INTX_EN;
int_msi_en = devctrl.flags & COSIM_PCIE_PROTO_CTRL_MSI_EN;
int_msix_en = devctrl.flags & COSIM_PCIE_PROTO_CTRL_MSIX_EN;
}
} // namespace nicbm
lib/simbricks/nicbm/nicbm.h
View file @ d4666c97
......@@ -27,10 +27,11 @@
#include <cassert>
#include <cstring>
#include <set>
#include <deque>
#include <set>
extern "C" {
#include <simbricks/nicif/nicsim.h>
#include <simbricks/nicif/nicsim.h>
}
namespace nicbm {
......@@ -39,7 +40,8 @@ static const size_t MAX_DMA_LEN = 2048;
class DMAOp {
public:
virtual ~DMAOp() { }
virtual ~DMAOp() {
}
bool write;
uint64_t dma_addr;
size_t len;
......@@ -48,11 +50,11 @@ class DMAOp {
class TimedEvent {
public:
virtual ~TimedEvent() { }
virtual ~TimedEvent() {
}
uint64_t time;
};
/**
* The Runner drives the main simulation loop. It's initialized with a reference
* to a device it should manage, and then once `runMain` is called, it will
......@@ -72,8 +74,7 @@ class Runner {
* Initialize device specific parameters (pci dev/vendor id,
* BARs etc. in intro struct.
*/
virtual void setup_intro(struct cosim_pcie_proto_dev_intro &di)
= 0;
virtual void setup_intro(struct cosim_pcie_proto_dev_intro &di) = 0;
/**
* execute a register read from `bar`:`addr` of length `len`.
......@@ -86,8 +87,8 @@ class Runner {
* execute a register write to `bar`:`addr` of length `len`,
* with the data in `src`.
*/
virtual void reg_write(uint8_t bar, uint64_t addr,
const void *src, size_t len) = 0;
virtual void reg_write(uint8_t bar, uint64_t addr, const void *src,
size_t len) = 0;
/**
* the previously issued DMA operation `op` completed.
......@@ -98,8 +99,7 @@ class Runner {
* A packet has arrived on the wire, of length `len` with
* payload `data`.
*/
virtual void eth_rx(uint8_t port, const void *data, size_t len)
= 0;
virtual void eth_rx(uint8_t port, const void *data, size_t len) = 0;
/**
* A timed event is due.
......@@ -109,14 +109,12 @@ class Runner {
/**
* Device control update
*/
virtual void devctrl_update(
struct cosim_pcie_proto_h2d_devctrl &devctrl);
virtual void devctrl_update(struct cosim_pcie_proto_h2d_devctrl &devctrl);
};
protected:
struct event_cmp {
bool operator() (TimedEvent *a, TimedEvent *b)
{
bool operator()(TimedEvent *a, TimedEvent *b) {
return a->time < b->time;
}
};
......@@ -176,17 +174,14 @@ class SimpleDevice : public Runner::Device {
virtual TReg reg_read(uint8_t bar, uint64_t addr) = 0;
virtual void reg_write(uint8_t bar, uint64_t addr, TReg val) = 0;
virtual void reg_read(uint8_t bar, uint64_t addr, void *dest,
size_t len)
{
virtual void reg_read(uint8_t bar, uint64_t addr, void *dest, size_t len) {
assert(len == sizeof(TReg));
TReg r = reg_read(bar, addr);
memcpy(dest, &r, sizeof(r));
}
virtual void reg_write(uint8_t bar, uint64_t addr,
const void *src, size_t len)
{
virtual void reg_write(uint8_t bar, uint64_t addr, const void *src,
size_t len) {
assert(len == sizeof(TReg));
TReg r;
memcpy(&r, src, sizeof(r));
......
lib/simbricks/nicif/nicsim.c
View file @ d4666c97
......@@ -22,11 +22,11 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <poll.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <poll.h>
#include <unistd.h>
#include <simbricks/nicif/nicsim.h>
......@@ -45,7 +45,6 @@
#define N2D_ELEN (9024 + 64)
#define N2D_ENUM 8192
static uint8_t *d2h_queue;
static size_t d2h_pos;
static size_t d2h_off; /* offset in shm region */
......@@ -74,8 +73,7 @@ static int pci_cfd = -1;
static int eth_cfd = -1;
static int accept_pci(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
int *sync_pci)
{
int *sync_pci) {
if ((pci_cfd = accept(pci_lfd, NULL, NULL)) < 0) {
return -1;
}
......@@ -93,7 +91,7 @@ static int accept_pci(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
if (*sync_pci)
di->flags |= COSIM_PCIE_PROTO_FLAGS_DI_SYNC;
else
di->flags &= ~((uint64_t) COSIM_PCIE_PROTO_FLAGS_DI_SYNC);
di->flags &= ~((uint64_t)COSIM_PCIE_PROTO_FLAGS_DI_SYNC);
if (uxsocket_send(pci_cfd, di, sizeof(*di), shm_fd)) {
return -1;
......@@ -102,8 +100,7 @@ static int accept_pci(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
return 0;
}
static int accept_eth(int eth_lfd, int *sync_eth)
{
static int accept_eth(int eth_lfd, int *sync_eth) {
struct cosim_eth_proto_dev_intro di;
if ((eth_cfd = accept(eth_lfd, NULL, NULL)) < 0) {
......@@ -132,9 +129,8 @@ static int accept_eth(int eth_lfd, int *sync_eth)
return 0;
}
static int accept_conns(struct cosim_pcie_proto_dev_intro *di,
int pci_lfd, int *sync_pci, int eth_lfd, int *sync_eth)
{
static int accept_conns(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
int *sync_pci, int eth_lfd, int *sync_eth) {
struct pollfd pfds[2];
int await_pci = pci_lfd != -1;
int await_eth = eth_lfd != -1;
......@@ -181,32 +177,27 @@ static int accept_conns(struct cosim_pcie_proto_dev_intro *di,
}
int nicsim_init(struct nicsim_params *params,
struct cosim_pcie_proto_dev_intro *di)
{
struct cosim_pcie_proto_dev_intro *di) {
int pci_lfd = -1, eth_lfd = -1;
void *shmptr;
size_t shm_size;
/* ready in memory queues */
shm_size = (uint64_t) D2H_ELEN * D2H_ENUM +
(uint64_t) H2D_ELEN * H2D_ENUM +
(uint64_t) D2N_ELEN * D2N_ENUM +
(uint64_t) N2D_ELEN * N2D_ENUM;
if ((shm_fd = shm_create(params->shm_path, shm_size, &shmptr))
< 0)
{
shm_size = (uint64_t)D2H_ELEN * D2H_ENUM + (uint64_t)H2D_ELEN * H2D_ENUM +
(uint64_t)D2N_ELEN * D2N_ENUM + (uint64_t)N2D_ELEN * N2D_ENUM;
if ((shm_fd = shm_create(params->shm_path, shm_size, &shmptr)) < 0) {
return -1;
}
d2h_off = 0;
h2d_off = d2h_off + (uint64_t) D2H_ELEN * D2H_ENUM;
d2n_off = h2d_off + (uint64_t) H2D_ELEN * H2D_ENUM;
n2d_off = d2n_off + (uint64_t) D2N_ELEN * D2N_ENUM;
h2d_off = d2h_off + (uint64_t)D2H_ELEN * D2H_ENUM;
d2n_off = h2d_off + (uint64_t)H2D_ELEN * H2D_ENUM;
n2d_off = d2n_off + (uint64_t)D2N_ELEN * D2N_ENUM;
d2h_queue = (uint8_t *) shmptr + d2h_off;
h2d_queue = (uint8_t *) shmptr + h2d_off;
d2n_queue = (uint8_t *) shmptr + d2n_off;
n2d_queue = (uint8_t *) shmptr + n2d_off;
d2h_queue = (uint8_t *)shmptr + d2h_off;
h2d_queue = (uint8_t *)shmptr + h2d_off;
d2n_queue = (uint8_t *)shmptr + d2n_off;
n2d_queue = (uint8_t *)shmptr + n2d_off;
d2h_pos = h2d_pos = d2n_pos = n2d_pos = 0;
......@@ -224,8 +215,7 @@ int nicsim_init(struct nicsim_params *params,
/* accept connection fds */
if (accept_conns(di, pci_lfd, &params->sync_pci, eth_lfd,
&params->sync_eth) != 0)
{
&params->sync_eth) != 0) {
return -1;
}
......@@ -252,8 +242,7 @@ int nicsim_init(struct nicsim_params *params,
return 0;
}
void nicsim_cleanup(void)
{
void nicsim_cleanup(void) {
close(pci_cfd);
close(eth_cfd);
}
......@@ -261,8 +250,7 @@ void nicsim_cleanup(void)
/******************************************************************************/
/* Sync */
int nicsim_sync(struct nicsim_params *params, uint64_t timestamp)
{
int nicsim_sync(struct nicsim_params *params, uint64_t timestamp) {
int ret = 0;
volatile union cosim_pcie_proto_d2h *d2h;
volatile union cosim_eth_proto_d2n *d2n;
......@@ -284,14 +272,13 @@ int nicsim_sync(struct nicsim_params *params, uint64_t timestamp)
return ret;
}
if (sync)
{
if (sync) {
d2h = nicsim_d2h_alloc(params, timestamp);
if (d2h == NULL) {
ret = -1;
} else {
d2h->sync.own_type = COSIM_PCIE_PROTO_D2H_MSG_SYNC |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
d2h->sync.own_type =
COSIM_PCIE_PROTO_D2H_MSG_SYNC | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
}
}
......@@ -313,14 +300,13 @@ int nicsim_sync(struct nicsim_params *params, uint64_t timestamp)
return ret;
}
if (sync)
{
if (sync) {
d2n = nicsim_d2n_alloc(params, timestamp);
if (d2n == NULL) {
ret = -1;
} else {
d2n->sync.own_type = COSIM_ETH_PROTO_D2N_MSG_SYNC |
COSIM_ETH_PROTO_D2N_OWN_NET;
d2n->sync.own_type =
COSIM_ETH_PROTO_D2N_MSG_SYNC | COSIM_ETH_PROTO_D2N_OWN_NET;
}
}
}
......@@ -328,8 +314,7 @@ int nicsim_sync(struct nicsim_params *params, uint64_t timestamp)
return ret;
}
void nicsim_advance_epoch(struct nicsim_params *params, uint64_t timestamp)
{
void nicsim_advance_epoch(struct nicsim_params *params, uint64_t timestamp) {
if (params->sync_mode == SYNC_BARRIER) {
if ((params->sync_pci || params->sync_eth) &&
timestamp - current_epoch >= params->sync_delay) {
......@@ -338,25 +323,24 @@ void nicsim_advance_epoch(struct nicsim_params *params, uint64_t timestamp)
}
}
uint64_t nicsim_advance_time(struct nicsim_params *params, uint64_t timestamp)
{
uint64_t nicsim_advance_time(struct nicsim_params *params, uint64_t timestamp) {
switch (params->sync_mode) {
case SYNC_MODES:
return timestamp;
case SYNC_BARRIER:
return timestamp < current_epoch + params->sync_delay ?
timestamp : current_epoch + params->sync_delay;
return timestamp < current_epoch + params->sync_delay
? timestamp
: current_epoch + params->sync_delay;
default:
fprintf(stderr, "unsupported sync mode=%u\n", params->sync_mode);
return timestamp;
}
}
uint64_t nicsim_next_timestamp(struct nicsim_params *params)
{
uint64_t nicsim_next_timestamp(struct nicsim_params *params) {
if (params->sync_pci && params->sync_eth) {
return (pci_last_rx_time <= eth_last_rx_time ? pci_last_rx_time :
eth_last_rx_time);
return (pci_last_rx_time <= eth_last_rx_time ? pci_last_rx_time
: eth_last_rx_time);
} else if (params->sync_pci) {
return pci_last_rx_time;
} else if (params->sync_eth) {
......@@ -370,11 +354,9 @@ uint64_t nicsim_next_timestamp(struct nicsim_params *params)
/* PCI */
volatile union cosim_pcie_proto_h2d *nicif_h2d_poll(
struct nicsim_params *params, uint64_t timestamp)
{
struct nicsim_params *params, uint64_t timestamp) {
volatile union cosim_pcie_proto_h2d *msg =
(volatile union cosim_pcie_proto_h2d *)
(h2d_queue + h2d_pos * H2D_ELEN);
(volatile union cosim_pcie_proto_h2d *)(h2d_queue + h2d_pos * H2D_ELEN);
/* message not ready */
if ((msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_OWN_MASK) !=
......@@ -389,27 +371,22 @@ volatile union cosim_pcie_proto_h2d *nicif_h2d_poll(
return msg;
}
void nicif_h2d_done(volatile union cosim_pcie_proto_h2d *msg)
{
msg->dummy.own_type = (msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_MSG_MASK)
| COSIM_PCIE_PROTO_H2D_OWN_HOST;
void nicif_h2d_done(volatile union cosim_pcie_proto_h2d *msg) {
msg->dummy.own_type = (msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_MSG_MASK) |
COSIM_PCIE_PROTO_H2D_OWN_HOST;
}
void nicif_h2d_next(void)
{
void nicif_h2d_next(void) {
h2d_pos = (h2d_pos + 1) % H2D_ENUM;
}
volatile union cosim_pcie_proto_d2h *nicsim_d2h_alloc(
struct nicsim_params *params, uint64_t timestamp)
{
struct nicsim_params *params, uint64_t timestamp) {
volatile union cosim_pcie_proto_d2h *msg =
(volatile union cosim_pcie_proto_d2h *)
(d2h_queue + d2h_pos * D2H_ELEN);
(volatile union cosim_pcie_proto_d2h *)(d2h_queue + d2h_pos * D2H_ELEN);
if ((msg->dummy.own_type & COSIM_PCIE_PROTO_D2H_OWN_MASK) !=
COSIM_PCIE_PROTO_D2H_OWN_DEV)
{
COSIM_PCIE_PROTO_D2H_OWN_DEV) {
return NULL;
}
......@@ -423,12 +400,10 @@ volatile union cosim_pcie_proto_d2h *nicsim_d2h_alloc(
/******************************************************************************/
/* Ethernet */
volatile union cosim_eth_proto_n2d *nicif_n2d_poll(
struct nicsim_params *params, uint64_t timestamp)
{
volatile union cosim_eth_proto_n2d *nicif_n2d_poll(struct nicsim_params *params,
uint64_t timestamp) {
volatile union cosim_eth_proto_n2d *msg =
(volatile union cosim_eth_proto_n2d *)
(n2d_queue + n2d_pos * N2D_ELEN);
(volatile union cosim_eth_proto_n2d *)(n2d_queue + n2d_pos * N2D_ELEN);
/* message not ready */
if ((msg->dummy.own_type & COSIM_ETH_PROTO_N2D_OWN_MASK) !=
......@@ -443,27 +418,22 @@ volatile union cosim_eth_proto_n2d *nicif_n2d_poll(
return msg;
}
void nicif_n2d_done(volatile union cosim_eth_proto_n2d *msg)
{
msg->dummy.own_type = (msg->dummy.own_type & COSIM_ETH_PROTO_N2D_MSG_MASK)
| COSIM_ETH_PROTO_N2D_OWN_NET;
void nicif_n2d_done(volatile union cosim_eth_proto_n2d *msg) {
msg->dummy.own_type = (msg->dummy.own_type & COSIM_ETH_PROTO_N2D_MSG_MASK) |
COSIM_ETH_PROTO_N2D_OWN_NET;
}
void nicif_n2d_next(void)
{
void nicif_n2d_next(void) {
n2d_pos = (n2d_pos + 1) % N2D_ENUM;
}
volatile union cosim_eth_proto_d2n *nicsim_d2n_alloc(
struct nicsim_params *params, uint64_t timestamp)
{
struct nicsim_params *params, uint64_t timestamp) {
volatile union cosim_eth_proto_d2n *msg =
(volatile union cosim_eth_proto_d2n *)
(d2n_queue + d2n_pos * D2N_ELEN);
(volatile union cosim_eth_proto_d2n *)(d2n_queue + d2n_pos * D2N_ELEN);
if ((msg->dummy.own_type & COSIM_ETH_PROTO_D2N_OWN_MASK) !=
COSIM_ETH_PROTO_D2N_OWN_DEV)
{
COSIM_ETH_PROTO_D2N_OWN_DEV) {
return NULL;
}
......
lib/simbricks/nicif/nicsim.h
View file @ d4666c97
......@@ -25,8 +25,8 @@
#ifndef SIMBRICKS_NICIF_NICSIM_H_
#define SIMBRICKS_NICIF_NICSIM_H_
#include <simbricks/proto/pcie.h>
#include <simbricks/proto/network.h>
#include <simbricks/proto/pcie.h>
#define SYNC_MODES 0 // ModES style synchronization
#define SYNC_BARRIER 1 // Global barrier style synchronization
......@@ -62,9 +62,8 @@ void nicif_h2d_next(void);
volatile union cosim_pcie_proto_d2h *nicsim_d2h_alloc(
struct nicsim_params *params, uint64_t timestamp);
volatile union cosim_eth_proto_n2d *nicif_n2d_poll(
struct nicsim_params *params, uint64_t timestamp);
volatile union cosim_eth_proto_n2d *nicif_n2d_poll(struct nicsim_params *params,
uint64_t timestamp);
void nicif_n2d_done(volatile union cosim_eth_proto_n2d *msg);
void nicif_n2d_next(void);
......
lib/simbricks/nicif/utils.c
View file @ d4666c97
......@@ -24,18 +24,17 @@
#include <errno.h>
#include <fcntl.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <sys/un.h>
#include <sys/socket.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <sys/socket.h>
#include <sys/un.h>
#include <unistd.h>
#include "lib/simbricks/nicif/internal.h"
int uxsocket_init(const char *path)
{
int uxsocket_init(const char *path) {
int fd;
struct sockaddr_un saun;
......@@ -47,7 +46,7 @@ int uxsocket_init(const char *path)
memset(&saun, 0, sizeof(saun));
saun.sun_family = AF_UNIX;
memcpy(saun.sun_path, path, strlen(path));
if (bind(fd, (struct sockaddr *) &saun, sizeof(saun))) {
if (bind(fd, (struct sockaddr *)&saun, sizeof(saun))) {
perror("uxsocket_init: bind failed");
goto error_close;
}
......@@ -65,8 +64,7 @@ error_exit:
return -1;
}
int uxsocket_send(int connfd, void *data, size_t len, int fd)
{
int uxsocket_send(int connfd, void *data, size_t len, int fd) {
ssize_t tx;
struct iovec iov = {
.iov_base = data,
......@@ -94,10 +92,10 @@ int uxsocket_send(int connfd, void *data, size_t len, int fd)
cmsg->cmsg_type = SCM_RIGHTS;
cmsg->cmsg_len = CMSG_LEN(sizeof(int));
*(int *) CMSG_DATA(cmsg) = fd;
*(int *)CMSG_DATA(cmsg) = fd;
}
if ((tx = sendmsg(connfd, &msg, 0)) != (ssize_t) len) {
if ((tx = sendmsg(connfd, &msg, 0)) != (ssize_t)len) {
fprintf(stderr, "tx == %zd\n", tx);
return -1;
}
......@@ -105,8 +103,7 @@ int uxsocket_send(int connfd, void *data, size_t len, int fd)
return 0;
}
int shm_create(const char *path, size_t size, void **addr)
{
int shm_create(const char *path, size_t size, void **addr) {
int fd;
void *p;
......@@ -119,9 +116,8 @@ int shm_create(const char *path, size_t size, void **addr)
goto error_remove;
}
if ((p = mmap(NULL, size, PROT_READ | PROT_WRITE,
MAP_SHARED | MAP_POPULATE, fd, 0)) == (void *) -1)
{
if ((p = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_POPULATE,
fd, 0)) == (void *)-1) {
perror("util_create_shmsiszed: mmap failed");
goto error_remove;
}
......
lib/simbricks/proto/network.h
View file @ d4666c97
......@@ -56,7 +56,6 @@ struct cosim_eth_proto_dev_intro {
uint64_t n2d_nentries;
} __attribute__((packed));
#define COSIM_ETH_PROTO_FLAGS_NI_SYNC (1 << 0)
/** welcome message sent by network to device */
......@@ -65,7 +64,6 @@ struct cosim_eth_proto_net_intro {
uint64_t flags;
} __attribute__((packed));
/******************************************************************************/
/* Messages on in-memory device to network channel */
......@@ -111,7 +109,6 @@ union cosim_eth_proto_d2n {
struct cosim_eth_proto_d2n_send send;
};
/******************************************************************************/
/* Messages on in-memory network to device channel */
......
lib/simbricks/proto/pcie.h
View file @ d4666c97
......@@ -108,7 +108,6 @@ struct cosim_pcie_proto_dev_intro {
uint16_t psi_msix_cap_offset;
} __attribute__((packed));
#define COSIM_PCIE_PROTO_FLAGS_HI_SYNC (1 << 0)
/** welcome message sent by host to device */
......@@ -117,7 +116,6 @@ struct cosim_pcie_proto_host_intro {
uint64_t flags;
} __attribute__((packed));
/******************************************************************************/
/* Messages on in-memory device to host channel */
......@@ -221,7 +219,6 @@ union cosim_pcie_proto_d2h {
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(union cosim_pcie_proto_d2h);
/******************************************************************************/
/* Messages on in-memory host to device channel */
......
sims/net/switch/net_switch.cc
View file @ d4666c97
......@@ -22,15 +22,16 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <unistd.h>
#include <cassert>
#include <climits>
#include <csignal>
#include <cstdio>
#include <cstdlib>
#include <csignal>
#include <climits>
#include <cstring>
#include <unistd.h>
#include <vector>
#include <unordered_map>
#include <cassert>
#include <vector>
extern "C" {
#include <simbricks/netif/netsim.h>
......@@ -43,8 +44,8 @@ static uint64_t eth_latency = (500 * 1000ULL); // 500ns
struct MAC {
const volatile uint8_t *data;
MAC(const volatile uint8_t *data)
: data(data) {}
MAC(const volatile uint8_t *data) : data(data) {
}
bool operator==(const MAC &other) const {
for (int i = 0; i < 6; i++) {
......@@ -57,15 +58,14 @@ struct MAC {
};
namespace std {
template <>
struct hash<MAC>
{
size_t operator()(const MAC &m) const {
struct hash<MAC> {
size_t operator()(const MAC &m) const {
size_t res = 0;
for (int i = 0; i < 6; i++) {
res = (res << 4) | (res ^ m.data[i]);
}
return res;
}
}
};
} // namespace std
......@@ -77,13 +77,12 @@ static const MAC bcast_addr(bcast);
static std::vector<struct netsim_interface> nsifs;
static std::unordered_map<MAC, int> mac_table;
static void sigint_handler(int dummy)
{
static void sigint_handler(int dummy) {
exiting = 1;
}
static void forward_pkt(volatile struct cosim_eth_proto_d2n_send *tx, int port)
{
static void forward_pkt(volatile struct cosim_eth_proto_d2n_send *tx,
int port) {
volatile union cosim_eth_proto_n2d *msg_to;
msg_to = netsim_n2d_alloc(&nsifs[port], cur_ts, eth_latency);
if (msg_to != NULL) {
......@@ -94,17 +93,14 @@ static void forward_pkt(volatile struct cosim_eth_proto_d2n_send *tx, int port)
memcpy((void *)rx->data, (void *)tx->data, tx->len);
// WMB();
rx->own_type = COSIM_ETH_PROTO_N2D_MSG_RECV |
COSIM_ETH_PROTO_N2D_OWN_DEV;
rx->own_type = COSIM_ETH_PROTO_N2D_MSG_RECV | COSIM_ETH_PROTO_N2D_OWN_DEV;
} else {
fprintf(stderr, "forward_pkt: dropping packet\n");
}
}
static void switch_pkt(struct netsim_interface *nsif, int iport)
{
volatile union cosim_eth_proto_d2n *msg_from = netsim_d2n_poll(nsif,
cur_ts);
static void switch_pkt(struct netsim_interface *nsif, int iport) {
volatile union cosim_eth_proto_d2n *msg_from = netsim_d2n_poll(nsif, cur_ts);
if (msg_from == NULL) {
return;
}
......@@ -114,7 +110,7 @@ static void switch_pkt(struct netsim_interface *nsif, int iport)
volatile struct cosim_eth_proto_d2n_send *tx;
tx = &msg_from->send;
// Get MAC addresses
MAC dst(tx->data), src(tx->data+6);
MAC dst(tx->data), src(tx->data + 6);
// MAC learning
if (!(src == bcast_addr)) {
mac_table[src] = iport;
......@@ -140,8 +136,7 @@ static void switch_pkt(struct netsim_interface *nsif, int iport)
netsim_d2n_done(nsif, msg_from);
}
int main(int argc, char *argv[])
{
int main(int argc, char *argv[]) {
int c;
int bad_option = 0;
int sync_mode = SYNC_MODES;
......@@ -181,7 +176,8 @@ int main(int argc, char *argv[])
}
if (nsifs.empty() || bad_option) {
fprintf(stderr, "Usage: net_switch [-S SYNC-PERIOD] [-E ETH-LATENCY] "
fprintf(stderr,
"Usage: net_switch [-S SYNC-PERIOD] [-E ETH-LATENCY] "
"-s SOCKET-A [-s SOCKET-B ...]\n");
return EXIT_FAILURE;
}
......@@ -193,8 +189,8 @@ int main(int argc, char *argv[])
while (!exiting) {
// Sync all interfaces
for (auto &nsif : nsifs) {
if (netsim_n2d_sync(&nsif, cur_ts, eth_latency,
sync_period, sync_mode) != 0) {
if (netsim_n2d_sync(&nsif, cur_ts, eth_latency, sync_period, sync_mode) !=
0) {
fprintf(stderr, "netsim_n2d_sync failed\n");
abort();
}
......
sims/net/tap/net_tap.c
View file @ d4666c97
......@@ -23,15 +23,15 @@
*/
#include <fcntl.h>
#include <linux/if.h>
#include <linux/if_tun.h>
#include <pthread.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <unistd.h>
#include <linux/if.h>
#include <linux/if_tun.h>
#include <simbricks/netif/netsim.h>
......@@ -40,8 +40,7 @@
static struct netsim_interface nsif;
static int tap_fd;
static int tap_open(const char *name)
{
static int tap_open(const char *name) {
struct ifreq ifr;
int fd;
......@@ -63,19 +62,17 @@ static int tap_open(const char *name)
return fd;
}
static void d2n_send(volatile struct cosim_eth_proto_d2n_send *s)
{
static void d2n_send(volatile struct cosim_eth_proto_d2n_send *s) {
#ifdef DEBUG_PKTMETA
printf("sent packet: len=%u\n", s->len);
#endif
if (write(tap_fd, (void *) s->data, s->len) != (ssize_t) s->len) {
if (write(tap_fd, (void *)s->data, s->len) != (ssize_t)s->len) {
perror("d2n_send: send failed");
}
}
static void poll_d2n(void)
{
static void poll_d2n(void) {
volatile union cosim_eth_proto_d2n *msg = netsim_d2n_poll(&nsif, 0);
uint8_t type;
......@@ -96,8 +93,7 @@ static void poll_d2n(void)
netsim_d2n_done(&nsif, msg);
}
static void *rx_handler(void *arg)
{
static void *rx_handler(void *arg) {
volatile union cosim_eth_proto_n2d *msg;
volatile struct cosim_eth_proto_n2d_recv *rx;
ssize_t len;
......@@ -110,7 +106,7 @@ static void *rx_handler(void *arg)
}
rx = &msg->recv;
len = read(tap_fd, (void *) rx->data, nsif.n2d_elen - sizeof(*msg));
len = read(tap_fd, (void *)rx->data, nsif.n2d_elen - sizeof(*msg));
if (len <= 0) {
perror("rx handler: read failed");
}
......@@ -121,13 +117,11 @@ static void *rx_handler(void *arg)
#endif
// WMB();
rx->own_type = COSIM_ETH_PROTO_N2D_MSG_RECV |
COSIM_ETH_PROTO_N2D_OWN_DEV;
rx->own_type = COSIM_ETH_PROTO_N2D_MSG_RECV | COSIM_ETH_PROTO_N2D_OWN_DEV;
}
}
int main(int argc, char *argv[])
{
int main(int argc, char *argv[]) {
int sync;
if (argc != 3) {
......
sims/net/wire/net_wire.c
View file @ d4666c97
......@@ -22,19 +22,19 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <assert.h>
#include <fcntl.h>
#include <linux/if.h>
#include <linux/if_tun.h>
#include <pcap/pcap.h>
#include <pthread.h>
#include <stdlib.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <signal.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <unistd.h>
#include <linux/if.h>
#include <linux/if_tun.h>
#include <pcap/pcap.h>
#include <assert.h>
#include <simbricks/netif/netsim.h>
......@@ -44,20 +44,17 @@ static uint64_t cur_ts;
static int exiting = 0;
static pcap_dumper_t *dumpfile = NULL;
static void sigint_handler(int dummy)
{
static void sigint_handler(int dummy) {
exiting = 1;
}
static void sigusr1_handler(int dummy)
{
static void sigusr1_handler(int dummy) {
fprintf(stderr, "main_time = %lu\n", cur_ts);
}
static void move_pkt(struct netsim_interface *from, struct netsim_interface *to)
{
volatile union cosim_eth_proto_d2n *msg_from =
netsim_d2n_poll(from, cur_ts);
static void move_pkt(struct netsim_interface *from,
struct netsim_interface *to) {
volatile union cosim_eth_proto_d2n *msg_from = netsim_d2n_poll(from, cur_ts);
volatile union cosim_eth_proto_n2d *msg_to;
volatile struct cosim_eth_proto_d2n_send *tx;
volatile struct cosim_eth_proto_n2d_recv *rx;
......@@ -78,8 +75,7 @@ static void move_pkt(struct netsim_interface *from, struct netsim_interface *to)
ph.ts.tv_usec = (cur_ts % 1000000000000ULL) / 1000ULL;
ph.caplen = tx->len;
ph.len = tx->len;
pcap_dump((unsigned char *) dumpfile, &ph,
(unsigned char *) tx->data);
pcap_dump((unsigned char *)dumpfile, &ph, (unsigned char *)tx->data);
}
msg_to = netsim_n2d_alloc(to, cur_ts, eth_latency);
......@@ -87,11 +83,10 @@ static void move_pkt(struct netsim_interface *from, struct netsim_interface *to)
rx = &msg_to->recv;
rx->len = tx->len;
rx->port = 0;
memcpy((void *) rx->data, (void *) tx->data, tx->len);
memcpy((void *)rx->data, (void *)tx->data, tx->len);
// WMB();
rx->own_type = COSIM_ETH_PROTO_N2D_MSG_RECV |
COSIM_ETH_PROTO_N2D_OWN_DEV;
rx->own_type = COSIM_ETH_PROTO_N2D_MSG_RECV | COSIM_ETH_PROTO_N2D_OWN_DEV;
} else {
fprintf(stderr, "move_pkt: dropping packet\n");
}
......@@ -104,8 +99,7 @@ static void move_pkt(struct netsim_interface *from, struct netsim_interface *to)
netsim_d2n_done(from, msg_from);
}
int main(int argc, char *argv[])
{
int main(int argc, char *argv[]) {
struct netsim_interface nsif_a, nsif_b;
uint64_t ts_a, ts_b;
int sync_a, sync_b;
......@@ -113,7 +107,8 @@ int main(int argc, char *argv[])
int sync_mode = SYNC_MODES;
if (argc < 3 && argc > 7) {
fprintf(stderr, "Usage: net_wire SOCKET-A SOCKET-B [SYNC-MODE] "
fprintf(stderr,
"Usage: net_wire SOCKET-A SOCKET-B [SYNC-MODE] "
"[SYNC-PERIOD] [ETH-LATENCY] [PCAP-FILE]\n");
return EXIT_FAILURE;
}
......@@ -154,13 +149,13 @@ int main(int argc, char *argv[])
printf("start polling\n");
while (!exiting) {
if (netsim_n2d_sync(&nsif_a, cur_ts, eth_latency, sync_period,
sync_mode) != 0) {
if (netsim_n2d_sync(&nsif_a, cur_ts, eth_latency, sync_period, sync_mode) !=
0) {
fprintf(stderr, "netsim_n2d_sync(nsif_a) failed\n");
abort();
}
if (netsim_n2d_sync(&nsif_b, cur_ts, eth_latency, sync_period,
sync_mode) != 0) {
if (netsim_n2d_sync(&nsif_b, cur_ts, eth_latency, sync_period, sync_mode) !=
0) {
fprintf(stderr, "netsim_n2d_sync(nsif_a) failed\n");
abort();
}
......@@ -172,12 +167,11 @@ int main(int argc, char *argv[])
ts_a = netsim_d2n_timestamp(&nsif_a);
ts_b = netsim_d2n_timestamp(&nsif_b);
} while (!exiting &&
((sync_a && ts_a <= cur_ts) ||
(sync_b && ts_b <= cur_ts)));
((sync_a && ts_a <= cur_ts) || (sync_b && ts_b <= cur_ts)));
if (sync_a && sync_b)
cur_ts = netsim_advance_time(ts_a <= ts_b ? ts_a : ts_b,
sync_period, sync_mode);
cur_ts = netsim_advance_time(ts_a <= ts_b ? ts_a : ts_b, sync_period,
sync_mode);
else if (sync_a)
cur_ts = netsim_advance_time(ts_a, sync_period, sync_mode);
else if (sync_b)
......
sims/nic/corundum/coord.h
View file @ d4666c97
......@@ -26,8 +26,8 @@
#define COORD_H_
#include <deque>
#include <map>
#include <iostream>
#include <map>
#include "sims/nic/corundum/debug.h"
......@@ -57,8 +57,7 @@ class PCICoordinator {
std::deque<PCIOp *> queue;
std::map<DMAOp *, PCIOp *> dmamap;
void process()
{
void process() {
PCIOp *op;
while (!queue.empty()) {
op = queue.front();
......@@ -68,21 +67,18 @@ class PCICoordinator {
queue.pop_front();
if (op->type == PCIOp::OP_MSI) {
#ifdef COORD_DEBUG
std::cout << main_time << " issuing msi " << op->msi_vec <<
std::endl;
std::cout << main_time << " issuing msi " << op->msi_vec << std::endl;
#endif
pci_msi_issue(op->msi_vec);
} else if (op->type == PCIOp::OP_DMA) {
#ifdef COORD_DEBUG
std::cout << main_time << " issuing dma " << op->dma_op <<
std::endl;
std::cout << main_time << " issuing dma " << op->dma_op << std::endl;
#endif
pci_dma_issue(op->dma_op);
dmamap.erase(op->dma_op);
} else if (op->type == PCIOp::OP_RWCOMP) {
#ifdef COORD_DEBUG
std::cout << main_time << " issuing mmio " << op->mmio_op <<
std::endl;
std::cout << main_time << " issuing mmio " << op->mmio_op << std::endl;
#endif
pci_rwcomp_issue(op->mmio_op);
} else {
......@@ -94,11 +90,10 @@ class PCICoordinator {
}
public:
void dma_register(DMAOp *dma_op, bool ready)
{
void dma_register(DMAOp *dma_op, bool ready) {
#ifdef COORD_DEBUG
std::cout << main_time << " registering dma op " << dma_op << " "
<< ready << std::endl;
std::cout << main_time << " registering dma op " << dma_op << " " << ready
<< std::endl;
#endif
PCIOp *op = new PCIOp;
op->dma_op = dma_op;
......@@ -111,8 +106,7 @@ class PCICoordinator {
process();
}
void dma_mark_ready(DMAOp *op)
{
void dma_mark_ready(DMAOp *op) {
#ifdef COORD_DEBUG
std::cout << main_time << " readying dma op " << op << std::endl;
#endif
......@@ -121,8 +115,7 @@ class PCICoordinator {
process();
}
void msi_enqueue(uint32_t vec)
{
void msi_enqueue(uint32_t vec) {
#ifdef COORD_DEBUG
std::cout << main_time << " enqueuing MSI " << vec << std::endl;
#endif
......@@ -135,11 +128,9 @@ class PCICoordinator {
process();
}
void mmio_comp_enqueue(MMIOOp *mmio_op)
{
void mmio_comp_enqueue(MMIOOp *mmio_op) {
#ifdef COORD_DEBUG
std::cout << main_time << " enqueuing MMIO comp " << mmio_op <<
std::endl;
std::cout << main_time << " enqueuing MMIO comp " << mmio_op << std::endl;
#endif
PCIOp *op = new PCIOp;
op->mmio_op = mmio_op;
......
sims/nic/corundum/corundum_verilator.cc
View file @ d4666c97
......@@ -22,27 +22,26 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <iostream>
#include <deque>
#include <set>
#include <signal.h>
#include <verilated.h>
#include <deque>
#include <iostream>
#include <set>
#ifdef TRACE_ENABLED
#include <verilated_vcd_c.h>
#endif
extern "C" {
#include <simbricks/nicif/nicsim.h>
#include <simbricks/nicif/nicsim.h>
}
#include "sims/nic/corundum/obj_dir/Vinterface.h"
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/corundum.h"
#include "sims/nic/corundum/coord.h"
#include "sims/nic/corundum/corundum.h"
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/dma.h"
#include "sims/nic/corundum/mem.h"
#include "sims/nic/corundum/obj_dir/Vinterface.h"
struct DMAOp;
......@@ -51,35 +50,28 @@ static uint64_t sync_period = 500 * 1000ULL; // 500ns
static uint64_t pci_latency = 500 * 1000ULL; // 500ns
static uint64_t eth_latency = 500 * 1000ULL; // 500ns
static volatile int exiting = 0;
uint64_t main_time = 0;
static struct nicsim_params nsparams;
#ifdef TRACE_ENABLED
static VerilatedVcdC* trace;
static VerilatedVcdC *trace;
#endif
static volatile union cosim_pcie_proto_d2h *d2h_alloc(void);
static void sigint_handler(int dummy)
{
static void sigint_handler(int dummy) {
exiting = 1;
}
static void sigusr1_handler(int dummy)
{
static void sigusr1_handler(int dummy) {
fprintf(stderr, "main_time = %lu\n", main_time);
}
double sc_time_stamp()
{
double sc_time_stamp() {
return main_time;
}
static void reset_inputs(Vinterface *top)
{
static void reset_inputs(Vinterface *top) {
top->clk = 0;
top->rst = 0;
top->m_axis_ctrl_dma_read_desc_ready = 0;
......@@ -139,16 +131,14 @@ static void reset_inputs(Vinterface *top)
top->ptp_ts_step = 0;
}
static void report_output(const char *label, uint64_t val)
{
static void report_output(const char *label, uint64_t val) {
if (val == 0)
return;
std::cout << " " << label << " = " << val << std::endl;
}
static void report_outputs(Vinterface *top)
{
static void report_outputs(Vinterface *top) {
report_output("m_axis_ctrl_dma_read_desc_dma_addr",
top->m_axis_ctrl_dma_read_desc_dma_addr);
report_output("m_axis_ctrl_dma_read_desc_ram_sel",
......@@ -218,12 +208,10 @@ static void report_outputs(Vinterface *top)
report_output("m_axil_csr_rready", top->m_axil_csr_rready);
report_output("ctrl_dma_ram_wr_cmd_ready", top->ctrl_dma_ram_wr_cmd_ready);
report_output("ctrl_dma_ram_rd_cmd_ready", top->ctrl_dma_ram_rd_cmd_ready);
report_output("ctrl_dma_ram_rd_resp_valid",
top->ctrl_dma_ram_rd_resp_valid);
report_output("ctrl_dma_ram_rd_resp_valid", top->ctrl_dma_ram_rd_resp_valid);
report_output("data_dma_ram_wr_cmd_ready", top->data_dma_ram_wr_cmd_ready);
report_output("data_dma_ram_rd_cmd_ready", top->data_dma_ram_rd_cmd_ready);
report_output("data_dma_ram_rd_resp_valid",
top->data_dma_ram_rd_resp_valid);
report_output("data_dma_ram_rd_resp_valid", top->data_dma_ram_rd_resp_valid);
report_output("tx_axis_tkeep", top->tx_axis_tkeep);
report_output("tx_axis_tvalid", top->tx_axis_tvalid);
report_output("tx_axis_tlast", top->tx_axis_tlast);
......@@ -258,12 +246,10 @@ class MMIOInterface {
public:
MMIOInterface(Vinterface &top_, PCICoordinator &coord_)
: top(top_), coord(coord_), rCur(0), wCur(0)
{
: top(top_), coord(coord_), rCur(0), wCur(0) {
}
void step()
{
void step() {
if (rCur) {
/* work on active read operation */
......@@ -278,8 +264,8 @@ class MMIOInterface {
rCur->value = top.s_axil_rdata;
coord.mmio_comp_enqueue(rCur);
#ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: completed AXI read op=" <<
rCur << " val=" << rCur->value << std::endl;
std::cout << main_time << " MMIO: completed AXI read op=" << rCur
<< " val=" << rCur->value << std::endl;
#endif
rCur = 0;
}
......@@ -302,8 +288,8 @@ class MMIOInterface {
top.s_axil_bready = 0;
// TODO(antoinek): check top.s_axil_bresp
#ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: completed AXI write op="
<< wCur << std::endl;
std::cout << main_time << " MMIO: completed AXI write op=" << wCur
<< std::endl;
#endif
coord.mmio_comp_enqueue(wCur);
wCur = 0;
......@@ -340,12 +326,11 @@ class MMIOInterface {
}
}
void issueRead(uint64_t id, uint64_t addr, size_t len)
{
void issueRead(uint64_t id, uint64_t addr, size_t len) {
MMIOOp *op = new MMIOOp;
#ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: read id=" << id << " addr=" <<
std::hex << addr << " len=" << len << " op=" << op << std::endl;
std::cout << main_time << " MMIO: read id=" << id << " addr=" << std::hex
<< addr << " len=" << len << " op=" << op << std::endl;
#endif
op->id = id;
op->addr = addr;
......@@ -354,14 +339,12 @@ class MMIOInterface {
queue.push_back(op);
}
void issueWrite(uint64_t id, uint64_t addr, size_t len, uint64_t val)
{
void issueWrite(uint64_t id, uint64_t addr, size_t len, uint64_t val) {
MMIOOp *op = new MMIOOp;
#ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: write id=" << id << " addr=" <<
std::hex << addr << " len=" << len << " val=" << val << " op="
<< op << std::endl;
std::cout << main_time << " MMIO: write id=" << id << " addr=" << std::hex
<< addr << " len=" << len << " val=" << val << " op=" << op
<< std::endl;
#endif
op->id = id;
op->addr = addr;
......@@ -372,8 +355,7 @@ class MMIOInterface {
}
};
void pci_rwcomp_issue(MMIOOp *op)
{
void pci_rwcomp_issue(MMIOOp *op) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile struct cosim_pcie_proto_d2h_readcomp *rc;
volatile struct cosim_pcie_proto_d2h_writecomp *wc;
......@@ -386,16 +368,16 @@ void pci_rwcomp_issue(MMIOOp *op)
wc->req_id = op->id;
// WMB();
wc->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
wc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else {
rc = &msg->readcomp;
memcpy((void *) rc->data, &op->value, op->len);
memcpy((void *)rc->data, &op->value, op->len);
rc->req_id = op->id;
// WMB();
rc->own_type = COSIM_PCIE_PROTO_D2H_MSG_READCOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
rc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READCOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
delete op;
......@@ -446,8 +428,7 @@ class MemAccessor {
std::set<DMAOp *> pci_dma_pending;
void pci_dma_issue(DMAOp *op)
{
void pci_dma_issue(DMAOp *op) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
uint8_t ty;
......@@ -456,39 +437,37 @@ void pci_dma_issue(DMAOp *op)
if (op->write) {
volatile struct cosim_pcie_proto_d2h_write *write = &msg->write;
write->req_id = (uintptr_t) op;
write->req_id = (uintptr_t)op;
write->offset = op->dma_addr;
write->len = op->len;
// TODO(antoinek): check DMA length
memcpy((void *) write->data, op->data, op->len);
memcpy((void *)write->data, op->data, op->len);
// WMB();
write->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITE |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
write->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITE | COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else {
volatile struct cosim_pcie_proto_d2h_read *read = &msg->read;
read->req_id = (uintptr_t) op;
read->req_id = (uintptr_t)op;
read->offset = op->dma_addr;
read->len = op->len;
// WMB();
read->own_type = COSIM_PCIE_PROTO_D2H_MSG_READ |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
read->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READ | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
pci_dma_pending.insert(op);
}
static void h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc)
{
DMAOp *op = (DMAOp *) (uintptr_t) rc->req_id;
static void h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc) {
DMAOp *op = (DMAOp *)(uintptr_t)rc->req_id;
if (pci_dma_pending.find(op) == pci_dma_pending.end())
throw "unexpected completion";
pci_dma_pending.erase(op);
memcpy(op->data, (void *) rc->data, op->len);
memcpy(op->data, (void *)rc->data, op->len);
#if 0
std::cerr << "dma read comp: ";
......@@ -497,13 +476,11 @@ static void h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc)
std::cerr << std::endl;
#endif
op->engine->pci_op_complete(op);
}
static void h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc)
{
DMAOp *op = (DMAOp *) (uintptr_t) wc->req_id;
static void h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc) {
DMAOp *op = (DMAOp *)(uintptr_t)wc->req_id;
if (pci_dma_pending.find(op) == pci_dma_pending.end())
throw "unexpected completion";
pci_dma_pending.erase(op);
......@@ -511,33 +488,41 @@ static void h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc)
op->engine->pci_op_complete(op);
}
static uint64_t csr_read(uint64_t off)
{
static uint64_t csr_read(uint64_t off) {
switch (off) {
case 0x00: return 32; /* firmware id */
case 0x04: return 1; /* firmware version */
case 0x08: return 0x43215678; /* board id */
case 0x0c: return 0x1; /* board version */
case 0x10: return 1; /* phc count */
case 0x14: return 0x200; /* phc offset */
case 0x18: return 0x80; /* phc stride */
case 0x20: return 1; /* if_count */
case 0x24: return 0x80000; /* if stride */
case 0x2c: return 0x80000; /* if csr offset */
case 0x200: return 0x1; /* phc features */
case 0x00:
return 32; /* firmware id */
case 0x04:
return 1; /* firmware version */
case 0x08:
return 0x43215678; /* board id */
case 0x0c:
return 0x1; /* board version */
case 0x10:
return 1; /* phc count */
case 0x14:
return 0x200; /* phc offset */
case 0x18:
return 0x80; /* phc stride */
case 0x20:
return 1; /* if_count */
case 0x24:
return 0x80000; /* if stride */
case 0x2c:
return 0x80000; /* if csr offset */
case 0x200:
return 0x1; /* phc features */
default:
std::cerr << "csr_read(" << off << ") unimplemented" << std::endl;
return 0;
}
}
static void csr_write(uint64_t off, uint64_t val)
{
static void csr_write(uint64_t off, uint64_t val) {
}
static void h2d_read(MMIOInterface &mmio,
volatile struct cosim_pcie_proto_h2d_read *read)
{
volatile struct cosim_pcie_proto_h2d_read *read) {
// std::cout << "got read " << read->offset << std::endl;
if (read->offset < 0x80000) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
......@@ -547,14 +532,14 @@ static void h2d_read(MMIOInterface &mmio,
throw "completion alloc failed";
rc = &msg->readcomp;
memset((void *) rc->data, 0, read->len);
memset((void *)rc->data, 0, read->len);
uint64_t val = csr_read(read->offset);
memcpy((void *) rc->data, &val, read->len);
memcpy((void *)rc->data, &val, read->len);
rc->req_id = read->req_id;
// WMB();
rc->own_type = COSIM_PCIE_PROTO_D2H_MSG_READCOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
rc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READCOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else {
/*printf("read(bar=%u, off=%lu, len=%u) = %lu\n", read->bar, read->offset,
read->len, val);*/
......@@ -563,11 +548,10 @@ static void h2d_read(MMIOInterface &mmio,
}
static void h2d_write(MMIOInterface &mmio,
volatile struct cosim_pcie_proto_h2d_write *write)
{
volatile struct cosim_pcie_proto_h2d_write *write) {
uint64_t val = 0;
memcpy(&val, (void *) write->data, write->len);
memcpy(&val, (void *)write->data, write->len);
// std::cout << "got write " << write->offset << " = " << val << std::endl;
......@@ -584,15 +568,14 @@ static void h2d_write(MMIOInterface &mmio,
wc->req_id = write->req_id;
// WMB();
wc->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
wc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else {
mmio.issueWrite(write->req_id, write->offset, write->len, val);
}
}
static void poll_h2d(MMIOInterface &mmio)
{
static void poll_h2d(MMIOInterface &mmio) {
volatile union cosim_pcie_proto_h2d *msg =
nicif_h2d_poll(&nsparams, main_time);
uint8_t t;
......@@ -632,10 +615,9 @@ static void poll_h2d(MMIOInterface &mmio)
nicif_h2d_done(msg);
nicif_h2d_next();
};
}
static volatile union cosim_pcie_proto_d2h *d2h_alloc(void)
{
static volatile union cosim_pcie_proto_d2h *d2h_alloc(void) {
return nicsim_d2h_alloc(&nsparams, main_time);
}
......@@ -646,13 +628,10 @@ class EthernetTx {
size_t packet_len;
public:
EthernetTx(Vinterface &top_)
: top(top_), packet_len(0)
{
EthernetTx(Vinterface &top_) : top(top_), packet_len(0) {
}
void packet_done()
{
void packet_done() {
volatile union cosim_eth_proto_d2n *msg =
nicsim_d2n_alloc(&nsparams, main_time);
volatile struct cosim_eth_proto_d2n_send *send;
......@@ -661,26 +640,24 @@ class EthernetTx {
throw "completion alloc failed";
send = &msg->send;
memcpy((void *) send->data, packet_buf, packet_len);
memcpy((void *)send->data, packet_buf, packet_len);
send->len = packet_len;
send->timestamp = main_time + eth_latency;
// WMB();
send->own_type = COSIM_ETH_PROTO_D2N_MSG_SEND |
COSIM_ETH_PROTO_D2N_OWN_NET;
send->own_type = COSIM_ETH_PROTO_D2N_MSG_SEND | COSIM_ETH_PROTO_D2N_OWN_NET;
#ifdef ETH_DEBUG
std::cerr << main_time << " EthernetTx: packet len=" << std::hex <<
packet_len << " ";
std::cerr << main_time << " EthernetTx: packet len=" << std::hex
<< packet_len << " ";
for (size_t i = 0; i < packet_len; i++) {
std::cerr << (unsigned) packet_buf[i] << " ";
std::cerr << (unsigned)packet_buf[i] << " ";
}
std::cerr << std::endl;
#endif
}
void step()
{
void step() {
top.tx_axis_tready = 1;
if (top.tx_axis_tvalid) {
......@@ -688,8 +665,7 @@ class EthernetTx {
for (size_t i = 0; i < 8; i++) {
if ((top.tx_axis_tkeep & (1 << i)) != 0) {
assert(packet_len < 2048);
packet_buf[packet_len++] =
(top.tx_axis_tdata >> (i * 8));
packet_buf[packet_len++] = (top.tx_axis_tdata >> (i * 8));
}
}
......@@ -711,19 +687,15 @@ class EthernetRx {
size_t fifo_pos_rd;
size_t fifo_pos_wr;
size_t packet_off;
public:
EthernetRx(Vinterface &top_)
: top(top_), fifo_pos_rd(0), fifo_pos_wr(0), packet_off(0)
{
for (size_t i = 0; i < FIFO_SIZE; i++)
fifo_lens[i] = 0;
: top(top_), fifo_pos_rd(0), fifo_pos_wr(0), packet_off(0) {
for (size_t i = 0; i < FIFO_SIZE; i++) fifo_lens[i] = 0;
}
void packet_received(const void *data, size_t len)
{
void packet_received(const void *data, size_t len) {
if (fifo_lens[fifo_pos_wr] != 0) {
std::cerr << "EthernetRx: dropping packet" << std::endl;
return;
......@@ -734,10 +706,10 @@ class EthernetRx {
#ifdef ETH_DEBUG
std::cout << main_time << " rx into " << fifo_pos_wr << std::endl;
std::cerr << main_time << " EthernetRx: packet len=" << std::hex <<
len << " ";
std::cerr << main_time << " EthernetRx: packet len=" << std::hex << len
<< " ";
for (size_t i = 0; i < len; i++) {
std::cerr << (unsigned) fifo_bufs[fifo_pos_wr][i] << " ";
std::cerr << (unsigned)fifo_bufs[fifo_pos_wr][i] << " ";
}
std::cerr << std::endl;
#endif
......@@ -745,8 +717,7 @@ class EthernetRx {
fifo_pos_wr = (fifo_pos_wr + 1) % FIFO_SIZE;
}
void step()
{
void step() {
if (fifo_lens[fifo_pos_rd] != 0) {
// we have data to send
if (packet_off != 0 && !top.rx_axis_tready) {
......@@ -755,8 +726,7 @@ class EthernetRx {
} else if (packet_off == fifo_lens[fifo_pos_rd]) {
// done with packet
#ifdef ETH_DEBUG
std::cerr << main_time << " EthernetRx: finished packet" <<
std::endl;
std::cerr << main_time << " EthernetRx: finished packet" << std::endl;
#endif
top.rx_axis_tvalid = 0;
top.rx_axis_tlast = 0;
......@@ -767,19 +737,17 @@ class EthernetRx {
} else {
// put out more packet data
#ifdef ETH_DEBUG
std::cerr << main_time << " EthernetRx: push flit " <<
packet_off << std::endl;
std::cerr << main_time << " EthernetRx: push flit " << packet_off
<< std::endl;
if (packet_off == 0)
std::cout << "rx from " << fifo_pos_rd << std::endl;
#endif
top.rx_axis_tkeep = 0;
top.rx_axis_tdata = 0;
size_t i;
for (i = 0; i < 8 && packet_off < fifo_lens[fifo_pos_rd];
i++) {
top.rx_axis_tdata |=
((uint64_t) fifo_bufs[fifo_pos_rd][packet_off]) <<
(i * 8);
for (i = 0; i < 8 && packet_off < fifo_lens[fifo_pos_rd]; i++) {
top.rx_axis_tdata |= ((uint64_t)fifo_bufs[fifo_pos_rd][packet_off])
<< (i * 8);
top.rx_axis_tkeep |= (1 << i);
packet_off++;
}
......@@ -796,13 +764,11 @@ class EthernetRx {
};
static void n2d_recv(EthernetRx &rx,
volatile struct cosim_eth_proto_n2d_recv *recv)
{
rx.packet_received((const void *) recv->data, recv->len);
volatile struct cosim_eth_proto_n2d_recv *recv) {
rx.packet_received((const void *)recv->data, recv->len);
}
static void poll_n2d(EthernetRx &rx)
{
static void poll_n2d(EthernetRx &rx) {
volatile union cosim_eth_proto_n2d *msg =
nicif_n2d_poll(&nsparams, main_time);
uint8_t t;
......@@ -903,13 +869,12 @@ class PCICoordinator {
};
#endif
void pci_msi_issue(uint8_t vec)
{
void pci_msi_issue(uint8_t vec) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile struct cosim_pcie_proto_d2h_interrupt *intr;
#ifdef MSI_DEBUG
std::cerr << main_time << " MSI interrupt vec=" << (int) vec << std::endl;
std::cerr << main_time << " MSI interrupt vec=" << (int)vec << std::endl;
#endif
intr = &msg->interrupt;
......@@ -917,19 +882,18 @@ void pci_msi_issue(uint8_t vec)
intr->inttype = COSIM_PCIE_PROTO_INT_MSI;
// WMB();
intr->own_type = COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT |
COSIM_PCIE_PROTO_D2H_OWN_HOST;
intr->own_type =
COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT | COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
static void msi_step(Vinterface &top, PCICoordinator &coord)
{
static void msi_step(Vinterface &top, PCICoordinator &coord) {
if (!top.msi_irq)
return;
#ifdef MSI_DEBUG
std::cerr << main_time << " msi_step: MSI interrupt raw vec=" <<
(int) top.msi_irq << std::endl;
std::cerr << main_time
<< " msi_step: MSI interrupt raw vec=" << (int)top.msi_irq
<< std::endl;
#endif
for (size_t i = 0; i < 32; i++) {
if (!((1ULL << i) & top.msi_irq))
......@@ -938,9 +902,8 @@ static void msi_step(Vinterface &top, PCICoordinator &coord)
}
}
int main(int argc, char *argv[])
{
char *vargs[2] = { argv[0], NULL };
int main(int argc, char *argv[]) {
char *vargs[2] = {argv[0], NULL};
Verilated::commandArgs(1, vargs);
int sync_mode = SYNC_MODES;
#ifdef TRACE_ENABLED
......@@ -948,7 +911,8 @@ int main(int argc, char *argv[])
#endif
if (argc < 4 && argc > 10) {
fprintf(stderr, "Usage: corundum_verilator PCI-SOCKET ETH-SOCKET "
fprintf(stderr,
"Usage: corundum_verilator PCI-SOCKET ETH-SOCKET "
"SHM [SYNC-MODE] [START-TICK] [SYNC-PERIOD] [PCI-LATENCY] "
"[ETH-LATENCY] [CLOCK-FREQ-MHZ]\n");
return EXIT_FAILURE;
......@@ -993,13 +957,12 @@ int main(int argc, char *argv[])
if (nicsim_init(&nsparams, &di)) {
return EXIT_FAILURE;
}
std::cout << "sync_pci=" << nsparams.sync_pci <<
" sync_eth=" << nsparams.sync_eth << std::endl;
std::cout << "sync_pci=" << nsparams.sync_pci
<< " sync_eth=" << nsparams.sync_eth << std::endl;
signal(SIGINT, sigint_handler);
signal(SIGUSR1, sigusr1_handler);
Vinterface *top = new Vinterface;
#ifdef TRACE_ENABLED
trace = new VerilatedVcdC;
......@@ -1008,38 +971,25 @@ int main(int argc, char *argv[])
#endif
MemWritePort p_mem_write_ctrl_dma(
top->ctrl_dma_ram_wr_cmd_sel,
top->ctrl_dma_ram_wr_cmd_be,
top->ctrl_dma_ram_wr_cmd_addr,
top->ctrl_dma_ram_wr_cmd_data,
top->ctrl_dma_ram_wr_cmd_valid,
top->ctrl_dma_ram_wr_cmd_ready);
top->ctrl_dma_ram_wr_cmd_sel, top->ctrl_dma_ram_wr_cmd_be,
top->ctrl_dma_ram_wr_cmd_addr, top->ctrl_dma_ram_wr_cmd_data,
top->ctrl_dma_ram_wr_cmd_valid, top->ctrl_dma_ram_wr_cmd_ready);
MemReadPort p_mem_read_ctrl_dma(
top->ctrl_dma_ram_rd_cmd_sel,
top->ctrl_dma_ram_rd_cmd_addr,
top->ctrl_dma_ram_rd_cmd_valid,
top->ctrl_dma_ram_rd_resp_ready,
top->ctrl_dma_ram_rd_resp_data,
top->ctrl_dma_ram_rd_cmd_ready,
top->ctrl_dma_ram_rd_cmd_sel, top->ctrl_dma_ram_rd_cmd_addr,
top->ctrl_dma_ram_rd_cmd_valid, top->ctrl_dma_ram_rd_resp_ready,
top->ctrl_dma_ram_rd_resp_data, top->ctrl_dma_ram_rd_cmd_ready,
top->ctrl_dma_ram_rd_resp_valid);
MemWritePort p_mem_write_data_dma(
top->data_dma_ram_wr_cmd_sel,
top->data_dma_ram_wr_cmd_be,
top->data_dma_ram_wr_cmd_addr,
top->data_dma_ram_wr_cmd_data,
top->data_dma_ram_wr_cmd_valid,
top->data_dma_ram_wr_cmd_ready);
top->data_dma_ram_wr_cmd_sel, top->data_dma_ram_wr_cmd_be,
top->data_dma_ram_wr_cmd_addr, top->data_dma_ram_wr_cmd_data,
top->data_dma_ram_wr_cmd_valid, top->data_dma_ram_wr_cmd_ready);
MemReadPort p_mem_read_data_dma(
top->data_dma_ram_rd_cmd_sel,
top->data_dma_ram_rd_cmd_addr,
top->data_dma_ram_rd_cmd_valid,
top->data_dma_ram_rd_resp_ready,
top->data_dma_ram_rd_resp_data,
top->data_dma_ram_rd_cmd_ready,
top->data_dma_ram_rd_cmd_sel, top->data_dma_ram_rd_cmd_addr,
top->data_dma_ram_rd_cmd_valid, top->data_dma_ram_rd_resp_ready,
top->data_dma_ram_rd_resp_data, top->data_dma_ram_rd_cmd_ready,
top->data_dma_ram_rd_resp_valid);
DMAPorts p_dma_read_ctrl(
top->m_axis_ctrl_dma_read_desc_dma_addr,
DMAPorts p_dma_read_ctrl(top->m_axis_ctrl_dma_read_desc_dma_addr,
top->m_axis_ctrl_dma_read_desc_ram_sel,
top->m_axis_ctrl_dma_read_desc_ram_addr,
top->m_axis_ctrl_dma_read_desc_len,
......@@ -1048,8 +998,7 @@ int main(int argc, char *argv[])
top->m_axis_ctrl_dma_read_desc_ready,
top->s_axis_ctrl_dma_read_desc_status_tag,
top->s_axis_ctrl_dma_read_desc_status_valid);
DMAPorts p_dma_write_ctrl(
top->m_axis_ctrl_dma_write_desc_dma_addr,
DMAPorts p_dma_write_ctrl(top->m_axis_ctrl_dma_write_desc_dma_addr,
top->m_axis_ctrl_dma_write_desc_ram_sel,
top->m_axis_ctrl_dma_write_desc_ram_addr,
top->m_axis_ctrl_dma_write_desc_len,
......@@ -1058,8 +1007,7 @@ int main(int argc, char *argv[])
top->m_axis_ctrl_dma_write_desc_ready,
top->s_axis_ctrl_dma_write_desc_status_tag,
top->s_axis_ctrl_dma_write_desc_status_valid);
DMAPorts p_dma_read_data(
top->m_axis_data_dma_read_desc_dma_addr,
DMAPorts p_dma_read_data(top->m_axis_data_dma_read_desc_dma_addr,
top->m_axis_data_dma_read_desc_ram_sel,
top->m_axis_data_dma_read_desc_ram_addr,
top->m_axis_data_dma_read_desc_len,
......@@ -1068,8 +1016,7 @@ int main(int argc, char *argv[])
top->m_axis_data_dma_read_desc_ready,
top->s_axis_data_dma_read_desc_status_tag,
top->s_axis_data_dma_read_desc_status_valid);
DMAPorts p_dma_write_data(
top->m_axis_data_dma_write_desc_dma_addr,
DMAPorts p_dma_write_data(top->m_axis_data_dma_write_desc_dma_addr,
top->m_axis_data_dma_write_desc_ram_sel,
top->m_axis_data_dma_write_desc_ram_addr,
top->m_axis_data_dma_write_desc_len,
......@@ -1117,8 +1064,8 @@ int main(int argc, char *argv[])
while (!exiting) {
while (nicsim_sync(&nsparams, main_time)) {
std::cerr << "warn: nicsim_sync failed (t=" << main_time << ")" <<
std::endl;
std::cerr << "warn: nicsim_sync failed (t=" << main_time << ")"
<< std::endl;
}
nicsim_advance_epoch(&nsparams, main_time);
......@@ -1161,8 +1108,7 @@ int main(int argc, char *argv[])
top->eval();
}
report_outputs(top);
std::cout << std::endl << std::endl << "main_time:" << main_time <<
std::endl;
std::cout << std::endl << std::endl << "main_time:" << main_time << std::endl;
#ifdef TRACE_ENABLED
trace->dump(main_time + 1);
......
sims/nic/corundum/dma.cc
View file @ d4666c97
......@@ -22,16 +22,15 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sims/nic/corundum/dma.h"
#include <iostream>
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/corundum.h"
#include "sims/nic/corundum/dma.h"
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/mem.h"
void DMAReader::step()
{
void DMAReader::step() {
p.dma_ready = 1;
if (p.dma_valid) {
DMAOp *op = new DMAOp;
......@@ -45,9 +44,9 @@ void DMAReader::step()
pending.insert(op);
#ifdef DMA_DEBUG
std::cout << main_time << " dma[" << label << "] op " << std::hex <<
op->dma_addr << " -> " << op->ram_sel << ":" << op->ram_addr <<
" len=" << op->len << " tag=" << (int) op->tag << std::endl;
std::cout << main_time << " dma[" << label << "] op " << std::hex
<< op->dma_addr << " -> " << op->ram_sel << ":" << op->ram_addr
<< " len=" << op->len << " tag=" << (int)op->tag << std::endl;
#endif
coord.dma_register(op, true);
......@@ -68,22 +67,17 @@ void DMAReader::step()
}
}
void DMAReader::pci_op_complete(DMAOp *op)
{
void DMAReader::pci_op_complete(DMAOp *op) {
mw.op_issue(op);
}
void DMAReader::mem_op_complete(DMAOp *op)
{
void DMAReader::mem_op_complete(DMAOp *op) {
completed.push_back(op);
// std::cout << "dma[" << label << "] mem complete " << op->dma_addr <<
// std::endl;
}
void DMAWriter::step()
{
void DMAWriter::step() {
p.dma_ready = 1;
if (p.dma_valid) {
DMAOp *op = new DMAOp;
......@@ -97,10 +91,9 @@ void DMAWriter::step()
pending.insert(op);
#ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label << "] op " <<
std::hex << op->dma_addr << " -> " << op->ram_sel << ":" <<
op->ram_addr << " len=" << op->len << " tag=" << (int) op->tag
<< std::endl;
std::cout << main_time << " dma write [" << label << "] op " << std::hex
<< op->dma_addr << " -> " << op->ram_sel << ":" << op->ram_addr
<< " len=" << op->len << " tag=" << (int)op->tag << std::endl;
#endif
coord.dma_register(op, false);
......@@ -113,8 +106,8 @@ void DMAWriter::step()
completed.pop_front();
#ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label <<
"] status complete " << op->dma_addr << std::endl;
std::cout << main_time << " dma write [" << label << "] status complete "
<< op->dma_addr << std::endl;
#endif
p.dma_status_valid = 1;
......@@ -125,22 +118,20 @@ void DMAWriter::step()
}
}
void DMAWriter::pci_op_complete(DMAOp *op)
{
void DMAWriter::pci_op_complete(DMAOp *op) {
#ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label << "] pci complete " <<
op->dma_addr << std::endl;
std::cout << main_time << " dma write [" << label << "] pci complete "
<< op->dma_addr << std::endl;
#endif
completed.push_back(op);
}
void DMAWriter::mem_op_complete(DMAOp *op)
{
void DMAWriter::mem_op_complete(DMAOp *op) {
#ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label << "] mem complete " <<
op->dma_addr << ": ";
std::cout << main_time << " dma write [" << label << "] mem complete "
<< op->dma_addr << ": ";
for (size_t i = 0; i < op->len; i++)
std::cout << (unsigned) op->data[i] << " ";
std::cout << (unsigned)op->data[i] << " ";
std::cout << std::endl;
#endif
coord.dma_mark_ready(op);
......
sims/nic/corundum/dma.h
View file @ d4666c97
......@@ -25,15 +25,14 @@
#ifndef DMA_H_
#define DMA_H_
#include <set>
#include <deque>
#include <verilated.h>
#include "sims/nic/corundum/obj_dir/Vinterface.h"
#include <deque>
#include <set>
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/coord.h"
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/obj_dir/Vinterface.h"
#define MAX_DMA_LEN 2048
......@@ -55,18 +54,19 @@ struct DMAPorts {
vluint8_t &dma_status_tag;
vluint8_t &dma_status_valid;
DMAPorts(vluint64_t &dma_addr_, vluint8_t &dma_ram_sel_,
vluint32_t &dma_ram_addr_, vluint16_t &dma_len_,
vluint8_t &dma_tag_, vluint8_t &dma_valid_,
vluint8_t &dma_ready_, vluint8_t &dma_status_tag_,
vluint8_t &dma_status_valid_)
: dma_addr(dma_addr_), dma_ram_sel(dma_ram_sel_),
dma_ram_addr(dma_ram_addr_), dma_len(dma_len_),
dma_tag(dma_tag_), dma_valid(dma_valid_),
dma_ready(dma_ready_), dma_status_tag(dma_status_tag_),
dma_status_valid(dma_status_valid_)
{
vluint32_t &dma_ram_addr_, vluint16_t &dma_len_, vluint8_t &dma_tag_,
vluint8_t &dma_valid_, vluint8_t &dma_ready_,
vluint8_t &dma_status_tag_, vluint8_t &dma_status_valid_)
: dma_addr(dma_addr_),
dma_ram_sel(dma_ram_sel_),
dma_ram_addr(dma_ram_addr_),
dma_len(dma_len_),
dma_tag(dma_tag_),
dma_valid(dma_valid_),
dma_ready(dma_ready_),
dma_status_tag(dma_status_tag_),
dma_status_valid(dma_status_valid_) {
}
};
......@@ -86,8 +86,8 @@ class DMAEngine {
DMAPorts &p;
PCICoordinator &coord;
DMAEngine(DMAPorts &p_, PCICoordinator &coord_)
: p(p_), coord(coord_) { }
DMAEngine(DMAPorts &p_, PCICoordinator &coord_) : p(p_), coord(coord_) {
}
public:
virtual void pci_op_complete(DMAOp *op) = 0;
......@@ -104,8 +104,7 @@ class DMAReader : public DMAEngine {
public:
DMAReader(const char *label_, DMAPorts &p_, MemWriter &mw_,
PCICoordinator &coord_)
: DMAEngine(p_, coord_), label(label_), mw(mw_)
{
: DMAEngine(p_, coord_), label(label_), mw(mw_) {
}
virtual void pci_op_complete(DMAOp *op);
......@@ -123,8 +122,7 @@ class DMAWriter : public DMAEngine {
public:
DMAWriter(const char *label_, DMAPorts &p_, MemReader &mr_,
PCICoordinator &coord_)
: DMAEngine(p_, coord_), label(label_), mr(mr_)
{
: DMAEngine(p_, coord_), label(label_), mr(mr_) {
}
virtual void pci_op_complete(DMAOp *op);
......@@ -132,5 +130,4 @@ class DMAWriter : public DMAEngine {
void step();
};
#endif // DMA_H_
sims/nic/corundum/mem.cc
View file @ d4666c97
......@@ -22,10 +22,11 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sims/nic/corundum/mem.h"
#include <iostream>
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/mem.h"
#include "sims/nic/corundum/dma.h"
/*
......@@ -40,11 +41,8 @@
#define SEG_COUNT 8
#define SEG_WIDTH (DATA_WIDTH / SEG_COUNT)
void MemWriter::step()
{
if (cur && p.mem_ready &&
((p.mem_ready & p.mem_valid) == p.mem_valid))
{
void MemWriter::step() {
if (cur && p.mem_ready && ((p.mem_ready & p.mem_valid) == p.mem_valid)) {
#ifdef MEM_DEBUG
std::cerr << "completed write to: " << cur->ram_addr << std::endl;
#endif
......@@ -75,18 +73,17 @@ void MemWriter::step()
p.mem_addr[0] = p.mem_addr[1] = p.mem_addr[2] = 0;
p.mem_be[0] = p.mem_be[1] = p.mem_be[2] = p.mem_be[3] = 0;
p.mem_valid = 0;
for (size_t i = 0; i < data_byte_width / 4; i++)
p.mem_data[i] = 0;
for (size_t i = 0; i < data_byte_width / 4; i++) p.mem_data[i] = 0;
/* put data bytes in the right places */
size_t off = data_offset;
size_t cur_len = (cur->len - cur_off > data_byte_width - data_offset ?
data_byte_width - data_offset : cur->len - cur_off);
size_t cur_len = (cur->len - cur_off > data_byte_width - data_offset
? data_byte_width - data_offset
: cur->len - cur_off);
for (size_t i = 0; i < cur_len; i++, off++) {
size_t byte_off = off % 4;
p.mem_data[off / 4] |= (((uint32_t) cur->data[cur_off + i]) <<
(byte_off * 8));
p.mem_data[off / 4] |=
(((uint32_t)cur->data[cur_off + i]) << (byte_off * 8));
p.mem_be[off / 32] |= (1 << (off % 32));
p.mem_valid |= (1 << (off / (SEG_WIDTH / 8)));
}
......@@ -108,27 +105,22 @@ void MemWriter::step()
}
}
void MemWriter::op_issue(DMAOp *op)
{
void MemWriter::op_issue(DMAOp *op) {
#ifdef MEM_DEBUG
std::cerr << "enqueued write to " << op->ram_addr << std::endl;
#endif
pending.push_back(op);
}
void MemReader::step()
{
void MemReader::step() {
size_t data_byte_width = DATA_WIDTH / 8;
if (cur && p.mem_resvalid &&
((p.mem_resvalid & p.mem_valid) == p.mem_valid)) {
#ifdef MEM_DEBUG
std::cerr << "completed read from: " << std::hex << cur->ram_addr <<
std::endl;
std::cerr << " reval = " << (unsigned) p.mem_resvalid << std::endl;
std::cerr << "completed read from: " << std::hex << cur->ram_addr
<< std::endl;
std::cerr << " reval = " << (unsigned)p.mem_resvalid << std::endl;
#endif
p.mem_valid = 0;
#ifdef MEM_DEBUG
......@@ -137,12 +129,12 @@ void MemReader::step()
#endif
size_t off = (cur->ram_addr + cur_off) % data_byte_width;
size_t cur_len = (cur->len - cur_off > data_byte_width - off ?
data_byte_width - off : cur->len - cur_off);
size_t cur_len =
(cur->len - cur_off > data_byte_width - off ? data_byte_width - off
: cur->len - cur_off);
for (size_t i = 0; i < cur_len; i++, off++) {
size_t byte_off = (off % 4);
cur->data[cur_off + i] = (p.mem_data[off / 4] >> (byte_off * 8)) &
0xff;
cur->data[cur_off + i] = (p.mem_data[off / 4] >> (byte_off * 8)) & 0xff;
}
cur_off += cur_len;
......@@ -161,8 +153,8 @@ void MemReader::step()
size_t data_offset = (cur->ram_addr + cur_off) % data_byte_width;
#ifdef MEM_DEBUG
std::cerr << "issuing op=" << cur << " read from " << std::hex <<
cur->ram_addr << std::endl;
std::cerr << "issuing op=" << cur << " read from " << std::hex
<< cur->ram_addr << std::endl;
std::cerr << " off=" << data_offset << std::endl;
#endif
......@@ -171,11 +163,11 @@ void MemReader::step()
p.mem_addr[0] = p.mem_addr[1] = p.mem_addr[2] = 0;
p.mem_valid = 0x0;
/* put data bytes in the right places */
size_t off = data_offset;
size_t cur_len = (cur->len - cur_off > data_byte_width - data_offset ?
data_byte_width - data_offset : cur->len - cur_off);
size_t cur_len = (cur->len - cur_off > data_byte_width - data_offset
? data_byte_width - data_offset
: cur->len - cur_off);
for (size_t i = 0; i < cur_len; i++, off++) {
p.mem_valid |= (1 << (off / (SEG_WIDTH / 8)));
}
......@@ -198,13 +190,12 @@ void MemReader::step()
#ifdef MEM_DEBUG
for (size_t i = 0; i < 3; i++)
std::cerr << " addr = " << p.mem_addr[i] << std::endl;
std::cerr << " mem_valid = " << (unsigned) p.mem_valid << std::endl;
std::cerr << " mem_valid = " << (unsigned)p.mem_valid << std::endl;
#endif
}
}
void MemReader::op_issue(DMAOp *op)
{
void MemReader::op_issue(DMAOp *op) {
#ifdef MEM_DEBUG
std::cerr << "enqueued read from " << op->ram_addr << std::endl;
#endif
......
sims/nic/corundum/mem.h
View file @ d4666c97
......@@ -25,10 +25,10 @@
#ifndef MEM_H_
#define MEM_H_
#include <deque>
#include <verilated.h>
#include <deque>
#include "sims/nic/corundum/obj_dir/Vinterface.h"
class DMAOp;
......@@ -49,10 +49,13 @@ struct MemReadPort {
vluint8_t &mem_valid_, vluint8_t &mem_resready_,
vluint32_t (&mem_data_)[32], vluint8_t &mem_ready_,
vluint8_t &mem_resvalid_)
: mem_sel(mem_sel_), mem_addr(mem_addr_), mem_valid(mem_valid_),
mem_resready(mem_resready_), mem_data(mem_data_), mem_ready(mem_ready_),
mem_resvalid(mem_resvalid_)
{
: mem_sel(mem_sel_),
mem_addr(mem_addr_),
mem_valid(mem_valid_),
mem_resready(mem_resready_),
mem_data(mem_data_),
mem_ready(mem_ready_),
mem_resvalid(mem_resvalid_) {
}
};
......@@ -70,9 +73,12 @@ struct MemWritePort {
MemWritePort(vluint8_t &mem_sel_, vluint32_t (&mem_be_)[4],
vluint32_t (&mem_addr_)[3], vluint32_t (&mem_data_)[32],
vluint8_t &mem_valid_, vluint8_t &mem_ready_)
: mem_sel(mem_sel_), mem_be(mem_be_), mem_addr(mem_addr_),
mem_data(mem_data_), mem_valid(mem_valid_), mem_ready(mem_ready_)
{
: mem_sel(mem_sel_),
mem_be(mem_be_),
mem_addr(mem_addr_),
mem_data(mem_data_),
mem_valid(mem_valid_),
mem_ready(mem_ready_) {
}
};
......@@ -85,9 +91,7 @@ class MemReader {
size_t cur_off;
public:
MemReader(MemReadPort &p_)
: p(p_), cur(0), cur_off(0)
{
MemReader(MemReadPort &p_) : p(p_), cur(0), cur_off(0) {
}
void step();
......@@ -103,9 +107,7 @@ class MemWriter {
size_t cur_off;
public:
MemWriter(MemWritePort &p_)
: p(p_), cur(0), cur_off(0)
{
MemWriter(MemWritePort &p_) : p(p_), cur(0), cur_off(0) {
}
void step();
......
sims/nic/corundum_bm/corundum_bm.cc
View file @ d4666c97
......@@ -22,79 +22,69 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include "sims/nic/corundum_bm/corundum_bm.h"
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <unistd.h>
#include <signal.h>
#include <cassert>
#include "sims/nic/corundum_bm/corundum_bm.h"
#include <cassert>
static nicbm::Runner *runner;
namespace corundum {
DescRing::DescRing()
: _dmaAddr(0), _sizeLog(0), _size(0), _sizeMask(0),
_index(0), _headPtr(0), _tailPtr(0),
_currHead(0), _currTail(0), active(false), armed(false)
{
: _dmaAddr(0),
_sizeLog(0),
_size(0),
_sizeMask(0),
_index(0),
_headPtr(0),
_tailPtr(0),
_currHead(0),
_currTail(0),
active(false),
armed(false) {
}
DescRing::~DescRing()
{
DescRing::~DescRing() {
}
addr_t
DescRing::dmaAddr()
{
addr_t DescRing::dmaAddr() {
return this->_dmaAddr;
}
size_t
DescRing::sizeLog()
{
size_t DescRing::sizeLog() {
return this->_sizeLog;
}
unsigned
DescRing::index()
{
unsigned DescRing::index() {
return this->_index;
}
ptr_t
DescRing::headPtr()
{
ptr_t DescRing::headPtr() {
return this->_headPtr;
}
ptr_t
DescRing::tailPtr()
{
ptr_t DescRing::tailPtr() {
return this->_tailPtr;
}
void
DescRing::setDMALower(uint32_t addr)
{
void DescRing::setDMALower(uint32_t addr) {
this->_dmaAddr &= 0xFFFFFFFF00000000;
this->_dmaAddr |= (addr_t)addr;
}
void
DescRing::setDMAUpper(uint32_t addr)
{
void DescRing::setDMAUpper(uint32_t addr) {
this->_dmaAddr &= 0xFFFFFFFF;
this->_dmaAddr |= ((addr_t)addr << 32);
}
void
DescRing::setSizeLog(size_t size_log)
{
void DescRing::setSizeLog(size_t size_log) {
if (size_log & QUEUE_ACTIVE_MASK) {
this->active = true;
} else {
......@@ -107,9 +97,7 @@ DescRing::setSizeLog(size_t size_log)
this->cplDma.resize(this->_size, false);
}
void
DescRing::setIndex(unsigned index)
{
void DescRing::setIndex(unsigned index) {
assert(!(index & QUEUE_CONT_MASK));
if (index & QUEUE_ARM_MASK) {
this->armed = true;
......@@ -117,34 +105,23 @@ DescRing::setIndex(unsigned index)
this->_index = index & 0xFF;
}
void
DescRing::setHeadPtr(ptr_t ptr)
{
void DescRing::setHeadPtr(ptr_t ptr) {
this->_headPtr = ptr;
}
void
DescRing::setTailPtr(ptr_t ptr)
{
void DescRing::setTailPtr(ptr_t ptr) {
this->_tailPtr = ptr;
}
bool
DescRing::empty()
{
bool DescRing::empty() {
return (this->_headPtr == this->_currTail);
}
bool
DescRing::full()
{
bool DescRing::full() {
return (this->_currHead - this->_tailPtr >= this->_size);
}
bool
DescRing::updatePtr(ptr_t ptr, bool head)
{
bool DescRing::updatePtr(ptr_t ptr, bool head) {
ptr_t curr_ptr = head ? this->_headPtr : this->_tailPtr;
if (ptr != curr_ptr) {
// out of order completion
......@@ -168,17 +145,13 @@ DescRing::updatePtr(ptr_t ptr, bool head)
return true;
}
EventRing::EventRing()
{
EventRing::EventRing() {
}
EventRing::~EventRing()
{
EventRing::~EventRing() {
}
void
EventRing::dmaDone(DMAOp *op)
{
void EventRing::dmaDone(DMAOp *op) {
assert(op->write);
switch (op->type) {
case DMA_TYPE_EVENT:
......@@ -193,17 +166,15 @@ EventRing::dmaDone(DMAOp *op)
}
}
void
EventRing::issueEvent(unsigned type, unsigned source)
{
void EventRing::issueEvent(unsigned type, unsigned source) {
assert(type == EVENT_TYPE_TX_CPL || type == EVENT_TYPE_RX_CPL);
if (this->armed) {
if (full()) {
fprintf(stderr, "Event ring is rull\n");
return;
}
addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) *
EVENT_SIZE;
addr_t dma_addr =
this->_dmaAddr + (this->_currHead & this->_sizeMask) * EVENT_SIZE;
/* Issue DMA write */
DMAOp *op = new DMAOp;
op->type = DMA_TYPE_EVENT;
......@@ -222,25 +193,20 @@ EventRing::issueEvent(unsigned type, unsigned source)
}
}
CplRing::CplRing(EventRing *eventRing)
: eventRing(eventRing)
{
CplRing::CplRing(EventRing *eventRing) : eventRing(eventRing) {
}
CplRing::~CplRing()
{
CplRing::~CplRing() {
}
void
CplRing::dmaDone(DMAOp *op)
{
void CplRing::dmaDone(DMAOp *op) {
assert(op->write);
switch (op->type) {
case DMA_TYPE_TX_CPL:
case DMA_TYPE_RX_CPL: {
if (updatePtr((ptr_t)op->tag, true)) {
unsigned type = op->type == DMA_TYPE_TX_CPL ? EVENT_TYPE_TX_CPL :
EVENT_TYPE_RX_CPL;
unsigned type =
op->type == DMA_TYPE_TX_CPL ? EVENT_TYPE_TX_CPL : EVENT_TYPE_RX_CPL;
this->eventRing->issueEvent(type, 0);
}
delete op;
......@@ -252,9 +218,7 @@ CplRing::dmaDone(DMAOp *op)
}
}
void
CplRing::complete(unsigned index, size_t len, bool tx)
{
void CplRing::complete(unsigned index, size_t len, bool tx) {
CplData data;
data.index = index;
data.len = len;
......@@ -262,8 +226,8 @@ CplRing::complete(unsigned index, size_t len, bool tx)
this->pending.push_back(data);
while (!full() && !this->pending.empty()) {
CplData &data = this->pending.front();
addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) *
CPL_SIZE;
addr_t dma_addr =
this->_dmaAddr + (this->_currHead & this->_sizeMask) * CPL_SIZE;
/* Issue DMA write */
DMAOp *op = new DMAOp;
op->type = data.tx ? DMA_TYPE_TX_CPL : DMA_TYPE_RX_CPL;
......@@ -282,18 +246,13 @@ CplRing::complete(unsigned index, size_t len, bool tx)
}
}
TxRing::TxRing(CplRing *cplRing)
: txCplRing(cplRing)
{
TxRing::TxRing(CplRing *cplRing) : txCplRing(cplRing) {
}
TxRing::~TxRing()
{
TxRing::~TxRing() {
}
void
TxRing::setHeadPtr(ptr_t ptr)
{
void TxRing::setHeadPtr(ptr_t ptr) {
DescRing::setHeadPtr(ptr);
while (this->_currTail != this->_headPtr) {
unsigned index = this->_currTail & this->_sizeMask;
......@@ -311,9 +270,7 @@ TxRing::setHeadPtr(ptr_t ptr)
}
}
void
TxRing::dmaDone(DMAOp *op)
{
void TxRing::dmaDone(DMAOp *op) {
switch (op->type) {
case DMA_TYPE_DESC: {
assert(!op->write);
......@@ -338,18 +295,13 @@ TxRing::dmaDone(DMAOp *op)
}
}
RxRing::RxRing(CplRing *cplRing)
: rxCplRing(cplRing)
{
RxRing::RxRing(CplRing *cplRing) : rxCplRing(cplRing) {
}
RxRing::~RxRing()
{
RxRing::~RxRing() {
}
void
RxRing::dmaDone(DMAOp *op)
{
void RxRing::dmaDone(DMAOp *op) {
switch (op->type) {
case DMA_TYPE_DESC: {
assert(!op->write);
......@@ -375,15 +327,13 @@ RxRing::dmaDone(DMAOp *op)
}
}
void
RxRing::rx(RxData *rx_data)
{
void RxRing::rx(RxData *rx_data) {
if (empty()) {
delete rx_data;
return;
}
addr_t dma_addr = this->_dmaAddr + (this->_currTail & this->_sizeMask) *
DESC_SIZE;
addr_t dma_addr =
this->_dmaAddr + (this->_currTail & this->_sizeMask) * DESC_SIZE;
/* Issue DMA read */
DMAOp *op = new DMAOp;
op->type = DMA_TYPE_DESC;
......@@ -398,146 +348,109 @@ RxRing::rx(RxData *rx_data)
}
Port::Port()
: _id(0), _features(0), _mtu(0),
_schedCount(0), _schedOffset(0), _schedStride(0),
_schedType(0), _rssMask(0), _schedEnable(false),
_queueEnable(false)
{
: _id(0),
_features(0),
_mtu(0),
_schedCount(0),
_schedOffset(0),
_schedStride(0),
_schedType(0),
_rssMask(0),
_schedEnable(false),
_queueEnable(false) {
}
Port::~Port()
{
Port::~Port() {
}
unsigned
Port::id()
{
unsigned Port::id() {
return this->_id;
}
unsigned
Port::features()
{
unsigned Port::features() {
return this->_features;
}
size_t
Port::mtu()
{
size_t Port::mtu() {
return this->_mtu;
}
size_t
Port::schedCount()
{
size_t Port::schedCount() {
return this->_schedCount;
}
addr_t
Port::schedOffset()
{
addr_t Port::schedOffset() {
return this->_schedOffset;
}
addr_t
Port::schedStride()
{
addr_t Port::schedStride() {
return this->_schedStride;
}
unsigned
Port::schedType()
{
unsigned Port::schedType() {
return this->_schedType;
}
unsigned
Port::rssMask()
{
unsigned Port::rssMask() {
return this->_rssMask;
}
void
Port::setId(unsigned id)
{
void Port::setId(unsigned id) {
this->_id = id;
}
void
Port::setFeatures(unsigned features)
{
this->_features = features & (IF_FEATURE_RSS |
IF_FEATURE_PTP_TS |
IF_FEATURE_TX_CSUM |
IF_FEATURE_RX_CSUM |
IF_FEATURE_RX_HASH);
void Port::setFeatures(unsigned features) {
this->_features =
features & (IF_FEATURE_RSS | IF_FEATURE_PTP_TS | IF_FEATURE_TX_CSUM |
IF_FEATURE_RX_CSUM | IF_FEATURE_RX_HASH);
}
void
Port::setMtu(size_t mtu)
{
void Port::setMtu(size_t mtu) {
this->_mtu = mtu;
}
void
Port::setSchedCount(size_t count)
{
void Port::setSchedCount(size_t count) {
this->_schedCount = count;
}
void
Port::setSchedOffset(addr_t offset)
{
void Port::setSchedOffset(addr_t offset) {
this->_schedOffset = offset;
}
void
Port::setSchedStride(addr_t stride)
{
void Port::setSchedStride(addr_t stride) {
this->_schedStride = stride;
}
void
Port::setSchedType(unsigned type)
{
void Port::setSchedType(unsigned type) {
this->_schedType = type;
}
void
Port::setRssMask(unsigned mask)
{
void Port::setRssMask(unsigned mask) {
this->_rssMask = mask;
}
void
Port::schedEnable()
{
void Port::schedEnable() {
this->_schedEnable = true;
}
void
Port::schedDisable()
{
void Port::schedDisable() {
this->_schedEnable = false;
}
void
Port::queueEnable()
{
void Port::queueEnable() {
this->_queueEnable = true;
}
void
Port::queueDisable()
{
void Port::queueDisable() {
this->_queueEnable = false;
}
Corundum::Corundum()
: txCplRing(&this->eventRing), rxCplRing(&this->eventRing),
txRing(&this->txCplRing), rxRing(&this->rxCplRing), features(0)
{
: txCplRing(&this->eventRing),
rxCplRing(&this->eventRing),
txRing(&this->txCplRing),
rxRing(&this->rxCplRing),
features(0) {
this->port.setId(0);
this->port.setFeatures(this->features);
this->port.setMtu(2048);
......@@ -549,13 +462,10 @@ Corundum::Corundum()
this->port.schedDisable();
}
Corundum::~Corundum()
{
Corundum::~Corundum() {
}
reg_t
Corundum::reg_read(uint8_t bar, addr_t addr)
{
reg_t Corundum::reg_read(uint8_t bar, addr_t addr) {
switch (addr) {
case REG_FW_ID:
return 32;
......@@ -645,9 +555,7 @@ Corundum::reg_read(uint8_t bar, addr_t addr)
}
}
void
Corundum::reg_write(uint8_t bar, uint64_t addr, reg_t val)
{
void Corundum::reg_write(uint8_t bar, uint64_t addr, reg_t val) {
switch (addr) {
case REG_FW_ID:
case REG_FW_VER:
......@@ -778,9 +686,7 @@ Corundum::reg_write(uint8_t bar, uint64_t addr, reg_t val)
}
}
void
Corundum::setup_intro(struct cosim_pcie_proto_dev_intro &di)
{
void Corundum::setup_intro(struct cosim_pcie_proto_dev_intro &di) {
di.bars[0].len = 1 << 24;
di.bars[0].flags = COSIM_PCIE_PROTO_BAR_64;
di.pci_vendor_id = 0x5543;
......@@ -791,16 +697,12 @@ Corundum::setup_intro(struct cosim_pcie_proto_dev_intro &di)
di.pci_msi_nvecs = 32;
}
void
Corundum::dma_complete(nicbm::DMAOp &op)
{
void Corundum::dma_complete(nicbm::DMAOp &op) {
DMAOp *op_ = reinterpret_cast<DMAOp *>(&op);
op_->ring->dmaDone(op_);
}
void
Corundum::eth_rx(uint8_t port, const void *data, size_t len)
{
void Corundum::eth_rx(uint8_t port, const void *data, size_t len) {
RxData *rx_data = new RxData;
memcpy((void *)rx_data->data, data, len);
rx_data->len = len;
......@@ -809,11 +711,8 @@ Corundum::eth_rx(uint8_t port, const void *data, size_t len)
} // namespace corundum
using namespace corundum;
int main(int argc, char *argv[])
{
Corundum dev;
int main(int argc, char *argv[]) {
corundum::Corundum dev;
runner = new nicbm::Runner(dev);
return runner->runMain(argc, argv);
}
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