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Commit c7e904bf authored by Antoine Kaufmann's avatar Antoine Kaufmann
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lib/nicbm: refactor identifier names for google style

parent 78f27099
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Showing with 325 additions and 325 deletions
lib/simbricks/nicbm/nicbm.cc
View file @ c7e904bf
......@@ -57,97 +57,97 @@ static void sigusr1_handler(int dummy) {
fprintf(stderr, "main_time = %lu\n", main_time);
}
volatile union SimbricksProtoPcieD2H *Runner::d2h_alloc(void) {
volatile union SimbricksProtoPcieD2H *Runner::D2HAlloc() {
volatile union SimbricksProtoPcieD2H *msg;
while ((msg = SimbricksNicIfD2HAlloc(&nsparams, main_time)) == NULL) {
fprintf(stderr, "d2h_alloc: no entry available\n");
while ((msg = SimbricksNicIfD2HAlloc(&nsparams_, main_time)) == NULL) {
fprintf(stderr, "D2HAlloc: no entry available\n");
}
return msg;
}
volatile union SimbricksProtoNetD2N *Runner::d2n_alloc(void) {
volatile union SimbricksProtoNetD2N *Runner::D2NAlloc() {
volatile union SimbricksProtoNetD2N *msg;
while ((msg = SimbricksNicIfD2NAlloc(&nsparams, main_time)) == NULL) {
fprintf(stderr, "d2n_alloc: no entry available\n");
while ((msg = SimbricksNicIfD2NAlloc(&nsparams_, main_time)) == NULL) {
fprintf(stderr, "D2NAlloc: no entry available\n");
}
return msg;
}
void Runner::issue_dma(DMAOp &op) {
if (dma_pending < DMA_MAX_PENDING) {
void Runner::IssueDma(DMAOp &op) {
if (dma_pending_ < DMA_MAX_PENDING) {
// can directly issue
#ifdef DEBUG_NICBM
printf("nicbm: issuing dma op %p addr %lx len %zu pending %zu\n", &op,
op.dma_addr, op.len, dma_pending);
#endif
dma_do(op);
DmaDo(op);
} else {
#ifdef DEBUG_NICBM
printf("nicbm: enqueuing dma op %p addr %lx len %zu pending %zu\n", &op,
op.dma_addr, op.len, dma_pending);
#endif
dma_queue.push_back(&op);
dma_queue_.push_back(&op);
}
}
void Runner::dma_trigger() {
if (dma_queue.empty() || dma_pending == DMA_MAX_PENDING)
void Runner::DmaTrigger() {
if (dma_queue_.empty() || dma_pending_ == DMA_MAX_PENDING)
return;
DMAOp *op = dma_queue.front();
dma_queue.pop_front();
DMAOp *op = dma_queue_.front();
dma_queue_.pop_front();
dma_do(*op);
DmaDo(*op);
}
void Runner::dma_do(DMAOp &op) {
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
dma_pending++;
void Runner::DmaDo(DMAOp &op) {
volatile union SimbricksProtoPcieD2H *msg = D2HAlloc();
dma_pending_++;
#ifdef DEBUG_NICBM
printf("nicbm: executing dma op %p addr %lx len %zu pending %zu\n", &op,
op.dma_addr, op.len, dma_pending);
op.dma_addr_, op.len_, dma_pending_);
#endif
if (op.write) {
if (op.write_) {
volatile struct SimbricksProtoPcieD2HWrite *write = &msg->write;
if (dintro.d2h_elen < sizeof(*write) + op.len) {
if (dintro_.d2h_elen < sizeof(*write) + op.len_) {
fprintf(stderr,
"issue_dma: write too big (%zu), can only fit up "
"to (%zu)\n",
op.len, dintro.d2h_elen - sizeof(*write));
op.len_, dintro_.d2h_elen - sizeof(*write));
abort();
}
write->req_id = (uintptr_t)&op;
write->offset = op.dma_addr;
write->len = op.len;
memcpy((void *)write->data, (void *)op.data, op.len);
write->offset = op.dma_addr_;
write->len = op.len_;
memcpy((void *)write->data, (void *)op.data_, op.len_);
// WMB();
write->own_type =
SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITE | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
} else {
volatile struct SimbricksProtoPcieD2HRead *read = &msg->read;
if (dintro.h2d_elen <
sizeof(struct SimbricksProtoPcieH2DReadcomp) + op.len) {
if (dintro_.h2d_elen <
sizeof(struct SimbricksProtoPcieH2DReadcomp) + op.len_) {
fprintf(stderr,
"issue_dma: write too big (%zu), can only fit up "
"to (%zu)\n",
op.len,
dintro.h2d_elen - sizeof(struct SimbricksProtoPcieH2DReadcomp));
op.len_,
dintro_.h2d_elen - sizeof(struct SimbricksProtoPcieH2DReadcomp));
abort();
}
read->req_id = (uintptr_t)&op;
read->offset = op.dma_addr;
read->len = op.len;
read->offset = op.dma_addr_;
read->len = op.len_;
// WMB();
read->own_type =
SIMBRICKS_PROTO_PCIE_D2H_MSG_READ | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
}
void Runner::msi_issue(uint8_t vec) {
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
void Runner::MsiIssue(uint8_t vec) {
volatile union SimbricksProtoPcieD2H *msg = D2HAlloc();
#ifdef DEBUG_NICBM
printf("nicbm: issue MSI interrupt vec %u\n", vec);
#endif
......@@ -161,8 +161,8 @@ void Runner::msi_issue(uint8_t vec) {
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::msix_issue(uint8_t vec) {
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
void Runner::MsiXIssue(uint8_t vec) {
volatile union SimbricksProtoPcieD2H *msg = D2HAlloc();
#ifdef DEBUG_NICBM
printf("nicbm: issue MSI-X interrupt vec %u\n", vec);
#endif
......@@ -176,22 +176,22 @@ void Runner::msix_issue(uint8_t vec) {
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::event_schedule(TimedEvent &evt) {
events.insert(&evt);
void Runner::EventSchedule(TimedEvent &evt) {
events_.insert(&evt);
}
void Runner::event_cancel(TimedEvent &evt) {
events.erase(&evt);
void Runner::EventCancel(TimedEvent &evt) {
events_.erase(&evt);
}
void Runner::h2d_read(volatile struct SimbricksProtoPcieH2DRead *read) {
void Runner::H2DRead(volatile struct SimbricksProtoPcieH2DRead *read) {
volatile union SimbricksProtoPcieD2H *msg;
volatile struct SimbricksProtoPcieD2HReadcomp *rc;
msg = d2h_alloc();
msg = D2HAlloc();
rc = &msg->readcomp;
dev.reg_read(read->bar, read->offset, (void *)rc->data, read->len);
dev_.RegRead(read->bar, read->offset, (void *)rc->data, read->len);
rc->req_id = read->req_id;
#ifdef DEBUG_NICBM
......@@ -206,11 +206,11 @@ void Runner::h2d_read(volatile struct SimbricksProtoPcieH2DRead *read) {
SIMBRICKS_PROTO_PCIE_D2H_MSG_READCOMP | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::h2d_write(volatile struct SimbricksProtoPcieH2DWrite *write) {
void Runner::H2DWrite(volatile struct SimbricksProtoPcieH2DWrite *write) {
volatile union SimbricksProtoPcieD2H *msg;
volatile struct SimbricksProtoPcieD2HWritecomp *wc;
msg = d2h_alloc();
msg = D2HAlloc();
wc = &msg->writecomp;
#ifdef DEBUG_NICBM
......@@ -219,7 +219,7 @@ void Runner::h2d_write(volatile struct SimbricksProtoPcieH2DWrite *write) {
printf("nicbm: write(off=0x%lx, len=%u, val=0x%lx)\n", write->offset,
write->len, dbg_val);
#endif
dev.reg_write(write->bar, write->offset, (void *)write->data, write->len);
dev_.RegWrite(write->bar, write->offset, (void *)write->data, write->len);
wc->req_id = write->req_id;
// WMB();
......@@ -228,7 +228,7 @@ void Runner::h2d_write(volatile struct SimbricksProtoPcieH2DWrite *write) {
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::h2d_readcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc) {
void Runner::H2DReadcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc) {
DMAOp *op = (DMAOp *)(uintptr_t)rc->req_id;
#ifdef DEBUG_NICBM
......@@ -236,14 +236,14 @@ void Runner::h2d_readcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc) {
op->len);
#endif
memcpy(op->data, (void *)rc->data, op->len);
dev.dma_complete(*op);
memcpy(op->data_, (void *)rc->data, op->len_);
dev_.DmaComplete(*op);
dma_pending--;
dma_trigger();
dma_pending_--;
DmaTrigger();
}
void Runner::h2d_writecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc) {
void Runner::H2DWritecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc) {
DMAOp *op = (DMAOp *)(uintptr_t)wc->req_id;
#ifdef DEBUG_NICBM
......@@ -251,30 +251,30 @@ void Runner::h2d_writecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc) {
op->dma_addr, op->len);
#endif
dev.dma_complete(*op);
dev_.DmaComplete(*op);
dma_pending--;
dma_trigger();
dma_pending_--;
DmaTrigger();
}
void Runner::h2d_devctrl(volatile struct SimbricksProtoPcieH2DDevctrl *dc) {
dev.devctrl_update(*(struct SimbricksProtoPcieH2DDevctrl *)dc);
void Runner::H2DDevctrl(volatile struct SimbricksProtoPcieH2DDevctrl *dc) {
dev_.DevctrlUpdate(*(struct SimbricksProtoPcieH2DDevctrl *)dc);
}
void Runner::eth_recv(volatile struct SimbricksProtoNetN2DRecv *recv) {
void Runner::EthRecv(volatile struct SimbricksProtoNetN2DRecv *recv) {
#ifdef DEBUG_NICBM
printf("nicbm: eth rx: port %u len %u\n", recv->port, recv->len);
#endif
dev.eth_rx(recv->port, (void *)recv->data, recv->len);
dev_.EthRx(recv->port, (void *)recv->data, recv->len);
}
void Runner::eth_send(const void *data, size_t len) {
void Runner::EthSend(const void *data, size_t len) {
#ifdef DEBUG_NICBM
printf("nicbm: eth tx: len %zu\n", len);
#endif
volatile union SimbricksProtoNetD2N *msg = d2n_alloc();
volatile union SimbricksProtoNetD2N *msg = D2NAlloc();
volatile struct SimbricksProtoNetD2NSend *send = &msg->send;
send->port = 0; // single port
send->len = len;
......@@ -283,9 +283,9 @@ void Runner::eth_send(const void *data, size_t len) {
SIMBRICKS_PROTO_NET_D2N_OWN_NET;
}
void Runner::poll_h2d() {
void Runner::PollH2D() {
volatile union SimbricksProtoPcieH2D *msg =
SimbricksNicIfH2DPoll(&nsparams, main_time);
SimbricksNicIfH2DPoll(&nsparams_, main_time);
uint8_t type;
if (msg == NULL)
......@@ -294,23 +294,23 @@ void Runner::poll_h2d() {
type = msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_H2D_MSG_MASK;
switch (type) {
case SIMBRICKS_PROTO_PCIE_H2D_MSG_READ:
h2d_read(&msg->read);
H2DRead(&msg->read);
break;
case SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITE:
h2d_write(&msg->write);
H2DWrite(&msg->write);
break;
case SIMBRICKS_PROTO_PCIE_H2D_MSG_READCOMP:
h2d_readcomp(&msg->readcomp);
H2DReadcomp(&msg->readcomp);
break;
case SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITECOMP:
h2d_writecomp(&msg->writecomp);
H2DWritecomp(&msg->writecomp);
break;
case SIMBRICKS_PROTO_PCIE_H2D_MSG_DEVCTRL:
h2d_devctrl(&msg->devctrl);
H2DDevctrl(&msg->devctrl);
break;
case SIMBRICKS_PROTO_PCIE_H2D_MSG_SYNC:
......@@ -324,9 +324,9 @@ void Runner::poll_h2d() {
SimbricksNicIfH2DNext();
}
void Runner::poll_n2d() {
void Runner::PollN2D() {
volatile union SimbricksProtoNetN2D *msg =
SimbricksNicIfN2DPoll(&nsparams, main_time);
SimbricksNicIfN2DPoll(&nsparams_, main_time);
uint8_t t;
if (msg == NULL)
......@@ -335,7 +335,7 @@ void Runner::poll_n2d() {
t = msg->dummy.own_type & SIMBRICKS_PROTO_NET_N2D_MSG_MASK;
switch (t) {
case SIMBRICKS_PROTO_NET_N2D_MSG_RECV:
eth_recv(&msg->recv);
EthRecv(&msg->recv);
break;
case SIMBRICKS_PROTO_NET_N2D_MSG_SYNC:
......@@ -349,50 +349,50 @@ void Runner::poll_n2d() {
SimbricksNicIfN2DNext();
}
uint64_t Runner::time_ps() const {
uint64_t Runner::TimePs() const {
return main_time;
}
uint64_t Runner::get_mac_addr() const {
return mac_addr;
uint64_t Runner::GetMacAddr() const {
return mac_addr_;
}
bool Runner::event_next(uint64_t &retval) {
if (events.empty())
bool Runner::EventNext(uint64_t &retval) {
if (events_.empty())
return false;
retval = (*events.begin())->time;
retval = (*events_.begin())->time_;
return true;
}
void Runner::event_trigger() {
auto it = events.begin();
if (it == events.end())
void Runner::EventTrigger() {
auto it = events_.begin();
if (it == events_.end())
return;
TimedEvent *ev = *it;
// event is in the future
if (ev->time > main_time)
if (ev->time_ > main_time)
return;
events.erase(it);
dev.timed_event(*ev);
events_.erase(it);
dev_.Timed(*ev);
}
Runner::Runner(Device &dev_) : dev(dev_), events(event_cmp()) {
Runner::Runner(Device &dev) : dev_(dev), events_(EventCmp()) {
// mac_addr = lrand48() & ~(3ULL << 46);
dma_pending = 0;
dma_pending_ = 0;
srand48(time(NULL) ^ getpid());
mac_addr = lrand48();
mac_addr <<= 16;
mac_addr ^= lrand48();
mac_addr &= ~3ULL;
mac_addr_ = lrand48();
mac_addr_ <<= 16;
mac_addr_ ^= lrand48();
mac_addr_ &= ~3ULL;
std::cerr << std::hex << mac_addr << std::endl;
std::cerr << std::hex << mac_addr_ << std::endl;
}
int Runner::runMain(int argc, char *argv[]) {
int Runner::RunMain(int argc, char *argv[]) {
uint64_t next_ts;
uint64_t max_step = 10000;
uint64_t sync_period = 100 * 1000ULL;
......@@ -421,42 +421,42 @@ int Runner::runMain(int argc, char *argv[]) {
signal(SIGINT, sigint_handler);
signal(SIGUSR1, sigusr1_handler);
memset(&dintro, 0, sizeof(dintro));
dev.setup_intro(dintro);
nsparams.sync_pci = 1;
nsparams.sync_eth = 1;
nsparams.pci_socket_path = argv[1];
nsparams.eth_socket_path = argv[2];
nsparams.shm_path = argv[3];
nsparams.pci_latency = pci_latency;
nsparams.eth_latency = eth_latency;
nsparams.sync_delay = sync_period;
memset(&dintro_, 0, sizeof(dintro_));
dev_.SetupIntro(dintro_);
nsparams_.sync_pci = 1;
nsparams_.sync_eth = 1;
nsparams_.pci_socket_path = argv[1];
nsparams_.eth_socket_path = argv[2];
nsparams_.shm_path = argv[3];
nsparams_.pci_latency = pci_latency;
nsparams_.eth_latency = eth_latency;
nsparams_.sync_delay = sync_period;
assert(sync_mode == SIMBRICKS_PROTO_SYNC_SIMBRICKS ||
sync_mode == SIMBRICKS_PROTO_SYNC_BARRIER);
nsparams.sync_mode = sync_mode;
nsparams_.sync_mode = sync_mode;
if (SimbricksNicIfInit(&nsparams, &dintro)) {
if (SimbricksNicIfInit(&nsparams_, &dintro_)) {
return EXIT_FAILURE;
}
fprintf(stderr, "sync_pci=%d sync_eth=%d\n", nsparams.sync_pci,
nsparams.sync_eth);
fprintf(stderr, "sync_pci=%d sync_eth=%d\n", nsparams_.sync_pci,
nsparams_.sync_eth);
bool is_sync = nsparams.sync_pci || nsparams.sync_eth;
bool is_sync = nsparams_.sync_pci || nsparams_.sync_eth;
while (!exiting) {
while (SimbricksNicIfSync(&nsparams, main_time)) {
while (SimbricksNicIfSync(&nsparams_, main_time)) {
fprintf(stderr, "warn: SimbricksNicIfSync failed (t=%lu)\n", main_time);
}
SimbricksNicIfAdvanceEpoch(&nsparams, main_time);
SimbricksNicIfAdvanceEpoch(&nsparams_, main_time);
do {
poll_h2d();
poll_n2d();
event_trigger();
PollH2D();
PollN2D();
EventTrigger();
if (is_sync) {
next_ts = SimbricksNicIfNextTimestamp(&nsparams);
next_ts = SimbricksNicIfNextTimestamp(&nsparams_);
if (next_ts > main_time + max_step)
next_ts = main_time + max_step;
} else {
......@@ -464,10 +464,10 @@ int Runner::runMain(int argc, char *argv[]) {
}
uint64_t ev_ts;
if (event_next(ev_ts) && ev_ts < next_ts)
if (EventNext(ev_ts) && ev_ts < next_ts)
next_ts = ev_ts;
} while (next_ts <= main_time && !exiting);
main_time = SimbricksNicIfAdvanceTime(&nsparams, next_ts);
main_time = SimbricksNicIfAdvanceTime(&nsparams_, next_ts);
}
fprintf(stderr, "exit main_time: %lu\n", main_time);
......@@ -475,14 +475,14 @@ int Runner::runMain(int argc, char *argv[]) {
return 0;
}
void Runner::Device::timed_event(TimedEvent &te) {
void Runner::Device::Timed(TimedEvent &te) {
}
void Runner::Device::devctrl_update(
void Runner::Device::DevctrlUpdate(
struct SimbricksProtoPcieH2DDevctrl &devctrl) {
int_intx_en = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_INTX_EN;
int_msi_en = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_MSI_EN;
int_msix_en = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_MSIX_EN;
int_intx_en_ = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_INTX_EN;
int_msi_en_ = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_MSI_EN;
int_msix_en_ = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_MSIX_EN;
}
} // namespace nicbm
lib/simbricks/nicbm/nicbm.h
View file @ c7e904bf
......@@ -36,23 +36,23 @@ extern "C" {
namespace nicbm {
static const size_t MAX_DMA_LEN = 2048;
static const size_t kMaxDmaLen = 2048;
class DMAOp {
public:
virtual ~DMAOp() {
}
bool write;
uint64_t dma_addr;
size_t len;
void *data;
bool write_;
uint64_t dma_addr_;
size_t len_;
void *data_;
};
class TimedEvent {
public:
virtual ~TimedEvent() {
}
uint64_t time;
uint64_t time_;
};
/**
......@@ -65,104 +65,104 @@ class Runner {
public:
class Device {
protected:
bool int_intx_en;
bool int_msi_en;
bool int_msix_en;
bool int_intx_en_;
bool int_msi_en_;
bool int_msix_en_;
public:
/**
* Initialize device specific parameters (pci dev/vendor id,
* BARs etc. in intro struct.
*/
virtual void setup_intro(struct SimbricksProtoPcieDevIntro &di) = 0;
virtual void SetupIntro(struct SimbricksProtoPcieDevIntro &di) = 0;
/**
* execute a register read from `bar`:`addr` of length `len`.
* Should store result in `dest`.
*/
virtual void reg_read(uint8_t bar, uint64_t addr, void *dest,
virtual void RegRead(uint8_t bar, uint64_t addr, void *dest,
size_t len) = 0;
/**
* execute a register write to `bar`:`addr` of length `len`,
* with the data in `src`.
*/
virtual void reg_write(uint8_t bar, uint64_t addr, const void *src,
virtual void RegWrite(uint8_t bar, uint64_t addr, const void *src,
size_t len) = 0;
/**
* the previously issued DMA operation `op` completed.
*/
virtual void dma_complete(DMAOp &op) = 0;
virtual void DmaComplete(DMAOp &op) = 0;
/**
* A packet has arrived on the wire, of length `len` with
* payload `data`.
*/
virtual void eth_rx(uint8_t port, const void *data, size_t len) = 0;
virtual void EthRx(uint8_t port, const void *data, size_t len) = 0;
/**
* A timed event is due.
*/
virtual void timed_event(TimedEvent &ev);
virtual void Timed(TimedEvent &ev);
/**
* Device control update
*/
virtual void devctrl_update(struct SimbricksProtoPcieH2DDevctrl &devctrl);
virtual void DevctrlUpdate(struct SimbricksProtoPcieH2DDevctrl &devctrl);
};
protected:
struct event_cmp {
struct EventCmp {
bool operator()(TimedEvent *a, TimedEvent *b) {
return a->time < b->time;
return a->time_ < b->time_;
}
};
Device &dev;
std::set<TimedEvent *, event_cmp> events;
std::deque<DMAOp *> dma_queue;
size_t dma_pending;
uint64_t mac_addr;
struct SimbricksNicIfParams nsparams;
struct SimbricksProtoPcieDevIntro dintro;
Device &dev_;
std::set<TimedEvent *, EventCmp> events_;
std::deque<DMAOp *> dma_queue_;
size_t dma_pending_;
uint64_t mac_addr_;
struct SimbricksNicIfParams nsparams_;
struct SimbricksProtoPcieDevIntro dintro_;
volatile union SimbricksProtoPcieD2H *d2h_alloc(void);
volatile union SimbricksProtoNetD2N *d2n_alloc(void);
volatile union SimbricksProtoPcieD2H *D2HAlloc();
volatile union SimbricksProtoNetD2N *D2NAlloc();
void h2d_read(volatile struct SimbricksProtoPcieH2DRead *read);
void h2d_write(volatile struct SimbricksProtoPcieH2DWrite *write);
void h2d_readcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc);
void h2d_writecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc);
void h2d_devctrl(volatile struct SimbricksProtoPcieH2DDevctrl *dc);
void poll_h2d();
void H2DRead(volatile struct SimbricksProtoPcieH2DRead *read);
void H2DWrite(volatile struct SimbricksProtoPcieH2DWrite *write);
void H2DReadcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc);
void H2DWritecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc);
void H2DDevctrl(volatile struct SimbricksProtoPcieH2DDevctrl *dc);
void PollH2D();
void eth_recv(volatile struct SimbricksProtoNetN2DRecv *recv);
void poll_n2d();
void EthRecv(volatile struct SimbricksProtoNetN2DRecv *recv);
void PollN2D();
bool event_next(uint64_t &retval);
void event_trigger();
bool EventNext(uint64_t &retval);
void EventTrigger();
void dma_do(DMAOp &op);
void dma_trigger();
void DmaDo(DMAOp &op);
void DmaTrigger();
public:
Runner(Device &dev_);
/** Run the simulation */
int runMain(int argc, char *argv[]);
int RunMain(int argc, char *argv[]);
/* these three are for `Runner::Device`. */
void issue_dma(DMAOp &op);
void msi_issue(uint8_t vec);
void msix_issue(uint8_t vec);
void eth_send(const void *data, size_t len);
void IssueDma(DMAOp &op);
void MsiIssue(uint8_t vec);
void MsiXIssue(uint8_t vec);
void EthSend(const void *data, size_t len);
void event_schedule(TimedEvent &evt);
void event_cancel(TimedEvent &evt);
void EventSchedule(TimedEvent &evt);
void EventCancel(TimedEvent &evt);
uint64_t time_ps() const;
uint64_t get_mac_addr() const;
uint64_t TimePs() const;
uint64_t GetMacAddr() const;
};
/**
......@@ -171,21 +171,21 @@ class Runner {
template <class TReg = uint32_t>
class SimpleDevice : public Runner::Device {
public:
virtual TReg reg_read(uint8_t bar, uint64_t addr) = 0;
virtual void reg_write(uint8_t bar, uint64_t addr, TReg val) = 0;
virtual TReg RegRead(uint8_t bar, uint64_t addr) = 0;
virtual void RegWrite(uint8_t bar, uint64_t addr, TReg val) = 0;
virtual void reg_read(uint8_t bar, uint64_t addr, void *dest, size_t len) {
void RegRead(uint8_t bar, uint64_t addr, void *dest, size_t len) override {
assert(len == sizeof(TReg));
TReg r = reg_read(bar, addr);
TReg r = RegRead(bar, addr);
memcpy(dest, &r, sizeof(r));
}
virtual void reg_write(uint8_t bar, uint64_t addr, const void *src,
size_t len) {
void RegWrite(uint8_t bar, uint64_t addr, const void *src,
size_t len) override {
assert(len == sizeof(TReg));
TReg r;
memcpy(&r, src, sizeof(r));
reg_write(bar, addr, r);
RegWrite(bar, addr, r);
}
};
} // namespace nicbm
......
sims/nic/corundum_bm/corundum_bm.cc
View file @ c7e904bf
......@@ -152,11 +152,11 @@ EventRing::~EventRing() {
}
void EventRing::dmaDone(DMAOp *op) {
assert(op->write);
assert(op->write_);
switch (op->type) {
case DMA_TYPE_EVENT:
if (updatePtr((ptr_t)op->tag, true)) {
runner->msi_issue(0);
runner->MsiIssue(0);
}
delete op;
break;
......@@ -178,16 +178,16 @@ void EventRing::issueEvent(unsigned type, unsigned source) {
/* Issue DMA write */
DMAOp *op = new DMAOp;
op->type = DMA_TYPE_EVENT;
op->dma_addr = dma_addr;
op->len = EVENT_SIZE;
op->dma_addr_ = dma_addr;
op->len_ = EVENT_SIZE;
op->ring = this;
op->tag = this->_currHead;
op->write = true;
Event *event = (Event *)op->data;
op->write_ = true;
Event *event = (Event *)op->data_;
memset(event, 0, sizeof(Event));
event->type = type;
event->source = source;
runner->issue_dma(*op);
runner->IssueDma(*op);
this->_currHead++;
this->armed = false;
}
......@@ -200,7 +200,7 @@ CplRing::~CplRing() {
}
void CplRing::dmaDone(DMAOp *op) {
assert(op->write);
assert(op->write_);
switch (op->type) {
case DMA_TYPE_TX_CPL:
case DMA_TYPE_RX_CPL: {
......@@ -231,17 +231,17 @@ void CplRing::complete(unsigned index, size_t len, bool tx) {
/* Issue DMA write */
DMAOp *op = new DMAOp;
op->type = data.tx ? DMA_TYPE_TX_CPL : DMA_TYPE_RX_CPL;
op->dma_addr = dma_addr;
op->len = CPL_SIZE;
op->dma_addr_ = dma_addr;
op->len_ = CPL_SIZE;
op->ring = this;
op->tag = this->_currHead;
op->write = true;
Cpl *cpl = (Cpl *)op->data;
op->write_ = true;
Cpl *cpl = (Cpl *)op->data_;
memset(cpl, 0, sizeof(Cpl));
cpl->index = data.index;
cpl->len = data.len;
this->pending.pop_front();
runner->issue_dma(*op);
runner->IssueDma(*op);
this->_currHead++;
}
}
......@@ -260,12 +260,12 @@ void TxRing::setHeadPtr(ptr_t ptr) {
/* Issue DMA read */
DMAOp *op = new DMAOp;
op->type = DMA_TYPE_DESC;
op->dma_addr = dma_addr;
op->len = DESC_SIZE;
op->dma_addr_ = dma_addr;
op->len_ = DESC_SIZE;
op->ring = this;
op->tag = this->_currTail;
op->write = false;
runner->issue_dma(*op);
op->write_ = false;
runner->IssueDma(*op);
this->_currTail++;
}
}
......@@ -273,20 +273,20 @@ void TxRing::setHeadPtr(ptr_t ptr) {
void TxRing::dmaDone(DMAOp *op) {
switch (op->type) {
case DMA_TYPE_DESC: {
assert(!op->write);
Desc *desc = (Desc *)op->data;
assert(!op->write_);
Desc *desc = (Desc *)op->data_;
op->type = DMA_TYPE_MEM;
op->dma_addr = desc->addr;
op->len = desc->len;
op->write = false;
runner->issue_dma(*op);
op->dma_addr_ = desc->addr;
op->len_ = desc->len;
op->write_ = false;
runner->IssueDma(*op);
break;
}
case DMA_TYPE_MEM:
assert(!op->write);
runner->eth_send(op->data, op->len);
assert(!op->write_);
runner->EthSend(op->data_, op->len_);
updatePtr((ptr_t)op->tag, false);
this->txCplRing->complete(op->tag, op->len, true);
this->txCplRing->complete(op->tag, op->len_, true);
delete op;
break;
default:
......@@ -304,21 +304,21 @@ RxRing::~RxRing() {
void RxRing::dmaDone(DMAOp *op) {
switch (op->type) {
case DMA_TYPE_DESC: {
assert(!op->write);
Desc *desc = (Desc *)op->data;
assert(!op->write_);
Desc *desc = (Desc *)op->data_;
op->type = DMA_TYPE_MEM;
op->dma_addr = desc->addr;
op->len = op->rx_data->len;
memcpy((void *)op->data, (void *)op->rx_data->data, op->len);
op->dma_addr_ = desc->addr;
op->len_ = op->rx_data->len;
memcpy((void *)op->data_, (void *)op->rx_data->data, op->len_);
delete op->rx_data;
op->write = true;
runner->issue_dma(*op);
op->write_ = true;
runner->IssueDma(*op);
break;
}
case DMA_TYPE_MEM:
assert(op->write);
assert(op->write_);
updatePtr((ptr_t)op->tag, false);
this->rxCplRing->complete(op->tag, op->len, false);
this->rxCplRing->complete(op->tag, op->len_, false);
delete op;
break;
default:
......@@ -337,13 +337,13 @@ void RxRing::rx(RxData *rx_data) {
/* Issue DMA read */
DMAOp *op = new DMAOp;
op->type = DMA_TYPE_DESC;
op->dma_addr = dma_addr;
op->len = DESC_SIZE;
op->dma_addr_ = dma_addr;
op->len_ = DESC_SIZE;
op->ring = this;
op->rx_data = rx_data;
op->tag = this->_currTail;
op->write = false;
runner->issue_dma(*op);
op->write_ = false;
runner->IssueDma(*op);
this->_currTail++;
}
......@@ -465,7 +465,7 @@ Corundum::Corundum()
Corundum::~Corundum() {
}
reg_t Corundum::reg_read(uint8_t bar, addr_t addr) {
reg_t Corundum::RegRead(uint8_t bar, addr_t addr) {
switch (addr) {
case REG_FW_ID:
return 32;
......@@ -555,7 +555,7 @@ reg_t Corundum::reg_read(uint8_t bar, addr_t addr) {
}
}
void Corundum::reg_write(uint8_t bar, uint64_t addr, reg_t val) {
void Corundum::RegWrite(uint8_t bar, uint64_t addr, reg_t val) {
switch (addr) {
case REG_FW_ID:
case REG_FW_VER:
......@@ -686,7 +686,7 @@ void Corundum::reg_write(uint8_t bar, uint64_t addr, reg_t val) {
}
}
void Corundum::setup_intro(struct SimbricksProtoPcieDevIntro &di) {
void Corundum::SetupIntro(struct SimbricksProtoPcieDevIntro &di) {
di.bars[0].len = 1 << 24;
di.bars[0].flags = SIMBRICKS_PROTO_PCIE_BAR_64;
di.pci_vendor_id = 0x5543;
......@@ -697,12 +697,12 @@ void Corundum::setup_intro(struct SimbricksProtoPcieDevIntro &di) {
di.pci_msi_nvecs = 32;
}
void Corundum::dma_complete(nicbm::DMAOp &op) {
void Corundum::DmaComplete(nicbm::DMAOp &op) {
DMAOp *op_ = reinterpret_cast<DMAOp *>(&op);
op_->ring->dmaDone(op_);
}
void Corundum::eth_rx(uint8_t port, const void *data, size_t len) {
void Corundum::EthRx(uint8_t port, const void *data, size_t len) {
RxData *rx_data = new RxData;
memcpy((void *)rx_data->data, data, len);
rx_data->len = len;
......@@ -714,5 +714,5 @@ void Corundum::eth_rx(uint8_t port, const void *data, size_t len) {
int main(int argc, char *argv[]) {
corundum::Corundum dev;
runner = new nicbm::Runner(dev);
return runner->runMain(argc, argv);
return runner->RunMain(argc, argv);
}
sims/nic/corundum_bm/corundum_bm.h
View file @ c7e904bf
......@@ -178,7 +178,7 @@ struct RxData {
struct DMAOp : public nicbm::DMAOp {
DMAOp() {
data = databuf;
data_ = databuf;
}
uint8_t type;
......@@ -323,11 +323,11 @@ class Corundum : public nicbm::SimpleDevice<reg_t> {
Corundum();
~Corundum();
virtual void setup_intro(struct SimbricksProtoPcieDevIntro &di);
virtual reg_t reg_read(uint8_t bar, addr_t addr);
virtual void reg_write(uint8_t bar, addr_t addr, reg_t val);
virtual void dma_complete(nicbm::DMAOp &op);
virtual void eth_rx(uint8_t port, const void *data, size_t len);
void SetupIntro(struct SimbricksProtoPcieDevIntro &di) override;
reg_t RegRead(uint8_t bar, addr_t addr) override;
void RegWrite(uint8_t bar, addr_t addr, reg_t val) override;
void DmaComplete(nicbm::DMAOp &op) override;
void EthRx(uint8_t port, const void *data, size_t len) override;
private:
EventRing eventRing;
......
sims/nic/i40e_bm/i40e_adminq.cc
View file @ c7e904bf
......@@ -226,7 +226,7 @@ void queue_admin_tx::admin_desc_ctx::process() {
reinterpret_cast<struct i40e_aqc_mac_address_read *>(d->params.raw);
struct i40e_aqc_mac_address_read_data ard;
uint64_t mac = runner->get_mac_addr();
uint64_t mac = runner->GetMacAddr();
#ifdef DEBUG_ADMINQ
queue.log << " mac = " << mac << logger::endl;
#endif
......
sims/nic/i40e_bm/i40e_bm.cc
View file @ c7e904bf
......@@ -48,7 +48,7 @@ i40e_bm::i40e_bm()
i40e_bm::~i40e_bm() {
}
void i40e_bm::setup_intro(struct SimbricksProtoPcieDevIntro &di) {
void i40e_bm::SetupIntro(struct SimbricksProtoPcieDevIntro &di) {
di.bars[BAR_REGS].len = 4 * 1024 * 1024;
di.bars[BAR_REGS].flags = SIMBRICKS_PROTO_PCIE_BAR_64;
di.bars[BAR_IO].len = 32;
......@@ -72,7 +72,7 @@ void i40e_bm::setup_intro(struct SimbricksProtoPcieDevIntro &di) {
di.psi_msix_cap_offset = 0x70;
}
void i40e_bm::dma_complete(nicbm::DMAOp &op) {
void i40e_bm::DmaComplete(nicbm::DMAOp &op) {
dma_base &dma = dynamic_cast<dma_base &>(op);
#ifdef DEBUG_DEV
log << "dma_complete(" << &op << ")" << logger::endl;
......@@ -80,21 +80,21 @@ void i40e_bm::dma_complete(nicbm::DMAOp &op) {
dma.done();
}
void i40e_bm::eth_rx(uint8_t port, const void *data, size_t len) {
void i40e_bm::EthRx(uint8_t port, const void *data, size_t len) {
#ifdef DEBUG_DEV
log << "i40e: received packet len=" << len << logger::endl;
#endif
lanmgr.packet_received(data, len);
}
void i40e_bm::reg_read(uint8_t bar, uint64_t addr, void *dest, size_t len) {
void i40e_bm::RegRead(uint8_t bar, uint64_t addr, void *dest, size_t len) {
uint32_t *dest_p = reinterpret_cast<uint32_t *>(dest);
if (len == 4) {
dest_p[0] = reg_read32(bar, addr);
dest_p[0] = RegRead32(bar, addr);
} else if (len == 8) {
dest_p[0] = reg_read32(bar, addr);
dest_p[1] = reg_read32(bar, addr + 4);
dest_p[0] = RegRead32(bar, addr);
dest_p[1] = RegRead32(bar, addr + 4);
} else {
log << "currently we only support 4/8B reads (got " << len << ")"
<< logger::endl;
......@@ -102,7 +102,7 @@ void i40e_bm::reg_read(uint8_t bar, uint64_t addr, void *dest, size_t len) {
}
}
uint32_t i40e_bm::reg_read32(uint8_t bar, uint64_t addr) {
uint32_t i40e_bm::RegRead32(uint8_t bar, uint64_t addr) {
if (bar == BAR_REGS) {
return reg_mem_read32(addr);
} else if (bar == BAR_IO) {
......@@ -113,15 +113,15 @@ uint32_t i40e_bm::reg_read32(uint8_t bar, uint64_t addr) {
}
}
void i40e_bm::reg_write(uint8_t bar, uint64_t addr, const void *src,
void i40e_bm::RegWrite(uint8_t bar, uint64_t addr, const void *src,
size_t len) {
const uint32_t *src_p = reinterpret_cast<const uint32_t *>(src);
if (len == 4) {
reg_write32(bar, addr, src_p[0]);
RegWrite32(bar, addr, src_p[0]);
} else if (len == 8) {
reg_write32(bar, addr, src_p[0]);
reg_write32(bar, addr + 4, src_p[1]);
RegWrite32(bar, addr, src_p[0]);
RegWrite32(bar, addr + 4, src_p[1]);
} else {
log << "currently we only support 4/8B writes (got " << len << ")"
<< logger::endl;
......@@ -129,7 +129,7 @@ void i40e_bm::reg_write(uint8_t bar, uint64_t addr, const void *src,
}
}
void i40e_bm::reg_write32(uint8_t bar, uint64_t addr, uint32_t val) {
void i40e_bm::RegWrite32(uint8_t bar, uint64_t addr, uint32_t val) {
if (bar == BAR_REGS) {
reg_mem_write32(addr, val);
} else if (bar == BAR_IO) {
......@@ -246,7 +246,7 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr) {
break;
case I40E_GLVFGEN_TIMER:
val = runner->time_ps() / 1000000;
val = runner->TimePs() / 1000000;
break;
case I40E_PFINT_LNKLST0:
......@@ -651,7 +651,7 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val) {
}
}
void i40e_bm::timed_event(nicbm::TimedEvent &ev) {
void i40e_bm::Timed(nicbm::TimedEvent &ev) {
int_ev &iev = *((int_ev *)&ev);
#ifdef DEBUG_DEV
log << "timed_event: triggering interrupt (" << iev.vec << ")"
......@@ -659,17 +659,17 @@ void i40e_bm::timed_event(nicbm::TimedEvent &ev) {
#endif
iev.armed = false;
if (int_msix_en) {
runner->msix_issue(iev.vec);
if (int_msix_en_) {
runner->MsiXIssue(iev.vec);
} else if (iev.vec > 0) {
log << "timed_event: MSI-X disabled, but vec != 0" << logger::endl;
abort();
} else {
runner->msi_issue(0);
runner->MsiIssue(0);
}
}
void i40e_bm::signal_interrupt(uint16_t vec, uint8_t itr) {
void i40e_bm::SignalInterrupt(uint16_t vec, uint8_t itr) {
int_ev &iev = intevs[vec];
uint64_t mindelay;
......@@ -688,9 +688,9 @@ void i40e_bm::signal_interrupt(uint16_t vec, uint8_t itr) {
abort();
}
uint64_t curtime = runner->time_ps();
uint64_t curtime = runner->TimePs();
uint64_t newtime = curtime + mindelay;
if (iev.armed && iev.time <= newtime) {
if (iev.armed && iev.time_ <= newtime) {
// already armed and this is not scheduled sooner
#ifdef DEBUG_DEV
log << "signal_interrupt: vec " << vec << " already scheduled"
......@@ -699,18 +699,18 @@ void i40e_bm::signal_interrupt(uint16_t vec, uint8_t itr) {
return;
} else if (iev.armed) {
// need to reschedule
runner->event_cancel(iev);
runner->EventCancel(iev);
}
iev.armed = true;
iev.time = newtime;
iev.time_ = newtime;
#ifdef DEBUG_DEV
log << "signal_interrupt: scheduled vec " << vec << " for time=" << newtime
<< " (itr " << itr << ")" << logger::endl;
#endif
runner->event_schedule(iev);
runner->EventSchedule(iev);
}
void i40e_bm::reset(bool indicate_done) {
......@@ -729,10 +729,10 @@ void i40e_bm::reset(bool indicate_done) {
for (uint16_t i = 0; i < NUM_PFINTS; i++) {
intevs[i].vec = i;
if (intevs[i].armed) {
runner->event_cancel(intevs[i]);
runner->EventCancel(intevs[i]);
intevs[i].armed = false;
}
intevs[i].time = 0;
intevs[i].time_ = 0;
}
// add default hash key
......@@ -821,7 +821,7 @@ void shadow_ram::write(uint16_t addr, uint16_t val) {
int_ev::int_ev() {
armed = false;
time = 0;
time_ = 0;
}
} // namespace i40e
......@@ -831,5 +831,5 @@ using namespace i40e;
int main(int argc, char *argv[]) {
i40e_bm dev;
runner = new nicbm::Runner(dev);
return runner->runMain(argc, argv);
return runner->RunMain(argc, argv);
}
sims/nic/i40e_bm/i40e_bm.h
View file @ c7e904bf
......@@ -583,17 +583,17 @@ class i40e_bm : public nicbm::Runner::Device {
i40e_bm();
~i40e_bm();
virtual void setup_intro(struct SimbricksProtoPcieDevIntro &di);
virtual void reg_read(uint8_t bar, uint64_t addr, void *dest, size_t len);
virtual uint32_t reg_read32(uint8_t bar, uint64_t addr);
virtual void reg_write(uint8_t bar, uint64_t addr, const void *src,
size_t len);
virtual void reg_write32(uint8_t bar, uint64_t addr, uint32_t val);
virtual void dma_complete(nicbm::DMAOp &op);
virtual void eth_rx(uint8_t port, const void *data, size_t len);
virtual void timed_event(nicbm::TimedEvent &ev);
void signal_interrupt(uint16_t vector, uint8_t itr);
void SetupIntro(struct SimbricksProtoPcieDevIntro &di) override;
void RegRead(uint8_t bar, uint64_t addr, void *dest, size_t len) override;
virtual uint32_t RegRead32(uint8_t bar, uint64_t addr);
void RegWrite(uint8_t bar, uint64_t addr, const void *src, size_t len)
override;
virtual void RegWrite32(uint8_t bar, uint64_t addr, uint32_t val);
void DmaComplete(nicbm::DMAOp &op) override;
void EthRx(uint8_t port, const void *data, size_t len) override;
void Timed(nicbm::TimedEvent &ev) override;
virtual void SignalInterrupt(uint16_t vector, uint8_t itr);
protected:
logger log;
......
sims/nic/i40e_bm/i40e_hmc.cc
View file @ c7e904bf
......@@ -100,9 +100,9 @@ void host_mem_cache::reg_updated(uint64_t addr) {
}
void host_mem_cache::issue_mem_op(mem_op &op) {
uint64_t addr = op.dma_addr;
uint64_t addr = op.dma_addr_;
uint16_t seg_idx = addr >> 21;
uint16_t seg_idx_last = (addr + op.len - 1) >> 21;
uint16_t seg_idx_last = (addr + op.len_ - 1) >> 21;
uint32_t dir_off = addr & ((1 << 21) - 1);
struct segment *seg = &segs[seg_idx];
......@@ -121,7 +121,7 @@ void host_mem_cache::issue_mem_op(mem_op &op) {
if (seg_idx != seg_idx_last) {
std::cerr << "hmc issue_mem_op: operation crosses segs addr=" << addr
<< " len=" << op.len << std::endl;
<< " len=" << op.len_ << std::endl;
abort();
}
......@@ -131,11 +131,11 @@ void host_mem_cache::issue_mem_op(mem_op &op) {
}
op.failed = false;
op.dma_addr = seg->addr + dir_off;
op.dma_addr_ = seg->addr + dir_off;
#ifdef DEBUG_HMC
std::cerr << "hmc issue_mem_op: hmc_addr=" << addr
<< " dma_addr=" << op.dma_addr << " len=" << op.len << std::endl;
#endif
runner->issue_dma(op);
runner->IssueDma(op);
}
sims/nic/i40e_bm/i40e_lan.cc
View file @ c7e904bf
......@@ -167,13 +167,13 @@ void lan_queue_base::enable() {
enabling = true;
qctx_fetch *qf = new qctx_fetch(*this);
qf->write = false;
qf->dma_addr = ((fpm_basereg & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) >>
qf->write_ = false;
qf->dma_addr_ = ((fpm_basereg & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) >>
I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) *
512;
qf->dma_addr += ctx_size * idx;
qf->len = ctx_size;
qf->data = ctx;
qf->dma_addr_ += ctx_size * idx;
qf->len_ = ctx_size;
qf->data_ = ctx;
lanmgr.dev.hmc.issue_mem_op(*qf);
}
......@@ -233,7 +233,7 @@ void lan_queue_base::interrupt() {
uint8_t itr =
(qctl & I40E_QINT_TQCTL_ITR_INDX_MASK) >> I40E_QINT_TQCTL_ITR_INDX_SHIFT;
lanmgr.dev.signal_interrupt(msix_idx, itr);
lanmgr.dev.SignalInterrupt(msix_idx, itr);
}
lan_queue_base::qctx_fetch::qctx_fetch(lan_queue_base &lq_) : lq(lq_) {
......@@ -427,12 +427,12 @@ void lan_queue_tx::do_writeback(uint32_t first_idx, uint32_t first_pos,
} else {
// else we just need to write the index back
dma_hwb *dma = new dma_hwb(*this, first_pos, cnt, (first_idx + cnt) % len);
dma->dma_addr = hwb_addr;
dma->dma_addr_ = hwb_addr;
#ifdef DEBUG_LAN
log << " hwb=" << *((uint32_t *)dma->data) << logger::endl;
#endif
runner->issue_dma(*dma);
runner->IssueDma(*dma);
}
}
......@@ -593,7 +593,7 @@ bool lan_queue_tx::trigger_tx_packet() {
xsum_tcp(pktbuf + tcp_off, tso_len - tcp_off);
}
runner->eth_send(pktbuf, tso_len);
runner->EthSend(pktbuf, tso_len);
} else {
#ifdef DEBUG_LAN
log << " tso packet off=" << tso_off << " len=" << tso_len
......@@ -610,7 +610,7 @@ bool lan_queue_tx::trigger_tx_packet() {
xsum_tcpip_tso(pktbuf + maclen, iplen, l4len, tso_paylen);
runner->eth_send(pktbuf, tso_len);
runner->EthSend(pktbuf, tso_len);
tso_postupdate_header(pktbuf + maclen, iplen, l4len, tso_paylen);
......@@ -693,9 +693,9 @@ void lan_queue_tx::tx_desc_ctx::processed() {
lan_queue_tx::dma_hwb::dma_hwb(lan_queue_tx &queue_, uint32_t pos_,
uint32_t cnt_, uint32_t nh_)
: queue(queue_), pos(pos_), cnt(cnt_), next_head(nh_) {
data = &next_head;
len = 4;
write = true;
data_ = &next_head;
len_ = 4;
write_ = true;
}
lan_queue_tx::dma_hwb::~dma_hwb() {
......
sims/nic/i40e_bm/i40e_queues.cc
View file @ c7e904bf
......@@ -98,13 +98,13 @@ void queue_base::trigger_fetch() {
// prepare & issue dma
dma_fetch *dma = new dma_fetch(*this, desc_len * fetch_cnt);
dma->write = false;
dma->dma_addr = base + next_idx * desc_len;
dma->write_ = false;
dma->dma_addr_ = base + next_idx * desc_len;
dma->pos = first_pos;
#ifdef DEBUG_QUEUES
log << " dma = " << dma << logger::endl;
#endif
runner->issue_dma(*dma);
runner->IssueDma(*dma);
}
void queue_base::trigger_process() {
......@@ -219,18 +219,18 @@ void queue_base::interrupt() {
void queue_base::do_writeback(uint32_t first_idx, uint32_t first_pos,
uint32_t cnt) {
dma_wb *dma = new dma_wb(*this, desc_len * cnt);
dma->write = true;
dma->dma_addr = base + first_idx * desc_len;
dma->write_ = true;
dma->dma_addr_ = base + first_idx * desc_len;
dma->pos = first_pos;
uint8_t *buf = reinterpret_cast<uint8_t *>(dma->data);
uint8_t *buf = reinterpret_cast<uint8_t *>(dma->data_);
for (uint32_t i = 0; i < cnt; i++) {
desc_ctx &ctx = *desc_ctxs[(first_pos + i) % MAX_ACTIVE_DESCS];
assert(ctx.state == desc_ctx::DESC_WRITING_BACK);
memcpy(buf + i * desc_len, ctx.desc, desc_len);
}
runner->issue_dma(*dma);
runner->IssueDma(*dma);
}
void queue_base::writeback_done(uint32_t first_pos, uint32_t cnt) {
......@@ -327,15 +327,15 @@ void queue_base::desc_ctx::data_fetch(uint64_t addr, size_t data_len) {
new dma_data_fetch(*this, std::min(data_len, MAX_DMA_SIZE), data);
dma->part_offset = 0;
dma->total_len = data_len;
dma->write = false;
dma->dma_addr = addr;
dma->write_ = false;
dma->dma_addr_ = addr;
#ifdef DEBUG_QUEUES
queue.log << "fetching data idx=" << index << " addr=" << addr
<< " len=" << data_len << logger::endl;
queue.log << " dma = " << dma << " data=" << data << logger::endl;
#endif
runner->issue_dma(*dma);
runner->IssueDma(*dma);
}
void queue_base::desc_ctx::data_fetched(uint64_t addr, size_t len) {
......@@ -349,11 +349,11 @@ void queue_base::desc_ctx::data_write(uint64_t addr, size_t data_len,
<< logger::endl;
#endif
dma_data_wb *data_dma = new dma_data_wb(*this, data_len);
data_dma->write = true;
data_dma->dma_addr = addr;
memcpy(data_dma->data, buf, data_len);
data_dma->write_ = true;
data_dma->dma_addr_ = addr;
memcpy(data_dma->data_, buf, data_len);
runner->issue_dma(*data_dma);
runner->IssueDma(*data_dma);
}
void queue_base::desc_ctx::data_written(uint64_t addr, size_t len) {
......@@ -364,19 +364,19 @@ void queue_base::desc_ctx::data_written(uint64_t addr, size_t len) {
processed();
}
queue_base::dma_fetch::dma_fetch(queue_base &queue_, size_t len_)
queue_base::dma_fetch::dma_fetch(queue_base &queue_, size_t len)
: queue(queue_) {
data = new char[len_];
len = len_;
data_ = new char[len];
len_ = len;
}
queue_base::dma_fetch::~dma_fetch() {
delete[]((char *)data);
delete[]((char *)data_);
}
void queue_base::dma_fetch::done() {
uint8_t *buf = reinterpret_cast<uint8_t *>(data);
for (uint32_t i = 0; i < len / queue.desc_len; i++) {
uint8_t *buf = reinterpret_cast<uint8_t *>(data_);
for (uint32_t i = 0; i < len_ / queue.desc_len; i++) {
desc_ctx &ctx = *queue.desc_ctxs[(pos + i) % queue.MAX_ACTIVE_DESCS];
memcpy(ctx.desc, buf + queue.desc_len * i, queue.desc_len);
......@@ -390,60 +390,60 @@ void queue_base::dma_fetch::done() {
delete this;
}
queue_base::dma_data_fetch::dma_data_fetch(desc_ctx &ctx_, size_t len_,
queue_base::dma_data_fetch::dma_data_fetch(desc_ctx &ctx_, size_t len,
void *buffer)
: ctx(ctx_) {
data = buffer;
len = len_;
data_ = buffer;
len_ = len;
}
queue_base::dma_data_fetch::~dma_data_fetch() {
}
void queue_base::dma_data_fetch::done() {
part_offset += len;
dma_addr += len;
data = (uint8_t *)data + len;
part_offset += len_;
dma_addr_ += len_;
data_ = (uint8_t *)data_ + len_;
if (part_offset < total_len) {
#ifdef DEBUG_QUEUES
ctx.queue.log << " dma_fetch: next part of multi part dma" << logger::endl;
#endif
len = std::min(total_len - part_offset, MAX_DMA_SIZE);
runner->issue_dma(*this);
len_ = std::min(total_len - part_offset, MAX_DMA_SIZE);
runner->IssueDma(*this);
return;
}
ctx.data_fetched(dma_addr - part_offset, total_len);
ctx.data_fetched(dma_addr_ - part_offset, total_len);
ctx.queue.trigger();
delete this;
}
queue_base::dma_wb::dma_wb(queue_base &queue_, size_t len_) : queue(queue_) {
data = new char[len_];
len = len_;
queue_base::dma_wb::dma_wb(queue_base &queue_, size_t len) : queue(queue_) {
data_ = new char[len];
len_ = len;
}
queue_base::dma_wb::~dma_wb() {
delete[]((char *)data);
delete[]((char *)data_);
}
void queue_base::dma_wb::done() {
queue.writeback_done(pos, len / queue.desc_len);
queue.writeback_done(pos, len_ / queue.desc_len);
queue.trigger();
delete this;
}
queue_base::dma_data_wb::dma_data_wb(desc_ctx &ctx_, size_t len_) : ctx(ctx_) {
data = new char[len_];
len = len_;
queue_base::dma_data_wb::dma_data_wb(desc_ctx &ctx_, size_t len) : ctx(ctx_) {
data_ = new char[len];
len_ = len;
}
queue_base::dma_data_wb::~dma_data_wb() {
delete[]((char *)data);
delete[]((char *)data_);
}
void queue_base::dma_data_wb::done() {
ctx.data_written(dma_addr, len);
ctx.data_written(dma_addr_, len_);
ctx.queue.trigger();
delete this;
}
sims/nic/i40e_bm/logger.cc
View file @ c7e904bf
......@@ -36,7 +36,7 @@ logger::logger(const std::string &label_) : label(label_) {
logger &logger::operator<<(char c) {
if (c == endl) {
std::cerr << runner->time_ps() << " " << label << ": " << ss.str()
std::cerr << runner->TimePs() << " " << label << ": " << ss.str()
<< std::endl;
ss.str(std::string());
ss << std::hex;
......
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