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Commit c15f2eab authored by Antoine Kaufmann's avatar Antoine Kaufmann
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sims/net/menshen: add

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sims/net/menshen/rtl/action/crossbar.v 0 → 100644
View file @ c15f2eab
`timescale 1ns / 1ps
module crossbar #(
parameter STAGE_ID = 0,
parameter PHV_LEN = 48*8+32*8+16*8+256,
parameter ACT_LEN = 25,
parameter width_2B = 16,
parameter width_4B = 32,
parameter width_6B = 48
)
(
input clk,
input rst_n,
//input from PHV
input [PHV_LEN-1:0] phv_in,
input phv_in_valid,
//input from action
input [ACT_LEN*25-1:0] action_in,
input action_in_valid,
output reg ready_out,
//output to the ALU
output reg alu_in_valid,
output reg [width_6B*8-1:0] alu_in_6B_1,
output reg [width_6B*8-1:0] alu_in_6B_2,
output reg [width_4B*8-1:0] alu_in_4B_1,
output reg [width_4B*8-1:0] alu_in_4B_2,
output reg [width_4B*8-1:0] alu_in_4B_3,
output reg [width_2B*8-1:0] alu_in_2B_1,
output reg [width_2B*8-1:0] alu_in_2B_2,
output reg [255:0] phv_remain_data,
//I have to delay action_in for ALUs for 1 cycle
output reg [ACT_LEN*25-1:0] action_out,
output reg action_valid_out,
input ready_in
);
/********intermediate variables declared here********/
integer i;
wire [width_6B-1:0] cont_6B [0:7];
wire [width_4B-1:0] cont_4B [0:7];
wire [width_2B-1:0] cont_2B [0:7];
wire [ACT_LEN-1:0] sub_action [24:0];
/********intermediate variables declared here********/
assign cont_6B[7] = phv_in[PHV_LEN-1 -: width_6B];
assign cont_6B[6] = phv_in[PHV_LEN-1- width_6B -: width_6B];
assign cont_6B[5] = phv_in[PHV_LEN-1-2*width_6B -: width_6B];
assign cont_6B[4] = phv_in[PHV_LEN-1-3*width_6B -: width_6B];
assign cont_6B[3] = phv_in[PHV_LEN-1-4*width_6B -: width_6B];
assign cont_6B[2] = phv_in[PHV_LEN-1-5*width_6B -: width_6B];
assign cont_6B[1] = phv_in[PHV_LEN-1-6*width_6B -: width_6B];
assign cont_6B[0] = phv_in[PHV_LEN-1-7*width_6B -: width_6B];
assign cont_4B[7] = phv_in[PHV_LEN-1-8*width_6B -: width_4B];
assign cont_4B[6] = phv_in[PHV_LEN-1-8*width_6B- width_4B -: width_4B];
assign cont_4B[5] = phv_in[PHV_LEN-1-8*width_6B-2*width_4B -: width_4B];
assign cont_4B[4] = phv_in[PHV_LEN-1-8*width_6B-3*width_4B -: width_4B];
assign cont_4B[3] = phv_in[PHV_LEN-1-8*width_6B-4*width_4B -: width_4B];
assign cont_4B[2] = phv_in[PHV_LEN-1-8*width_6B-5*width_4B -: width_4B];
assign cont_4B[1] = phv_in[PHV_LEN-1-8*width_6B-6*width_4B -: width_4B];
assign cont_4B[0] = phv_in[PHV_LEN-1-8*width_6B-7*width_4B -: width_4B];
assign cont_2B[7] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B -: width_2B];
assign cont_2B[6] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B- width_2B -: width_2B];
assign cont_2B[5] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B-2*width_2B -: width_2B];
assign cont_2B[4] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B-3*width_2B -: width_2B];
assign cont_2B[3] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B-4*width_2B -: width_2B];
assign cont_2B[2] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B-5*width_2B -: width_2B];
assign cont_2B[1] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B-6*width_2B -: width_2B];
assign cont_2B[0] = phv_in[PHV_LEN-1-8*width_6B-8*width_4B-7*width_2B -: width_2B];
// Tao: get action for each PHV container
assign sub_action[24] = action_in[ACT_LEN*25-1-:ACT_LEN]; // 1st action
assign sub_action[23] = action_in[ACT_LEN*25-1 - ACT_LEN-:ACT_LEN]; // 2nd action
assign sub_action[22] = action_in[ACT_LEN*25-1 -2*ACT_LEN-:ACT_LEN]; // 3rd action
assign sub_action[21] = action_in[ACT_LEN*25-1 -3*ACT_LEN-:ACT_LEN];
assign sub_action[20] = action_in[ACT_LEN*25-1 -4*ACT_LEN-:ACT_LEN];
assign sub_action[19] = action_in[ACT_LEN*25-1 -5*ACT_LEN-:ACT_LEN];
assign sub_action[18] = action_in[ACT_LEN*25-1 -6*ACT_LEN-:ACT_LEN];
assign sub_action[17] = action_in[ACT_LEN*25-1 -7*ACT_LEN-:ACT_LEN];
assign sub_action[16] = action_in[ACT_LEN*25-1 -8*ACT_LEN-:ACT_LEN];
assign sub_action[15] = action_in[ACT_LEN*25-1 -9*ACT_LEN-:ACT_LEN];
assign sub_action[14] = action_in[ACT_LEN*25-1 -10*ACT_LEN-:ACT_LEN];
assign sub_action[13] = action_in[ACT_LEN*25-1 -11*ACT_LEN-:ACT_LEN];
assign sub_action[12] = action_in[ACT_LEN*25-1 -12*ACT_LEN-:ACT_LEN];
assign sub_action[11] = action_in[ACT_LEN*25-1 -13*ACT_LEN-:ACT_LEN];
assign sub_action[10] = action_in[ACT_LEN*25-1 -14*ACT_LEN-:ACT_LEN];
assign sub_action[9] = action_in[ACT_LEN*25-1 -15*ACT_LEN-:ACT_LEN];
assign sub_action[8] = action_in[ACT_LEN*25-1 -16*ACT_LEN-:ACT_LEN];
assign sub_action[7] = action_in[ACT_LEN*25-1 -17*ACT_LEN-:ACT_LEN];
assign sub_action[6] = action_in[ACT_LEN*25-1 -18*ACT_LEN-:ACT_LEN];
assign sub_action[5] = action_in[ACT_LEN*25-1 -19*ACT_LEN-:ACT_LEN];
assign sub_action[4] = action_in[ACT_LEN*25-1 -20*ACT_LEN-:ACT_LEN];
assign sub_action[3] = action_in[ACT_LEN*25-1 -21*ACT_LEN-:ACT_LEN];
assign sub_action[2] = action_in[ACT_LEN*25-1 -22*ACT_LEN-:ACT_LEN];
assign sub_action[1] = action_in[ACT_LEN*25-1 -23*ACT_LEN-:ACT_LEN];
assign sub_action[0] = action_in[ACT_LEN*25-1 -24*ACT_LEN-:ACT_LEN];
//assign inputs for ALUs
always @(posedge clk) begin
action_out <= action_in;
action_valid_out <= action_in_valid;
end
localparam IDLE = 0,
PROCESS = 1,
HALT = 2;
reg [2:0] state;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
// phv_reg <= 1124'b0;
// action_full_reg <= 625'b0;
// phv_valid_reg <= 1'b0;
// action_valid_reg <= 1'b0;
//reset outputs
alu_in_valid <= 1'b0;
phv_remain_data <= 256'b0;
//reset all the outputs
alu_in_6B_1 <= 384'b0;
alu_in_6B_2 <= 384'b0;
alu_in_4B_1 <= 256'b0;
alu_in_4B_2 <= 256'b0;
alu_in_4B_3 <= 256'b0;
alu_in_2B_1 <= 128'b0;
alu_in_2B_2 <= 128'b0;
state <= IDLE;
ready_out <= 1;
end
else begin
case (state)
IDLE: begin
if(phv_in_valid == 1'b1) begin
if (ready_in) begin
alu_in_valid <= 1'b1;
end
else begin
ready_out <= 0;
state <= HALT;
end
//assign values one by one (of course need to consider act format)
for(i=7; i>=0; i=i-1) begin
case(sub_action[16+i+1][24:21])
//be noted that 2 ops need to be the same width
4'b0001, 4'b0010: begin
alu_in_6B_1[(i+1)*width_6B-1 -: width_6B] <= cont_6B[sub_action[16+i+1][18:16]];
alu_in_6B_2[(i+1)*width_6B-1 -: width_6B] <= cont_6B[sub_action[16+i+1][13:11]];
end
//extracted from action field (imm)
4'b1001, 4'b1010: begin
alu_in_6B_1[(i+1)*width_6B-1 -: width_6B] <= cont_6B[sub_action[16+i+1][18:16]];
alu_in_6B_2[(i+1)*width_6B-1 -: width_6B] <= {32'b0,sub_action[16+i+1][15:0]};
end
// set operation, operand A set to 0, operand B set to imm
4'b1110: begin
alu_in_6B_1[(i+1)*width_6B-1 -: width_6B] <= 48'b0;
alu_in_6B_2[(i+1)*width_6B-1 -: width_6B] <= {32'b0,sub_action[16+i+1][15:0]};
end
//if there is no action to take, output the original value
default: begin
//alu_1 should be set to the phv value
alu_in_6B_1[(i+1)*width_6B-1 -: width_6B] <= cont_6B[i];
alu_in_6B_2[(i+1)*width_6B-1 -: width_6B] <= 48'b0;
end
endcase
end
//4B is a bit of differernt from 2B and 6B
for(i=7; i>=0; i=i-1) begin
alu_in_4B_3[(i+1)*width_4B-1 -: width_4B] <= cont_4B[i];
casez(sub_action[8+i+1][24:21])
//be noted that 2 ops need to be the same width
4'b0001, 4'b0010: begin
alu_in_4B_1[(i+1)*width_4B-1 -: width_4B] <= cont_4B[sub_action[8+i+1][18:16]];
alu_in_4B_2[(i+1)*width_4B-1 -: width_4B] <= cont_4B[sub_action[8+i+1][13:11]];
end
4'b1001, 4'b1010: begin
alu_in_4B_1[(i+1)*width_4B-1 -: width_4B] <= cont_4B[sub_action[8+i+1][18:16]];
alu_in_4B_2[(i+1)*width_4B-1 -: width_4B] <= {16'b0,sub_action[8+i+1][15:0]};
end
// set operation, operand A set to 0, operand B set to imm
4'b1110: begin
alu_in_4B_1[(i+1)*width_4B-1 -: width_4B] <= 32'b0;
alu_in_4B_2[(i+1)*width_4B-1 -: width_4B] <= {16'b0,sub_action[8+i+1][15:0]};
end
//loadd put here
4'b1011, 4'b1000, 4'b0111: begin
alu_in_4B_1[(i+1)*width_4B-1 -: width_4B] <= cont_4B[sub_action[8+i+1][18:16]];
//alu_in_4B_2[(i+1)*width_4B-1 -: width_4B] <= {16'b0,sub_action[8+i+1][15:0]};
alu_in_4B_2[(i+1)*width_4B-1 -: width_4B] <= cont_4B[sub_action[8+i+1][13:11]];
end
//if there is no action to take, output the original value
default: begin
//alu_1 should be set to the phv value
alu_in_4B_1[(i+1)*width_4B-1 -: width_4B] <= cont_4B[i];
alu_in_4B_2[(i+1)*width_4B-1 -: width_4B] <= 32'b0;
end
endcase
end
for(i=7; i>=0; i=i-1) begin
casez(sub_action[i+1][24:21])
//be noted that 2 ops need to be the same width
4'b0001, 4'b0010: begin
alu_in_2B_1[(i+1)*width_2B-1 -: width_2B] <= cont_2B[sub_action[i+1][18:16]];
alu_in_2B_2[(i+1)*width_2B-1 -: width_2B] <= cont_2B[sub_action[i+1][13:11]];
end
4'b1001, 4'b1010: begin
alu_in_2B_1[(i+1)*width_2B-1 -: width_2B] <= cont_2B[sub_action[i+1][18:16]];
alu_in_2B_2[(i+1)*width_2B-1 -: width_2B] <= sub_action[i+1][15:0];
end
// set operation, operand A set to 0, operand B set to imm
4'b1110: begin
alu_in_2B_1[(i+1)*width_2B-1 -: width_2B] <= 16'b0;
alu_in_2B_2[(i+1)*width_2B-1 -: width_2B] <= sub_action[i+1][15:0];
end
//if there is no action to take, output the original value
default: begin
//alu_1 should be set to the phv value
alu_in_2B_1[(i+1)*width_2B-1 -: width_2B] <= cont_2B[i];
alu_in_2B_2[(i+1)*width_2B-1 -: width_2B] <= 16'b0;
end
endcase
end
//the left is metadata & conditional ins, no need to modify
phv_remain_data <= phv_in[255:0];
end
else begin
alu_in_valid <= 1'b0;
end
end
HALT: begin
if (ready_in) begin
alu_in_valid <= 1'b1;
state <= IDLE;
ready_out <= 1'b1;
end
end
endcase
end
end
endmodule
sims/net/menshen/rtl/depar_do_deparsing.v 0 → 100644
View file @ c15f2eab
`timescale 1ns / 1ps
`define SUB_DEPARSE_1P(idx) \
if(parse_action[idx][0]) begin \
case(sub_depar_val_out_type_d1[idx]) \
2'b01: pkts_tdata_stored_1p_next[parse_action_ind_10b[idx]<<3 +: 16] = sub_depar_val_out_swapped[idx][32+:16]; \
2'b10: pkts_tdata_stored_1p_next[parse_action_ind_10b[idx]<<3 +: 32] = sub_depar_val_out_swapped[idx][16+:32]; \
2'b11: pkts_tdata_stored_1p_next[parse_action_ind_10b[idx]<<3 +: 48] = sub_depar_val_out_swapped[idx][0+:48]; \
endcase \
end \
`define SUB_DEPARSE_2P(idx) \
if(parse_action[idx][0]) begin \
case(sub_depar_val_out_type_d1[idx]) \
2'b01: pkts_tdata_stored_2p_next[parse_action_ind_10b[idx]<<3 +: 16] = sub_depar_val_out_swapped[idx][32+:16]; \
2'b10: pkts_tdata_stored_2p_next[parse_action_ind_10b[idx]<<3 +: 32] = sub_depar_val_out_swapped[idx][16+:32]; \
2'b11: pkts_tdata_stored_2p_next[parse_action_ind_10b[idx]<<3 +: 48] = sub_depar_val_out_swapped[idx][0+:48]; \
endcase \
end \
`define SWAP_BYTE_ORDER2(idx) \
assign sub_depar_val_out_swapped[idx] = { sub_depar_val_out_d1[idx][0+:8], \
sub_depar_val_out_d1[idx][8+:8], \
sub_depar_val_out_d1[idx][16+:8], \
sub_depar_val_out_d1[idx][24+:8], \
sub_depar_val_out_d1[idx][32+:8], \
sub_depar_val_out_d1[idx][40+:8]}; \
module depar_do_deparsing #(
parameter C_AXIS_DATA_WIDTH = 512,
parameter C_AXIS_TUSER_WIDTH = 128,
parameter C_PKT_VEC_WIDTH = (6+4+2)*8*8+256,
parameter DEPARSER_MOD_ID = 3'b101,
parameter C_VLANID_WIDTH = 12
)
(
input clk,
input aresetn,
// phv
input [C_PKT_VEC_WIDTH-1:0] phv_fifo_out,
input phv_fifo_empty,
output reg phv_fifo_rd_en,
//
input [C_VLANID_WIDTH-1:0] vlan_id,
input vlan_fifo_empty,
output reg vlan_fifo_rd_en,
//
input [C_AXIS_DATA_WIDTH-1:0] fst_half_fifo_tdata,
input [C_AXIS_TUSER_WIDTH-1:0] fst_half_fifo_tuser,
input [C_AXIS_DATA_WIDTH/8-1:0] fst_half_fifo_tkeep,
input fst_half_fifo_tlast,
input fst_half_fifo_empty,
output reg fst_half_fifo_rd_en,
//
input [C_AXIS_DATA_WIDTH-1:0] snd_half_fifo_tdata,
input [C_AXIS_TUSER_WIDTH-1:0] snd_half_fifo_tuser,
input [C_AXIS_DATA_WIDTH/8-1:0] snd_half_fifo_tkeep,
input snd_half_fifo_tlast,
input snd_half_fifo_empty,
output reg snd_half_fifo_rd_en,
//
input [C_AXIS_DATA_WIDTH-1:0] pkt_fifo_tdata,
input [C_AXIS_TUSER_WIDTH-1:0] pkt_fifo_tuser,
input [C_AXIS_DATA_WIDTH/8-1:0] pkt_fifo_tkeep,
input pkt_fifo_tlast,
input pkt_fifo_empty,
output reg pkt_fifo_rd_en,
// output
output reg [C_AXIS_DATA_WIDTH-1:0] depar_out_tdata,
output reg [C_AXIS_DATA_WIDTH/8-1:0] depar_out_tkeep,
output reg [C_AXIS_TUSER_WIDTH-1:0] depar_out_tuser,
output reg depar_out_tvalid,
output reg depar_out_tlast,
input depar_out_tready,
// control path
input [C_AXIS_DATA_WIDTH-1:0] ctrl_s_axis_tdata,
input [C_AXIS_TUSER_WIDTH-1:0] ctrl_s_axis_tuser,
input [C_AXIS_DATA_WIDTH/8-1:0] ctrl_s_axis_tkeep,
input ctrl_s_axis_tvalid,
input ctrl_s_axis_tlast
);
integer i;
reg [C_AXIS_DATA_WIDTH-1:0] depar_out_tdata_next;
reg [C_AXIS_DATA_WIDTH/8-1:0] depar_out_tkeep_next;
reg [C_AXIS_TUSER_WIDTH-1:0] depar_out_tuser_next;
reg depar_out_tlast_next;
reg depar_out_tvalid_next;
wire [159:0] bram_out;
wire [6:0] parse_action_ind [0:9];
wire [9:0] parse_action_ind_10b [0:9];
wire [15:0] parse_action [0:9]; // we have 10 parse action
assign parse_action[9] = bram_out[0+:16];
assign parse_action[8] = bram_out[16+:16];
assign parse_action[7] = bram_out[32+:16];
assign parse_action[6] = bram_out[48+:16];
assign parse_action[5] = bram_out[64+:16];
assign parse_action[4] = bram_out[80+:16];
assign parse_action[3] = bram_out[96+:16];
assign parse_action[2] = bram_out[112+:16];
assign parse_action[1] = bram_out[128+:16];
assign parse_action[0] = bram_out[144+:16];
assign parse_action_ind[0] = parse_action[0][12:6];
assign parse_action_ind[1] = parse_action[1][12:6];
assign parse_action_ind[2] = parse_action[2][12:6];
assign parse_action_ind[3] = parse_action[3][12:6];
assign parse_action_ind[4] = parse_action[4][12:6];
assign parse_action_ind[5] = parse_action[5][12:6];
assign parse_action_ind[6] = parse_action[6][12:6];
assign parse_action_ind[7] = parse_action[7][12:6];
assign parse_action_ind[8] = parse_action[8][12:6];
assign parse_action_ind[9] = parse_action[9][12:6];
assign parse_action_ind_10b[0] = parse_action_ind[0];
assign parse_action_ind_10b[1] = parse_action_ind[1];
assign parse_action_ind_10b[2] = parse_action_ind[2];
assign parse_action_ind_10b[3] = parse_action_ind[3];
assign parse_action_ind_10b[4] = parse_action_ind[4];
assign parse_action_ind_10b[5] = parse_action_ind[5];
assign parse_action_ind_10b[6] = parse_action_ind[6];
assign parse_action_ind_10b[7] = parse_action_ind[7];
assign parse_action_ind_10b[8] = parse_action_ind[8];
assign parse_action_ind_10b[9] = parse_action_ind[9];
reg [9:0] sub_depar_act_valid;
wire [47:0] sub_depar_val_out_swapped [0:9];
wire [47:0] sub_depar_val_out [0:9];
wire [1:0] sub_depar_val_out_type [0:9];
wire [9:0] sub_depar_val_out_valid;
reg [47:0] sub_depar_val_out_d1 [0:9];
reg [1:0] sub_depar_val_out_type_d1 [0:9];
reg [9:0] sub_depar_val_out_valid_d1;
always @(posedge clk) begin
if (~aresetn) begin
for (i=0; i<10; i=i+1) begin
sub_depar_val_out_d1[i] <= 0;
sub_depar_val_out_type_d1[i] <= 0;
end
sub_depar_val_out_valid_d1 <= 0;
end
else begin
for (i=0; i<10; i=i+1) begin
sub_depar_val_out_d1[i] <= sub_depar_val_out[i];
sub_depar_val_out_type_d1[i] <= sub_depar_val_out_type[i];
end
sub_depar_val_out_valid_d1 <= sub_depar_val_out_valid;
end
end
`SWAP_BYTE_ORDER2(0)
`SWAP_BYTE_ORDER2(1)
`SWAP_BYTE_ORDER2(2)
`SWAP_BYTE_ORDER2(3)
`SWAP_BYTE_ORDER2(4)
`SWAP_BYTE_ORDER2(5)
`SWAP_BYTE_ORDER2(6)
`SWAP_BYTE_ORDER2(7)
`SWAP_BYTE_ORDER2(8)
`SWAP_BYTE_ORDER2(9)
wire discard_signal;
assign discard_signal = phv_fifo_out[128];
localparam IDLE=0,
WAIT_1CYCLE_RAM=1,
START_SUB_DEPARSE=2,
FINISH_SUB_DEPARSER_0=3,
FINISH_SUB_DEPARSER_1=4,
FINISH_SUB_DEPARSER_2=5,
FLUSH_PKT_0=6,
FLUSH_PKT_1=7,
FLUSH_PKT_2=8,
FLUSH_PKT_3=9,
FLUSH_PKT=10,
DROP_PKT=11,
DROP_PKT_REMAINING=12,
EMPTY_1=13,
EMPTY_2=14;
reg [C_AXIS_DATA_WIDTH-1:0] pkts_tdata_stored_1p, pkts_tdata_stored_2p;
reg [C_AXIS_TUSER_WIDTH-1:0] pkts_tuser_stored_1p, pkts_tuser_stored_2p;
reg [(C_AXIS_DATA_WIDTH/8)-1:0] pkts_tkeep_stored_1p, pkts_tkeep_stored_2p;
reg pkts_tlast_stored_1p, pkts_tlast_stored_2p;
reg [C_AXIS_DATA_WIDTH-1:0] pkts_tdata_stored_1p_next, pkts_tdata_stored_2p_next;
reg [C_AXIS_TUSER_WIDTH-1:0] pkts_tuser_stored_1p_next, pkts_tuser_stored_2p_next;
reg [(C_AXIS_DATA_WIDTH/8)-1:0] pkts_tkeep_stored_1p_next, pkts_tkeep_stored_2p_next;
reg pkts_tlast_stored_1p_next, pkts_tlast_stored_2p_next;
reg [4:0] state, state_next;
always @(*) begin
phv_fifo_rd_en = 0;
vlan_fifo_rd_en = 0;
fst_half_fifo_rd_en = 0;
snd_half_fifo_rd_en = 0;
pkt_fifo_rd_en = 0;
// output
depar_out_tdata_next = depar_out_tdata;
depar_out_tuser_next = depar_out_tuser;
depar_out_tkeep_next = depar_out_tkeep;
depar_out_tlast_next = depar_out_tlast;
depar_out_tvalid_next = 0;
sub_depar_act_valid = 10'b0;
state_next = state;
//
pkts_tdata_stored_1p_next = pkts_tdata_stored_1p;
pkts_tuser_stored_1p_next = pkts_tuser_stored_1p;
pkts_tkeep_stored_1p_next = pkts_tkeep_stored_1p;
pkts_tlast_stored_1p_next = pkts_tlast_stored_1p;
//
pkts_tdata_stored_2p_next = pkts_tdata_stored_2p;
pkts_tuser_stored_2p_next = pkts_tuser_stored_2p;
pkts_tkeep_stored_2p_next = pkts_tkeep_stored_2p;
pkts_tlast_stored_2p_next = pkts_tlast_stored_2p;
case (state)
IDLE: begin
if (!vlan_fifo_empty) begin
state_next = WAIT_1CYCLE_RAM;
end
end
WAIT_1CYCLE_RAM: begin
state_next = START_SUB_DEPARSE;
end
START_SUB_DEPARSE: begin
if (!fst_half_fifo_empty
&& !snd_half_fifo_empty
&& !phv_fifo_empty) begin
if (discard_signal == 1) begin
state_next = DROP_PKT;
phv_fifo_rd_en = 1;
end
else begin
sub_depar_act_valid = 10'b1111111111;
state_next = EMPTY_2;
pkts_tdata_stored_1p_next = fst_half_fifo_tdata;
pkts_tuser_stored_1p_next = phv_fifo_out[0+:128];
pkts_tkeep_stored_1p_next = fst_half_fifo_tkeep;
pkts_tlast_stored_1p_next = fst_half_fifo_tlast;
//
pkts_tdata_stored_2p_next = snd_half_fifo_tdata;
pkts_tuser_stored_2p_next = snd_half_fifo_tuser;
pkts_tkeep_stored_2p_next = snd_half_fifo_tkeep;
pkts_tlast_stored_2p_next = snd_half_fifo_tlast;
end
end
end
EMPTY_1: begin
// sub_depar_act_valid = 10'b1111111111;
state_next = EMPTY_2;
end
EMPTY_2: begin
state_next = FINISH_SUB_DEPARSER_0;
end
FINISH_SUB_DEPARSER_0: begin
`SUB_DEPARSE_1P(0)
`SUB_DEPARSE_1P(1)
`SUB_DEPARSE_2P(5)
state_next = FINISH_SUB_DEPARSER_1;
end
FINISH_SUB_DEPARSER_1: begin
`SUB_DEPARSE_1P(2)
`SUB_DEPARSE_2P(6)
`SUB_DEPARSE_2P(7)
state_next = FINISH_SUB_DEPARSER_2;
end
FINISH_SUB_DEPARSER_2: begin
`SUB_DEPARSE_1P(3)
`SUB_DEPARSE_1P(4)
`SUB_DEPARSE_2P(8)
`SUB_DEPARSE_2P(9)
state_next = FLUSH_PKT_0;
end
FLUSH_PKT_0: begin
phv_fifo_rd_en = 1;
vlan_fifo_rd_en = 1;
fst_half_fifo_rd_en = 1;
snd_half_fifo_rd_en = 1;
depar_out_tdata_next = pkts_tdata_stored_1p;
depar_out_tuser_next = pkts_tuser_stored_1p;
depar_out_tkeep_next = pkts_tkeep_stored_1p;
depar_out_tlast_next = pkts_tlast_stored_1p;
if (depar_out_tready) begin
depar_out_tvalid_next = 1;
if (pkts_tlast_stored_1p) begin
state_next = IDLE;
end
else begin
state_next = FLUSH_PKT_1;
end
end
end
FLUSH_PKT_1: begin
depar_out_tdata_next = pkts_tdata_stored_2p;
depar_out_tuser_next = pkts_tuser_stored_2p;
depar_out_tkeep_next = pkts_tkeep_stored_2p;
depar_out_tlast_next = pkts_tlast_stored_2p;
if (depar_out_tready) begin
depar_out_tvalid_next = 1;
if (pkts_tlast_stored_2p) begin
state_next = IDLE;
end
else begin
state_next = FLUSH_PKT;
end
end
end
FLUSH_PKT: begin
if (!pkt_fifo_empty) begin
depar_out_tdata_next = pkt_fifo_tdata;
depar_out_tuser_next = pkt_fifo_tuser;
depar_out_tkeep_next = pkt_fifo_tkeep;
depar_out_tlast_next = pkt_fifo_tlast;
if (depar_out_tready) begin
pkt_fifo_rd_en = 1;
depar_out_tvalid_next = 1;
if (pkt_fifo_tlast) begin
state_next = IDLE;
end
end
end
end
DROP_PKT: begin
if (fst_half_fifo_tlast==1
|| snd_half_fifo_tlast==1) begin
fst_half_fifo_rd_en = 1;
snd_half_fifo_rd_en = 1;
vlan_fifo_rd_en = 1;
state_next = IDLE;
end
else begin
fst_half_fifo_rd_en = 1;
snd_half_fifo_rd_en = 1;
vlan_fifo_rd_en = 1;
state_next = DROP_PKT_REMAINING;
end
end
DROP_PKT_REMAINING: begin
pkt_fifo_rd_en = 1;
if (pkt_fifo_tlast) begin
state_next = IDLE;
end
end
endcase
end
always @(posedge clk) begin
if (~aresetn) begin
state <= IDLE;
//
pkts_tdata_stored_1p <= 0;
pkts_tuser_stored_1p <= 0;
pkts_tkeep_stored_1p <= 0;
pkts_tlast_stored_1p <= 0;
//
pkts_tdata_stored_2p <= 0;
pkts_tuser_stored_2p <= 0;
pkts_tkeep_stored_2p <= 0;
pkts_tlast_stored_2p <= 0;
//
depar_out_tdata <= 0;
depar_out_tkeep <= 0;
depar_out_tuser <= 0;
depar_out_tlast <= 0;
depar_out_tvalid <= 0;
end
else begin
state <= state_next;
//
pkts_tdata_stored_1p <= pkts_tdata_stored_1p_next;
pkts_tuser_stored_1p <= pkts_tuser_stored_1p_next;
pkts_tkeep_stored_1p <= pkts_tkeep_stored_1p_next;
pkts_tlast_stored_1p <= pkts_tlast_stored_1p_next;
//
pkts_tdata_stored_2p <= pkts_tdata_stored_2p_next;
pkts_tuser_stored_2p <= pkts_tuser_stored_2p_next;
pkts_tkeep_stored_2p <= pkts_tkeep_stored_2p_next;
pkts_tlast_stored_2p <= pkts_tlast_stored_2p_next;
//
depar_out_tdata <= depar_out_tdata_next;
depar_out_tkeep <= depar_out_tkeep_next;
depar_out_tuser <= depar_out_tuser_next;
depar_out_tlast <= depar_out_tlast_next;
depar_out_tvalid <= depar_out_tvalid_next;
end
end
//===================== sub deparser
generate
genvar index;
for (index=0; index<10; index=index+1)
begin: sub_op
sub_deparser #(
.C_PKT_VEC_WIDTH(),
.C_PARSE_ACT_LEN()
)
sub_deparser (
.clk (clk),
.aresetn (aresetn),
.parse_act_valid (sub_depar_act_valid[index]),
.parse_act (parse_action[index][5:0]),
.phv_in (phv_fifo_out),
.val_out_valid (sub_depar_val_out_valid[index]),
.val_out (sub_depar_val_out[index]),
.val_out_type (sub_depar_val_out_type[index])
);
end
endgenerate
/*================Control Path====================*/
wire [7:0] mod_id; //module ID
wire [15:0] control_flag; //dst udp port num
reg [7:0] c_index; //table index(addr)
reg c_wr_en; //enable table write(wen)
reg [159:0] entry_reg;
reg [2:0] c_state;
localparam IDLE_C = 1,
WRITE_C = 2,
SU_WRITE_C = 3;
assign mod_id = ctrl_s_axis_tdata[368+:8];
assign control_flag = ctrl_s_axis_tdata[335:320];
//LE to BE switching
wire[C_AXIS_DATA_WIDTH-1:0] ctrl_s_axis_tdata_swapped;
assign ctrl_s_axis_tdata_swapped = {ctrl_s_axis_tdata[0+:8],
ctrl_s_axis_tdata[8+:8],
ctrl_s_axis_tdata[16+:8],
ctrl_s_axis_tdata[24+:8],
ctrl_s_axis_tdata[32+:8],
ctrl_s_axis_tdata[40+:8],
ctrl_s_axis_tdata[48+:8],
ctrl_s_axis_tdata[56+:8],
ctrl_s_axis_tdata[64+:8],
ctrl_s_axis_tdata[72+:8],
ctrl_s_axis_tdata[80+:8],
ctrl_s_axis_tdata[88+:8],
ctrl_s_axis_tdata[96+:8],
ctrl_s_axis_tdata[104+:8],
ctrl_s_axis_tdata[112+:8],
ctrl_s_axis_tdata[120+:8],
ctrl_s_axis_tdata[128+:8],
ctrl_s_axis_tdata[136+:8],
ctrl_s_axis_tdata[144+:8],
ctrl_s_axis_tdata[152+:8],
ctrl_s_axis_tdata[160+:8],
ctrl_s_axis_tdata[168+:8],
ctrl_s_axis_tdata[176+:8],
ctrl_s_axis_tdata[184+:8],
ctrl_s_axis_tdata[192+:8],
ctrl_s_axis_tdata[200+:8],
ctrl_s_axis_tdata[208+:8],
ctrl_s_axis_tdata[216+:8],
ctrl_s_axis_tdata[224+:8],
ctrl_s_axis_tdata[232+:8],
ctrl_s_axis_tdata[240+:8],
ctrl_s_axis_tdata[248+:8],
ctrl_s_axis_tdata[256+:8],
ctrl_s_axis_tdata[264+:8],
ctrl_s_axis_tdata[272+:8],
ctrl_s_axis_tdata[280+:8],
ctrl_s_axis_tdata[288+:8],
ctrl_s_axis_tdata[296+:8],
ctrl_s_axis_tdata[304+:8],
ctrl_s_axis_tdata[312+:8],
ctrl_s_axis_tdata[320+:8],
ctrl_s_axis_tdata[328+:8],
ctrl_s_axis_tdata[336+:8],
ctrl_s_axis_tdata[344+:8],
ctrl_s_axis_tdata[352+:8],
ctrl_s_axis_tdata[360+:8],
ctrl_s_axis_tdata[368+:8],
ctrl_s_axis_tdata[376+:8],
ctrl_s_axis_tdata[384+:8],
ctrl_s_axis_tdata[392+:8],
ctrl_s_axis_tdata[400+:8],
ctrl_s_axis_tdata[408+:8],
ctrl_s_axis_tdata[416+:8],
ctrl_s_axis_tdata[424+:8],
ctrl_s_axis_tdata[432+:8],
ctrl_s_axis_tdata[440+:8],
ctrl_s_axis_tdata[448+:8],
ctrl_s_axis_tdata[456+:8],
ctrl_s_axis_tdata[464+:8],
ctrl_s_axis_tdata[472+:8],
ctrl_s_axis_tdata[480+:8],
ctrl_s_axis_tdata[488+:8],
ctrl_s_axis_tdata[496+:8],
ctrl_s_axis_tdata[504+:8]
};
always @(posedge clk or negedge aresetn) begin
if(~aresetn) begin
c_wr_en <= 1'b0;
c_index <= 4'b0;
entry_reg <= 0;
c_state <= IDLE_C;
end
else begin
case(c_state)
IDLE_C: begin
if(ctrl_s_axis_tvalid && mod_id[2:0] == DEPARSER_MOD_ID && control_flag == 16'hf2f1)begin
c_wr_en <= 1'b0;
c_index <= ctrl_s_axis_tdata[384+:8];
c_state <= WRITE_C;
end
else begin
c_wr_en <= 1'b0;
c_index <= 4'b0;
entry_reg <= 0;
c_state <= IDLE_C;
end
end
//support full table flush
WRITE_C: begin
if(ctrl_s_axis_tvalid) begin
c_wr_en <= 1'b1;
entry_reg <= ctrl_s_axis_tdata_swapped[511 -: 160];
if(ctrl_s_axis_tlast) begin
c_state <= IDLE_C;
end
else begin
c_state <= SU_WRITE_C;
end
end
else begin
c_wr_en <= 1'b0;
end
end
SU_WRITE_C: begin
if(ctrl_s_axis_tvalid) begin
entry_reg <= ctrl_s_axis_tdata_swapped[511 -: 160];
c_wr_en <= 1'b1;
c_index <= c_index + 1'b1;
if(ctrl_s_axis_tlast) begin
c_state <= IDLE_C;
end
else begin
c_state <= SU_WRITE_C;
end
end
else begin
c_wr_en <= 1'b0;
end
end
endcase
end
end
parse_act_ram_ip
parse_act_ram
(
// write port
.clka (clk),
.addra (c_index[4:0]),
.dina (entry_reg),
.ena (1'b1),
.wea (c_wr_en),
//
.clkb (clk),
.addrb (vlan_id[8:4]), // TODO: note that we may change due to little or big endian
.doutb (bram_out),
.enb (1'b1) // always set to 1
);
endmodule
sims/net/menshen/rtl/depar_wait_segs.v 0 → 100644
View file @ c15f2eab
`timescale 1ns / 1ps
module depar_wait_segs #(
parameter C_AXIS_DATA_WIDTH = 512,
parameter C_AXIS_TUSER_WIDTH = 128
)
(
input clk,
input aresetn,
// input from pkt fifo
input [C_AXIS_DATA_WIDTH-1:0] pkt_fifo_tdata,
input [C_AXIS_TUSER_WIDTH-1:0] pkt_fifo_tuser,
input [C_AXIS_DATA_WIDTH/8-1:0] pkt_fifo_tkeep,
input pkt_fifo_tlast,
input pkt_fifo_empty,
input fst_half_fifo_ready,
input snd_half_fifo_ready,
// output
output reg pkt_fifo_rd_en,
output reg [11:0] vlan,
output reg vlan_valid,
output reg [C_AXIS_DATA_WIDTH-1:0] fst_half_tdata,
output reg [C_AXIS_TUSER_WIDTH-1:0] fst_half_tuser,
output reg [C_AXIS_DATA_WIDTH/8-1:0] fst_half_tkeep,
output reg fst_half_tlast,
output reg fst_half_valid,
output reg [C_AXIS_DATA_WIDTH-1:0] snd_half_tdata,
output reg [C_AXIS_TUSER_WIDTH-1:0] snd_half_tuser,
output reg [C_AXIS_DATA_WIDTH/8-1:0] snd_half_tkeep,
output reg snd_half_tlast,
output reg snd_half_valid,
// output remaining segs to FIFO
output reg [C_AXIS_DATA_WIDTH-1:0] output_fifo_tdata,
output reg [C_AXIS_TUSER_WIDTH-1:0] output_fifo_tuser,
output reg [C_AXIS_DATA_WIDTH/8-1:0] output_fifo_tkeep,
output reg output_fifo_tlast,
output reg output_fifo_valid,
input output_fifo_ready
);
localparam WAIT_FIRST_SEG=0,
WAIT_SECOND_SEG=1,
EMPTY_1=2,
EMPTY_2=3,
FLUSH_SEG=4;
reg [C_AXIS_DATA_WIDTH-1:0] output_fifo_tdata_next;
reg [C_AXIS_TUSER_WIDTH-1:0] output_fifo_tuser_next;
reg [C_AXIS_DATA_WIDTH/8-1:0] output_fifo_tkeep_next;
reg output_fifo_tlast_next;
reg output_fifo_valid_next;
reg [C_AXIS_DATA_WIDTH-1:0] fst_half_tdata_next, snd_half_tdata_next;
reg [C_AXIS_TUSER_WIDTH-1:0] fst_half_tuser_next, snd_half_tuser_next;
reg [C_AXIS_DATA_WIDTH/8-1:0] fst_half_tkeep_next, snd_half_tkeep_next;
reg fst_half_tlast_next, snd_half_tlast_next;
reg fst_half_valid_next, snd_half_valid_next;
reg vlan_valid_next;
reg [11:0] vlan_next;
reg [2:0] state, state_next;
// we delay the processing of PHV to the next module
always @(*) begin
state_next = state;
pkt_fifo_rd_en = 0;
fst_half_tdata_next = 0;
fst_half_tuser_next = 0;
fst_half_tkeep_next = 0;
fst_half_tlast_next = 0;
snd_half_tdata_next = 0;
snd_half_tuser_next = 0;
snd_half_tkeep_next = 0;
snd_half_tlast_next = 0;
fst_half_valid_next = 0;
snd_half_valid_next = 0;
vlan_valid_next = 0;
vlan_next = vlan;
// output remaining segs
output_fifo_tdata_next = 0;
output_fifo_tuser_next = 0;
output_fifo_tkeep_next = 0;
output_fifo_tlast_next = 0;
output_fifo_valid_next = 0;
case (state)
WAIT_FIRST_SEG: begin
if (!pkt_fifo_empty) begin
fst_half_tdata_next = pkt_fifo_tdata;
fst_half_tuser_next = pkt_fifo_tuser;
fst_half_tkeep_next = pkt_fifo_tkeep;
fst_half_tlast_next = pkt_fifo_tlast;
vlan_next = pkt_fifo_tdata[116+:12];
if (pkt_fifo_tlast) begin
if (fst_half_fifo_ready && snd_half_fifo_ready) begin
pkt_fifo_rd_en = 1;
fst_half_valid_next = 1;
snd_half_valid_next = 1;
vlan_valid_next = 1;
state_next = WAIT_FIRST_SEG;
end
end
else begin
if (fst_half_fifo_ready) begin
pkt_fifo_rd_en = 1;
fst_half_valid_next = 1;
vlan_valid_next = 1;
state_next = WAIT_SECOND_SEG;
end
end
end
end
WAIT_SECOND_SEG: begin
if (!pkt_fifo_empty) begin
snd_half_tdata_next = pkt_fifo_tdata;
snd_half_tuser_next = pkt_fifo_tuser;
snd_half_tkeep_next = pkt_fifo_tkeep;
snd_half_tlast_next = pkt_fifo_tlast;
if (pkt_fifo_tlast) begin
if (snd_half_fifo_ready) begin
pkt_fifo_rd_en = 1;
snd_half_valid_next = 1;
state_next = WAIT_FIRST_SEG;
end
end
else begin
if (snd_half_fifo_ready) begin
pkt_fifo_rd_en = 1;
snd_half_valid_next = 1;
state_next = FLUSH_SEG;
end
end
end
end
FLUSH_SEG: begin
if (!pkt_fifo_empty) begin
output_fifo_tdata_next = pkt_fifo_tdata;
output_fifo_tuser_next = pkt_fifo_tuser;
output_fifo_tkeep_next = pkt_fifo_tkeep;
output_fifo_tlast_next = pkt_fifo_tlast;
if (output_fifo_ready) begin
output_fifo_valid_next = 1;
pkt_fifo_rd_en = 1;
if (pkt_fifo_tlast) begin
state_next = WAIT_FIRST_SEG;
end
end
end
end
endcase
end
always @(posedge clk) begin
if (~aresetn) begin
state <= WAIT_FIRST_SEG;
fst_half_tdata <= 0;
fst_half_tuser <= 0;
fst_half_tkeep <= 0;
fst_half_tlast <= 0;
snd_half_tdata <= 0;
snd_half_tuser <= 0;
snd_half_tkeep <= 0;
snd_half_tlast <= 0;
fst_half_valid <= 0;
snd_half_valid <= 0;
vlan_valid <= 0;
vlan <= 0;
//
output_fifo_tdata <= 0;
output_fifo_tuser <= 0;
output_fifo_tkeep <= 0;
output_fifo_tlast <= 0;
output_fifo_valid <= 0;
end
else begin
state <= state_next;
fst_half_tdata <= fst_half_tdata_next;
fst_half_tuser <= fst_half_tuser_next;
fst_half_tkeep <= fst_half_tkeep_next;
fst_half_tlast <= fst_half_tlast_next;
snd_half_tdata <= snd_half_tdata_next;
snd_half_tuser <= snd_half_tuser_next;
snd_half_tkeep <= snd_half_tkeep_next;
snd_half_tlast <= snd_half_tlast_next;
fst_half_valid <= fst_half_valid_next;
snd_half_valid <= snd_half_valid_next;
vlan_valid <= vlan_valid_next;
vlan <= vlan_next;
//
output_fifo_tdata <= output_fifo_tdata_next;
output_fifo_tuser <= output_fifo_tuser_next;
output_fifo_tkeep <= output_fifo_tkeep_next;
output_fifo_tlast <= output_fifo_tlast_next;
output_fifo_valid <= output_fifo_valid_next;
end
end
endmodule
sims/net/menshen/rtl/deparser_top.v 0 → 100644
View file @ c15f2eab
`timescale 1ns / 1ps
module deparser_top #(
parameter C_AXIS_DATA_WIDTH = 512,
parameter C_AXIS_TUSER_WIDTH = 128,
parameter C_PKT_VEC_WIDTH = (6+4+2)*8*8+256,
parameter DEPARSER_MOD_ID = 3'b101,
parameter C_VLANID_WIDTH = 12,
parameter C_FIFO_BITS_WIDTH = 4
)
(
input axis_clk,
input aresetn,
//
input [C_AXIS_DATA_WIDTH-1:0] pkt_fifo_tdata,
input [C_AXIS_DATA_WIDTH/8-1:0] pkt_fifo_tkeep,
input [C_AXIS_TUSER_WIDTH-1:0] pkt_fifo_tuser,
input pkt_fifo_tlast,
input pkt_fifo_empty,
output pkt_fifo_rd_en,
input [C_PKT_VEC_WIDTH-1:0] phv_fifo_out,
input phv_fifo_empty,
output phv_fifo_rd_en,
output [C_AXIS_DATA_WIDTH-1:0] depar_out_tdata,
output [C_AXIS_DATA_WIDTH/8-1:0] depar_out_tkeep,
output [C_AXIS_TUSER_WIDTH-1:0] depar_out_tuser,
output depar_out_tvalid,
output depar_out_tlast,
input depar_out_tready,
// control path
input [C_AXIS_DATA_WIDTH-1:0] ctrl_s_axis_tdata,
input [C_AXIS_TUSER_WIDTH-1:0] ctrl_s_axis_tuser,
input [C_AXIS_DATA_WIDTH/8-1:0] ctrl_s_axis_tkeep,
input ctrl_s_axis_tvalid,
input ctrl_s_axis_tlast
);
wire [C_AXIS_DATA_WIDTH-1:0] fst_half_fifo_tdata_in, fst_half_fifo_tdata_out;
wire [C_AXIS_TUSER_WIDTH-1:0] fst_half_fifo_tuser_in, fst_half_fifo_tuser_out;
wire [C_AXIS_DATA_WIDTH/8-1:0] fst_half_fifo_tkeep_in, fst_half_fifo_tkeep_out;
wire fst_half_fifo_tlast_in, fst_half_fifo_tlast_out;
wire fst_half_fifo_empty;
wire fst_half_fifo_full;
wire fst_half_fifo_valid_in;
wire fst_half_fifo_rd_en;
reg [C_AXIS_DATA_WIDTH-1:0] fst_half_fifo_tdata_in_r;
reg [C_AXIS_TUSER_WIDTH-1:0] fst_half_fifo_tuser_in_r;
reg [C_AXIS_DATA_WIDTH/8-1:0] fst_half_fifo_tkeep_in_r;
reg fst_half_fifo_tlast_in_r;
reg fst_half_fifo_valid_in_r;
wire [C_AXIS_DATA_WIDTH-1:0] snd_half_fifo_tdata_in, snd_half_fifo_tdata_out;
wire [C_AXIS_TUSER_WIDTH-1:0] snd_half_fifo_tuser_in, snd_half_fifo_tuser_out;
wire [C_AXIS_DATA_WIDTH/8-1:0] snd_half_fifo_tkeep_in, snd_half_fifo_tkeep_out;
wire snd_half_fifo_tlast_in, snd_half_fifo_tlast_out;
wire snd_half_fifo_empty;
wire snd_half_fifo_full;
wire snd_half_fifo_valid_in;
wire snd_half_fifo_rd_en;
reg [C_AXIS_DATA_WIDTH-1:0] snd_half_fifo_tdata_in_r;
reg [C_AXIS_TUSER_WIDTH-1:0] snd_half_fifo_tuser_in_r;
reg [C_AXIS_DATA_WIDTH/8-1:0] snd_half_fifo_tkeep_in_r;
reg snd_half_fifo_tlast_in_r;
reg snd_half_fifo_valid_in_r;
fallthrough_small_fifo #(
.WIDTH(C_AXIS_DATA_WIDTH+C_AXIS_TUSER_WIDTH+C_AXIS_DATA_WIDTH/8+1),
.MAX_DEPTH_BITS(4)
)
fst_half_fifo (
.din ({fst_half_fifo_tdata_in_r, fst_half_fifo_tuser_in_r, fst_half_fifo_tkeep_in_r, fst_half_fifo_tlast_in_r}),
.wr_en (fst_half_fifo_valid_in_r),
// .din ({fst_half_fifo_tdata_in, fst_half_fifo_tuser_in, fst_half_fifo_tkeep_in, fst_half_fifo_tlast_in}),
// .wr_en (fst_half_fifo_valid_in),
//
.rd_en (fst_half_fifo_rd_en),
.dout ({fst_half_fifo_tdata_out, fst_half_fifo_tuser_out, fst_half_fifo_tkeep_out, fst_half_fifo_tlast_out}),
//
.full (),
.prog_full (),
.nearly_full (fst_half_fifo_full),
.empty (fst_half_fifo_empty),
.reset (~aresetn),
.clk (axis_clk)
);
fallthrough_small_fifo #(
.WIDTH(C_AXIS_DATA_WIDTH+C_AXIS_TUSER_WIDTH+C_AXIS_DATA_WIDTH/8+1),
.MAX_DEPTH_BITS(4)
)
snd_half_fifo (
.din ({snd_half_fifo_tdata_in_r, snd_half_fifo_tuser_in_r, snd_half_fifo_tkeep_in_r, snd_half_fifo_tlast_in_r}),
.wr_en (snd_half_fifo_valid_in_r),
// .din ({snd_half_fifo_tdata_in, snd_half_fifo_tuser_in, snd_half_fifo_tkeep_in, snd_half_fifo_tlast_in}),
// .wr_en (snd_half_fifo_valid_in),
//
.rd_en (snd_half_fifo_rd_en),
.dout ({snd_half_fifo_tdata_out, snd_half_fifo_tuser_out, snd_half_fifo_tkeep_out, snd_half_fifo_tlast_out}),
//
.full (),
.prog_full (),
.nearly_full (snd_half_fifo_full),
.empty (snd_half_fifo_empty),
.reset (~aresetn),
.clk (axis_clk)
);
//===============================================
wire [C_VLANID_WIDTH-1:0] vlan_fifo_in, vlan_fifo_out;
wire vlan_valid_in;
wire vlan_fifo_rd_en;
wire vlan_fifo_full;
wire vlan_fifo_empty;
// vlan fifo
fallthrough_small_fifo #(
.WIDTH(C_VLANID_WIDTH),
.MAX_DEPTH_BITS(5)
)
vlan_fifo (
.din (vlan_fifo_in),
.wr_en (vlan_valid_in),
//
.rd_en (vlan_fifo_rd_en),
.dout (vlan_fifo_out),
//
.full (),
.prog_full (),
.nearly_full (vlan_fifo_full),
.empty (vlan_fifo_empty),
.reset (~aresetn),
.clk (axis_clk)
);
wire [C_AXIS_DATA_WIDTH-1:0] seg_fifo_tdata_in, seg_fifo_tdata_out;
wire [C_AXIS_TUSER_WIDTH-1:0] seg_fifo_tuser_in, seg_fifo_tuser_out;
wire [C_AXIS_DATA_WIDTH/8-1:0] seg_fifo_tkeep_in, seg_fifo_tkeep_out;
wire seg_fifo_tlast_in, seg_fifo_tlast_out;
wire seg_fifo_valid_in;
wire seg_fifo_rd_en;
wire seg_fifo_full;
wire seg_fifo_empty;
reg [C_AXIS_DATA_WIDTH-1:0] seg_fifo_tdata_in_r;
reg [C_AXIS_TUSER_WIDTH-1:0] seg_fifo_tuser_in_r;
reg [C_AXIS_DATA_WIDTH/8-1:0] seg_fifo_tkeep_in_r;
reg seg_fifo_tlast_in_r;
reg seg_fifo_valid_in_r;
// seg fifo
fallthrough_small_fifo #(
.WIDTH(C_AXIS_DATA_WIDTH+C_AXIS_TUSER_WIDTH+C_AXIS_DATA_WIDTH/8+1),
.MAX_DEPTH_BITS(5)
)
seg_fifo (
.din ({seg_fifo_tdata_in_r, seg_fifo_tuser_in_r, seg_fifo_tkeep_in_r, seg_fifo_tlast_in_r}),
.wr_en (seg_fifo_valid_in_r),
// .din ({seg_fifo_tdata_in, seg_fifo_tuser_in, seg_fifo_tkeep_in, seg_fifo_tlast_in}),
// .wr_en (seg_fifo_valid_in),
//
.rd_en (seg_fifo_rd_en),
.dout ({seg_fifo_tdata_out, seg_fifo_tuser_out, seg_fifo_tkeep_out, seg_fifo_tlast_out}),
//
.full (),
.prog_full (),
.nearly_full (seg_fifo_full),
.empty (seg_fifo_empty),
.reset (~aresetn),
.clk (axis_clk)
);
//
depar_wait_segs #(
)
wait_segs
(
.clk (axis_clk),
.aresetn (aresetn),
.pkt_fifo_tdata (pkt_fifo_tdata),
.pkt_fifo_tuser (pkt_fifo_tuser),
.pkt_fifo_tkeep (pkt_fifo_tkeep),
.pkt_fifo_tlast (pkt_fifo_tlast),
.pkt_fifo_empty (pkt_fifo_empty),
.fst_half_fifo_ready (~fst_half_fifo_full),
.snd_half_fifo_ready (~snd_half_fifo_full),
.pkt_fifo_rd_en (pkt_fifo_rd_en),
.vlan (vlan_fifo_in),
.vlan_valid (vlan_valid_in),
.fst_half_tdata (fst_half_fifo_tdata_in),
.fst_half_tuser (fst_half_fifo_tuser_in),
.fst_half_tkeep (fst_half_fifo_tkeep_in),
.fst_half_tlast (fst_half_fifo_tlast_in),
.fst_half_valid (fst_half_fifo_valid_in),
//
.snd_half_tdata (snd_half_fifo_tdata_in),
.snd_half_tuser (snd_half_fifo_tuser_in),
.snd_half_tkeep (snd_half_fifo_tkeep_in),
.snd_half_tlast (snd_half_fifo_tlast_in),
.snd_half_valid (snd_half_fifo_valid_in),
//
.output_fifo_tdata (seg_fifo_tdata_in),
.output_fifo_tuser (seg_fifo_tuser_in),
.output_fifo_tkeep (seg_fifo_tkeep_in),
.output_fifo_tlast (seg_fifo_tlast_in),
.output_fifo_valid (seg_fifo_valid_in),
.output_fifo_ready (~seg_fifo_full)
);
//
depar_do_deparsing #(
.C_PKT_VEC_WIDTH(C_PKT_VEC_WIDTH),
.DEPARSER_MOD_ID(DEPARSER_MOD_ID)
)
do_deparsing
(
.clk (axis_clk),
.aresetn (aresetn),
// phv
.phv_fifo_out (phv_fifo_out),
.phv_fifo_empty (phv_fifo_empty),
.phv_fifo_rd_en (phv_fifo_rd_en),
// vlan
.vlan_id (vlan_fifo_out),
.vlan_fifo_empty (vlan_fifo_empty),
.vlan_fifo_rd_en (vlan_fifo_rd_en),
// first half
.fst_half_fifo_tdata (fst_half_fifo_tdata_out),
.fst_half_fifo_tuser (fst_half_fifo_tuser_out),
.fst_half_fifo_tkeep (fst_half_fifo_tkeep_out),
.fst_half_fifo_tlast (fst_half_fifo_tlast_out),
.fst_half_fifo_empty (fst_half_fifo_empty),
.fst_half_fifo_rd_en (fst_half_fifo_rd_en),
// second half
.snd_half_fifo_tdata (snd_half_fifo_tdata_out),
.snd_half_fifo_tuser (snd_half_fifo_tuser_out),
.snd_half_fifo_tkeep (snd_half_fifo_tkeep_out),
.snd_half_fifo_tlast (snd_half_fifo_tlast_out),
.snd_half_fifo_empty (snd_half_fifo_empty),
.snd_half_fifo_rd_en (snd_half_fifo_rd_en),
// segs
.pkt_fifo_tdata (seg_fifo_tdata_out),
.pkt_fifo_tuser (seg_fifo_tuser_out),
.pkt_fifo_tkeep (seg_fifo_tkeep_out),
.pkt_fifo_tlast (seg_fifo_tlast_out),
.pkt_fifo_empty (seg_fifo_empty),
.pkt_fifo_rd_en (seg_fifo_rd_en),
// output
.depar_out_tdata (depar_out_tdata),
.depar_out_tuser (depar_out_tuser),
.depar_out_tkeep (depar_out_tkeep),
.depar_out_tlast (depar_out_tlast),
.depar_out_tvalid (depar_out_tvalid),
.depar_out_tready (depar_out_tready),
// control path
.ctrl_s_axis_tdata (ctrl_s_axis_tdata),
.ctrl_s_axis_tuser (ctrl_s_axis_tuser),
.ctrl_s_axis_tkeep (ctrl_s_axis_tkeep),
.ctrl_s_axis_tvalid (ctrl_s_axis_tvalid),
.ctrl_s_axis_tlast (ctrl_s_axis_tlast)
);
always @(posedge axis_clk) begin
if (~aresetn) begin
//
fst_half_fifo_tdata_in_r <= 0;
fst_half_fifo_tuser_in_r <= 0;
fst_half_fifo_tkeep_in_r <= 0;
fst_half_fifo_tlast_in_r <= 0;
fst_half_fifo_valid_in_r <= 0;
//
snd_half_fifo_tdata_in_r <= 0;
snd_half_fifo_tuser_in_r <= 0;
snd_half_fifo_tkeep_in_r <= 0;
snd_half_fifo_tlast_in_r <= 0;
snd_half_fifo_valid_in_r <= 0;
//
seg_fifo_tdata_in_r <= 0;
seg_fifo_tuser_in_r <= 0;
seg_fifo_tkeep_in_r <= 0;
seg_fifo_tlast_in_r <= 0;
seg_fifo_valid_in_r <= 0;
end
else begin
//
fst_half_fifo_tdata_in_r <= fst_half_fifo_tdata_in;
fst_half_fifo_tuser_in_r <= fst_half_fifo_tuser_in;
fst_half_fifo_tkeep_in_r <= fst_half_fifo_tkeep_in;
fst_half_fifo_tlast_in_r <= fst_half_fifo_tlast_in;
fst_half_fifo_valid_in_r <= fst_half_fifo_valid_in;
//
snd_half_fifo_tdata_in_r <= snd_half_fifo_tdata_in;
snd_half_fifo_tuser_in_r <= snd_half_fifo_tuser_in;
snd_half_fifo_tkeep_in_r <= snd_half_fifo_tkeep_in;
snd_half_fifo_tlast_in_r <= snd_half_fifo_tlast_in;
snd_half_fifo_valid_in_r <= snd_half_fifo_valid_in;
//
seg_fifo_tdata_in_r <= seg_fifo_tdata_in;
seg_fifo_tuser_in_r <= seg_fifo_tuser_in;
seg_fifo_tkeep_in_r <= seg_fifo_tkeep_in;
seg_fifo_tlast_in_r <= seg_fifo_tlast_in;
seg_fifo_valid_in_r <= seg_fifo_valid_in;
end
end
endmodule
sims/net/menshen/rtl/extract/key_extract.v 0 → 100644
View file @ c15f2eab
`timescale 1ns / 1ps
module key_extract #(
parameter C_S_AXIS_DATA_WIDTH = 512,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter STAGE_ID = 0,
parameter PHV_LEN = 48*8+32*8+16*8+256,
parameter KEY_LEN = 48*2+32*2+16*2+1,
// format of KEY_OFF entry: |--3(6B)--|--3(6B)--|--3(4B)--|--3(4B)--|--3(2B)--|--3(2B)--|
parameter KEY_OFF = (3+3)*3+20,
parameter AXIL_WIDTH = 32,
parameter KEY_OFF_ADDR_WIDTH = 4,
parameter KEY_EX_ID = 1,
parameter C_VLANID_WIDTH = 12
)(
input clk,
input rst_n,
//
input [PHV_LEN-1:0] phv_in,
input phv_valid_in,
output ready_out,
// input from vlan fifo
input key_offset_valid,
input [KEY_OFF-1:0] key_offset_w,
input [KEY_LEN-1:0] key_mask_w,
// output PHV and key
output reg [PHV_LEN-1:0] phv_out,
output reg phv_valid_out,
output [KEY_LEN-1:0] key_out_masked,
output reg key_valid_out,
input ready_in
);
integer i;
localparam WIDTH_2B = 16;
localparam WIDTH_4B = 32;
localparam WIDTH_6B = 48;
//reg [KEY_LEN-1:0] key_out;
//24 fields to be retrived from the pkt header
reg [WIDTH_2B-1:0] cont_2B [0:7];
reg [WIDTH_4B-1:0] cont_4B [0:7];
reg [WIDTH_6B-1:0] cont_6B [0:7];
wire [19:0] com_op;
wire [47:0] com_op_1, com_op_2;
wire [47:0] com_op_1_val, com_op_2_val;
//
reg [KEY_OFF-1:0] key_offset_r;
//
reg [KEY_LEN-1:0] key_mask_out_r;
//
assign com_op = key_offset_r[0+:20];
assign com_op_1 = com_op[17]==1? {40'b0, com_op[16:9]} : com_op_1_val;
assign com_op_1_val = com_op[13:12]==2?cont_6B[com_op[11:9]][7:0]:
(com_op[13:12]==1?{16'b0, cont_4B[com_op[11:9]][7:0]}:
(com_op[13:12]==0?{32'b0, cont_2B[com_op[11:9]][7:0]}:0));
assign com_op_2 = com_op[8]==1? {40'b0, com_op[7:0]} : com_op_2_val;
assign com_op_2_val = com_op[4:3]==2?cont_6B[com_op[2:0]][7:0]:
(com_op[4:3]==1?{16'b0, cont_4B[com_op[2:0]][7:0]}:
(com_op[4:3]==0?{32'b0, cont_2B[com_op[2:0]][7:0]}:0));
localparam IDLE_S=0,
CYCLE_1=1;
reg [2:0] state, state_next;
reg [KEY_LEN-1:0] key_out;
// reg ready_out_next;
assign ready_out = 1;
assign key_out_masked = key_out&(~key_mask_out_r);
always @(posedge clk) begin
if (~rst_n) begin
key_out <= 0;
state <= IDLE_S;
for (i=0; i<8; i=i+1) begin
cont_6B[i] <= 0;
cont_4B[i] <= 0;
cont_2B[i] <= 0;
end
phv_out <= 0;
phv_valid_out <= 0;
key_valid_out <= 0;
key_offset_r <= 0;
key_mask_out_r <= 0;
end
else begin
case (state)
IDLE_S: begin
if (phv_valid_in) begin
key_offset_r <= key_offset_w;
key_mask_out_r <= key_mask_w;
phv_out <= phv_in;
cont_6B[7] <= phv_in[PHV_LEN-1 -: WIDTH_6B];
cont_6B[6] <= phv_in[PHV_LEN-1- WIDTH_6B -: WIDTH_6B];
cont_6B[5] <= phv_in[PHV_LEN-1-2*WIDTH_6B -: WIDTH_6B];
cont_6B[4] <= phv_in[PHV_LEN-1-3*WIDTH_6B -: WIDTH_6B];
cont_6B[3] <= phv_in[PHV_LEN-1-4*WIDTH_6B -: WIDTH_6B];
cont_6B[2] <= phv_in[PHV_LEN-1-5*WIDTH_6B -: WIDTH_6B];
cont_6B[1] <= phv_in[PHV_LEN-1-6*WIDTH_6B -: WIDTH_6B];
cont_6B[0] <= phv_in[PHV_LEN-1-7*WIDTH_6B -: WIDTH_6B];
cont_4B[7] <= phv_in[PHV_LEN-1-8*WIDTH_6B -: WIDTH_4B];
cont_4B[6] <= phv_in[PHV_LEN-1-8*WIDTH_6B- WIDTH_4B -: WIDTH_4B];
cont_4B[5] <= phv_in[PHV_LEN-1-8*WIDTH_6B-2*WIDTH_4B -: WIDTH_4B];
cont_4B[4] <= phv_in[PHV_LEN-1-8*WIDTH_6B-3*WIDTH_4B -: WIDTH_4B];
cont_4B[3] <= phv_in[PHV_LEN-1-8*WIDTH_6B-4*WIDTH_4B -: WIDTH_4B];
cont_4B[2] <= phv_in[PHV_LEN-1-8*WIDTH_6B-5*WIDTH_4B -: WIDTH_4B];
cont_4B[1] <= phv_in[PHV_LEN-1-8*WIDTH_6B-6*WIDTH_4B -: WIDTH_4B];
cont_4B[0] <= phv_in[PHV_LEN-1-8*WIDTH_6B-7*WIDTH_4B -: WIDTH_4B];
cont_2B[7] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B -: WIDTH_2B];
cont_2B[6] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B- WIDTH_2B -: WIDTH_2B];
cont_2B[5] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B-2*WIDTH_2B -: WIDTH_2B];
cont_2B[4] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B-3*WIDTH_2B -: WIDTH_2B];
cont_2B[3] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B-4*WIDTH_2B -: WIDTH_2B];
cont_2B[2] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B-5*WIDTH_2B -: WIDTH_2B];
cont_2B[1] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B-6*WIDTH_2B -: WIDTH_2B];
cont_2B[0] <= phv_in[PHV_LEN-1-8*WIDTH_6B-8*WIDTH_4B-7*WIDTH_2B -: WIDTH_2B];
state <= CYCLE_1;
end
else begin
phv_valid_out <= 0;
key_valid_out <= 0;
end
end
CYCLE_1: begin
key_out[KEY_LEN-1 -: WIDTH_6B] <= cont_6B[key_offset_r[KEY_OFF-1 -: 3]];
key_out[KEY_LEN-1- 1*WIDTH_6B -: WIDTH_6B] <= cont_6B[key_offset_r[KEY_OFF-1-1*3 -: 3]];
key_out[KEY_LEN-1- 2*WIDTH_6B -: WIDTH_4B] <= cont_4B[key_offset_r[KEY_OFF-1-2*3 -: 3]];
key_out[KEY_LEN-1- 2*WIDTH_6B - 1*WIDTH_4B -: WIDTH_4B] <= cont_4B[key_offset_r[KEY_OFF-1-3*3 -: 3]];
key_out[KEY_LEN-1- 2*WIDTH_6B - 2*WIDTH_4B -: WIDTH_2B] <= cont_2B[key_offset_r[KEY_OFF-1-4*3 -: 3]];
key_out[KEY_LEN-1- 2*WIDTH_6B - 2*WIDTH_4B - WIDTH_2B -: WIDTH_2B] <= cont_2B[key_offset_r[KEY_OFF-1-5*3 -: 3]];
case(com_op[19:18])
2'b00: begin
key_out[0] <= (com_op_1>com_op_2)?1'b1:1'b0;
end
2'b01: begin
key_out[0] <= (com_op_1>=com_op_2)?1'b1:1'b0;
end
2'b10: begin
key_out[0] <= (com_op_1==com_op_2)?1'b1:1'b0;
end
default: begin
key_out[0] <= 1'b1;
end
endcase
phv_valid_out <= 1;
key_valid_out <= 1;
state <= IDLE_S;
end
endcase
end
end
endmodule
sims/net/menshen/rtl/extract/key_extract_top.v 0 → 100644
View file @ c15f2eab
This diff is collapsed.
sims/net/menshen/rtl/last_stage.v 0 → 100644
View file @ c15f2eab
This diff is collapsed.
sims/net/menshen/rtl/lookup/lke_cam_part.v 0 → 100644
View file @ c15f2eab
This diff is collapsed.
sims/net/menshen/rtl/lookup/lke_ram_part.v 0 → 100644
View file @ c15f2eab
This diff is collapsed.
sims/net/menshen/rtl/lookup/lookup_engine_top.v 0 → 100644
View file @ c15f2eab
`timescale 1ns / 1ps
module lookup_engine_top #(
parameter C_S_AXIS_DATA_WIDTH = 512,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter STAGE_ID = 0,
parameter PHV_LEN = 48*8+32*8+16*8+256,
parameter KEY_LEN = 48*2+32*2+16*2+5,
parameter ACT_LEN = 625,
parameter LOOKUP_ID = 2,
parameter C_VLANID_WIDTH = 12
)
(
input clk,
input rst_n,
//output from key extractor
input [KEY_LEN-1:0] extract_key,
input key_valid,
input phv_valid,
input [PHV_LEN-1:0] phv_in,
output ready_out,
//output to the action engine
output [ACT_LEN-1:0] action,
output action_valid,
output [PHV_LEN-1:0] phv_out,
input ready_in,
// output vlan to ALU vlan fifo
output [C_VLANID_WIDTH-1:0] act_vlan_out,
output act_vlan_valid_out,
input act_vlan_ready,
//control path
input [C_S_AXIS_DATA_WIDTH-1:0] c_s_axis_tdata,
input [C_S_AXIS_TUSER_WIDTH-1:0] c_s_axis_tuser,
input [C_S_AXIS_DATA_WIDTH/8-1:0] c_s_axis_tkeep,
input c_s_axis_tvalid,
input c_s_axis_tlast,
output [C_S_AXIS_DATA_WIDTH-1:0] c_m_axis_tdata,
output [C_S_AXIS_TUSER_WIDTH-1:0] c_m_axis_tuser,
output [C_S_AXIS_DATA_WIDTH/8-1:0] c_m_axis_tkeep,
output c_m_axis_tvalid,
output c_m_axis_tlast
);
wire [C_S_AXIS_DATA_WIDTH-1:0] c_s_axis_tdata_0;
wire [C_S_AXIS_TUSER_WIDTH-1:0] c_s_axis_tuser_0;
wire [C_S_AXIS_DATA_WIDTH/8-1:0] c_s_axis_tkeep_0;
wire c_s_axis_tvalid_0;
wire c_s_axis_tlast_0;
wire [PHV_LEN-1:0] cam_phv_out;
wire cam_phv_out_valid;
wire [3:0] cam_match_addr_out;
wire cam_if_match;
wire lke_ram_ready;
reg [PHV_LEN-1:0] cam_phv_out_d1;
reg cam_phv_out_valid_d1;
reg [3:0] cam_match_addr_out_d1;
reg cam_if_match_d1;
always @(posedge clk) begin
if (~rst_n) begin
cam_phv_out_d1 <= 0;
cam_phv_out_valid_d1 <= 0;
cam_match_addr_out_d1 <= 0;
cam_if_match_d1 <= 0;
end
else begin
cam_phv_out_d1 <= cam_phv_out;
cam_phv_out_valid_d1 <= cam_phv_out_valid;
cam_match_addr_out_d1 <= cam_match_addr_out;
cam_if_match_d1 <= cam_if_match;
end
end
lke_cam_part #(
.C_S_AXIS_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_S_AXIS_TUSER_WIDTH(C_S_AXIS_TUSER_WIDTH),
.STAGE_ID(STAGE_ID),
.PHV_LEN(PHV_LEN),
.KEY_LEN(KEY_LEN),
.ACT_LEN(ACT_LEN),
.LOOKUP_ID(LOOKUP_ID),
.C_VLANID_WIDTH(C_VLANID_WIDTH)
)
lke_cam (
.clk (clk),
.rst_n (rst_n),
.extract_key (extract_key),
.key_valid (key_valid),
.phv_valid (phv_valid),
.phv_in (phv_in),
.ready_out (ready_out),
//
.phv_out (cam_phv_out),
.phv_out_valid (cam_phv_out_valid),
.match_addr_out (cam_match_addr_out),
.if_match (cam_if_match),
.ready_in (lke_ram_ready),
//
.c_s_axis_tdata (c_s_axis_tdata),
.c_s_axis_tuser (c_s_axis_tuser),
.c_s_axis_tkeep (c_s_axis_tkeep),
.c_s_axis_tvalid (c_s_axis_tvalid),
.c_s_axis_tlast (c_s_axis_tlast),
.c_m_axis_tdata (c_s_axis_tdata_0),
.c_m_axis_tuser (c_s_axis_tuser_0),
.c_m_axis_tkeep (c_s_axis_tkeep_0),
.c_m_axis_tvalid (c_s_axis_tvalid_0),
.c_m_axis_tlast (c_s_axis_tlast_0)
);
lke_ram_part #(
.C_S_AXIS_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_S_AXIS_TUSER_WIDTH(C_S_AXIS_TUSER_WIDTH),
.STAGE_ID(STAGE_ID),
.PHV_LEN(PHV_LEN),
.KEY_LEN(KEY_LEN),
.ACT_LEN(ACT_LEN),
.LOOKUP_ID(LOOKUP_ID),
.C_VLANID_WIDTH(C_VLANID_WIDTH)
)
lke_ram (
.clk (clk),
.rst_n (rst_n),
.phv_in (cam_phv_out_d1),
.phv_valid (cam_phv_out_valid_d1),
.match_addr (cam_match_addr_out_d1),
.if_match (cam_if_match_d1),
.ready_out (lke_ram_ready),
//
.action (action),
.action_valid (action_valid),
.phv_out (phv_out),
.ready_in (ready_in),
//
.act_vlan_out (act_vlan_out),
.act_vlan_out_valid (act_vlan_valid_out),
.act_vlan_ready (act_vlan_ready),
.c_s_axis_tdata (c_s_axis_tdata_0),
.c_s_axis_tuser (c_s_axis_tuser_0),
.c_s_axis_tkeep (c_s_axis_tkeep_0),
.c_s_axis_tvalid (c_s_axis_tvalid_0),
.c_s_axis_tlast (c_s_axis_tlast_0),
.c_m_axis_tdata (c_m_axis_tdata),
.c_m_axis_tuser (c_m_axis_tuser),
.c_m_axis_tkeep (c_m_axis_tkeep),
.c_m_axis_tvalid (c_m_axis_tvalid),
.c_m_axis_tlast (c_m_axis_tlast)
);
endmodule
sims/net/menshen/rtl/output_arbiter.v 0 → 100644
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