Commit b6f51d1a authored by Antoine Kaufmann's avatar Antoine Kaufmann
Browse files

experiments: add support for netmem and memnic (WIP)

This should probably never make it's way into main. It's a horrible mess in
terms of the class hierarchy.
parent 53e7044d
...@@ -25,7 +25,8 @@ import typing as tp ...@@ -25,7 +25,8 @@ import typing as tp
from simbricks.orchestration.proxy import NetProxyConnecter, NetProxyListener from simbricks.orchestration.proxy import NetProxyConnecter, NetProxyListener
from simbricks.orchestration.simulators import ( from simbricks.orchestration.simulators import (
HostSim, I40eMultiNIC, NetSim, NICSim, PCIDevSim, MemDevSim, Simulator HostSim, I40eMultiNIC, NetSim, NICSim, PCIDevSim, MemDevSim, NetMemSim,
Simulator
) )
...@@ -86,6 +87,9 @@ class Experiment(object): ...@@ -86,6 +87,9 @@ class Experiment(object):
raise Exception('Duplicate memdev name') raise Exception('Duplicate memdev name')
self.memdevs.append(sim) self.memdevs.append(sim)
def add_netmem(self, sim: NetMemSim):
self.memdevs.append(sim)
def add_network(self, sim: NetSim): def add_network(self, sim: NetSim):
for n in self.networks: for n in self.networks:
if n.name == sim.name: if n.name == sim.name:
......
...@@ -198,7 +198,8 @@ class NetSim(Simulator): ...@@ -198,7 +198,8 @@ class NetSim(Simulator):
return [s for (_, s) in self.listen_sockets(env)] return [s for (_, s) in self.listen_sockets(env)]
class MemDevSim(Simulator): # FIXME: Class hierarchy is broken here as an ugly hack
class MemDevSim(NICSim):
"""Base class for memory device simulators.""" """Base class for memory device simulators."""
def __init__(self): def __init__(self):
super().__init__() super().__init__()
...@@ -221,6 +222,27 @@ class MemDevSim(Simulator): ...@@ -221,6 +222,27 @@ class MemDevSim(Simulator):
def sockets_wait(self, env): def sockets_wait(self, env):
return [env.dev_mem_path(self)] return [env.dev_mem_path(self)]
class NetMemSim(NICSim):
"""Base class for netork memory simulators."""
def __init__(self):
super().__init__()
self.name = ''
self.sync_mode = 0
self.start_tick = 0
self.sync_period = 500
self.eth_latency = 500
def full_name(self):
return 'netmem.' + self.name
def sockets_cleanup(self, env):
return [env.nic_eth_path(self), env.dev_shm_path(self)]
def sockets_wait(self, env):
return [env.nic_eth_path(self)]
class HostSim(Simulator): class HostSim(Simulator):
"""Base class for host simulators.""" """Base class for host simulators."""
...@@ -676,3 +698,32 @@ class BasicMemDev(MemDevSim): ...@@ -676,3 +698,32 @@ class BasicMemDev(MemDevSim):
f' {self.mem_latency}' f' {self.mem_latency}'
) )
return cmd return cmd
class MemNIC(MemDevSim):
def run_cmd(self, env):
cmd = (
f'{env.repodir}/sims/mem/memnic/memnic'
f' {env.dev_mem_path(self)} {env.nic_eth_path(self)}'
f' {env.dev_shm_path(self)}'
f' {self.sync_mode} {self.start_tick} {self.sync_period}'
f' {self.mem_latency} {self.eth_latency}'
)
return cmd
def sockets_cleanup(self, env):
return super().sockets_cleanup(env) + [env.nic_eth_path(self)]
def sockets_wait(self, env):
return super().sockets_wait(env) + [env.nic_eth_path(self)]
class NetMem(NetMemSim):
def run_cmd(self, env):
cmd = (
f'{env.repodir}/sims/mem/netmem/netmem'
f' {env.nic_eth_path(self)} {env.dev_shm_path(self)}'
f' {self.sync_mode} {self.start_tick} {self.sync_period}'
f' {self.eth_latency}'
)
return cmd
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