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Commit 90dfce58 authored by Hejing Li's avatar Hejing Li
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sync mode experiment data add

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{"exp_name": "modetcp-1-gt-cv-switch-1", "metadata": {}, "start_time": 1607541231.100774, "end_time": 1607571668.3146589, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.server.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9410462784", " m_axis_ctrl_dma_read_desc_ram_addr = 2688", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 21", " m_axis_ctrl_dma_write_desc_dma_addr = 9516095328", " m_axis_ctrl_dma_write_desc_ram_addr = 192", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 6", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 14", " m_axis_data_dma_write_desc_dma_addr = 9390698496", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 10", " s_axil_rdata = 2147483665", " m_axil_csr_awaddr = 7340588", " m_axil_csr_wdata = 2147483665", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7340588", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19502628504000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.client.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9502396736", " m_axis_ctrl_dma_read_desc_ram_addr = 2816", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 22", " m_axis_ctrl_dma_write_desc_dma_addr = 9515166240", " m_axis_ctrl_dma_write_desc_ram_addr = 736", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 23", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 29", " m_axis_data_dma_write_desc_dma_addr = 8542150656", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 10", " s_axil_rdata = 2147483651", " m_axil_csr_awaddr = 4194412", " m_axil_csr_wdata = 2147483651", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4194412", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19502627988000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "1", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.eth.client.0."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65302", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 2014514851627", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.879917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.880917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.880917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.880917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.880917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.880917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.880917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.880917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.880917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.880917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.880917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.880917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.880917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.881917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.881917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.881917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.885916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.885916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.885916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.885916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.885916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.885916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.886916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.886916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.886916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.886916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.886916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.886916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.886916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.886916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.886916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.110882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.110882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.110882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.179871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 39476\r", "[ 5] local 10.0.0.1 port 5001 connected with 10.0.0.2 port 39474\r", "[ 5.280248] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.2 sec 832 MBytes 681 Mbits/sec\r", "[ 6] 0.0-10.3 sec 832 MBytes 679 Mbits/sec\r", "[SUM] 0.0-10.3 sec 1.62 GBytes 1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 2014514841627. Starting simulation...", "info: Entering event queue @ 2014514851627. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 2014514851950. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65303", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-1/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-1/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1951406616034", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.877919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.878919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.879919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.879919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.879919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.879919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.879919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.879919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.879919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.879919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.879919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.879919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.879919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.879919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.879919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.879919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.884918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.884918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.884918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.884918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.884918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.884918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.884918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.884918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.884918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.884918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.884918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.884918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.884918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.884918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.109884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.109884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.109884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.109884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.178874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.2 port 39476 connected with 10.0.0.1 port 5001\r", "[ 4] local 10.0.0.2 port 39474 connected with 10.0.0.1 port 5001\r", "[ 4.614351] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 681 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 0.0-10.3 sec 832 MBytes 680 Mbits/sec\r", "[SUM] 0.0-10.3 sec 1.62 GBytes 1.36 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19502627973876 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1951406606034. Starting simulation...", "info: Entering event queue @ 1951406616034. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1951406616357. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}
\ No newline at end of file
results/paper_data/modetcp/modetcp-1-gt-cv-switch-4-0.json deleted 100644 → 0
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results/paper_data/modetcp/modetcp-1-gt-cv-switch-4-1.json deleted 100644 → 0
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{"exp_name": "modetcp-1-gt-cv-switch-4", "metadata": {}, "start_time": 1607541231.1271818, "end_time": 1607600227.3188741, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9396604944", " m_axis_ctrl_dma_read_desc_ram_addr = 2688", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 21", " m_axis_ctrl_dma_write_desc_dma_addr = 9516116704", " m_axis_ctrl_dma_write_desc_ram_addr = 672", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 21", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 9", " m_axis_data_dma_write_desc_dma_addr = 8364748800", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 1", " s_axil_rdata = 2147483667", " m_axil_csr_awaddr = 7347820", " m_axil_csr_wdata = 2147483667", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7347820", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375898504000"], "stderr": []}, "nic.server.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.1.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.1.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.1.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9407036704", " m_axis_ctrl_dma_read_desc_ram_addr = 128", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 1", " m_axis_ctrl_dma_write_desc_dma_addr = 9516265248", " m_axis_ctrl_dma_write_desc_ram_addr = 224", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 7", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 26", " m_axis_data_dma_write_desc_dma_addr = 8720973824", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 11", " s_axil_rdata = 2147483670", " m_axil_csr_awaddr = 7343820", " m_axil_csr_wdata = 2147483670", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7343820", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375898504000"], "stderr": []}, "nic.server.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.2.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.2.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.2.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9400240592", " m_axis_ctrl_dma_read_desc_ram_addr = 2560", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 20", " m_axis_ctrl_dma_write_desc_dma_addr = 9516087616", " m_axis_ctrl_dma_write_desc_ram_addr = 256", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 8", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 3", " m_axis_data_dma_write_desc_dma_addr = 8774291456", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 1", " s_axil_rdata = 2147483667", " m_axil_csr_awaddr = 7344748", " m_axil_csr_wdata = 2147483667", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7344748", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375898504000"], "stderr": []}, "nic.server.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.3.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.3.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.3.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9397024048", " m_axis_ctrl_dma_read_desc_ram_addr = 1920", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 15", " m_axis_ctrl_dma_write_desc_dma_addr = 9516375744", " m_axis_ctrl_dma_write_desc_ram_addr = 896", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 28", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 15", " m_axis_data_dma_write_desc_dma_addr = 8331083776", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 13", " s_axil_rdata = 2147483675", " m_axil_csr_awaddr = 7348076", " m_axil_csr_wdata = 2147483675", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7348076", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375898504000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.0.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9495003264", " m_axis_ctrl_dma_read_desc_ram_addr = 2816", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 22", " m_axis_ctrl_dma_write_desc_dma_addr = 9516512608", " m_axis_ctrl_dma_write_desc_ram_addr = 864", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 27", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 2", " m_axis_data_dma_write_desc_dma_addr = 8592035840", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 22", " s_axil_rdata = 2147483679", " m_axil_csr_awaddr = 4195308", " m_axil_csr_wdata = 2147483679", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4195308", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375898504000"], "stderr": []}, "nic.client.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.1.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.1.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.1.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9448387776", " m_axis_ctrl_dma_read_desc_ram_addr = 256", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 2", " m_axis_ctrl_dma_write_desc_dma_addr = 9515903936", " m_axis_ctrl_dma_write_desc_ram_addr = 544", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 17", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_write_desc_dma_addr = 9162182656", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 24", " s_axil_rdata = 2147483658", " m_axil_csr_awaddr = 4199756", " m_axil_csr_wdata = 2147483658", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4199756", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375898504000"], "stderr": []}, "nic.client.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.2.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.2.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.2.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9468192640", " m_axis_ctrl_dma_read_desc_ram_addr = 2688", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 21", " m_axis_ctrl_dma_write_desc_dma_addr = 9515156032", " m_axis_ctrl_dma_write_desc_ram_addr = 512", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 16", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 10", " m_axis_data_dma_write_desc_dma_addr = 8492613632", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 21", " s_axil_rdata = 2147483654", " m_axil_csr_awaddr = 4197580", " m_axil_csr_wdata = 2147483654", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4197580", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375898504000"], "stderr": []}, "nic.client.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.3.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.3.", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.3.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9481737472", " m_axis_ctrl_dma_read_desc_ram_addr = 2048", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 16", " m_axis_ctrl_dma_write_desc_dma_addr = 9515086560", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 7", " m_axis_data_dma_write_desc_dma_addr = 8391131136", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 4", " s_axil_rdata = 2147483652", " m_axil_csr_awaddr = 4196492", " m_axil_csr_wdata = 2147483652", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4196492", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19375897612000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "1", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.1.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.2.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.server.3.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.0.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.1.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.2.", "-s", "/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.eth.client.3."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65305", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 2049990278023", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.887916] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.889916] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.889916] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.889916] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.889916] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.889916] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.889916] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.889916] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.889916] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.889916] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.889916] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.889916] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.889916] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.889916] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.890915] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.890915] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.895915] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.895915] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.895915] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.895915] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.895915] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.895915] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.895915] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.895915] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.895915] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.895915] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.895915] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.896915] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.896915] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.896915] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.896915] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.896915] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.896915] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.120880] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.120880] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.120880] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.120880] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.120880] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.120880] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.120880] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.189870] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 45778\r", "[ 6] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 45780\r", "[ 5.381233] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.0 sec 832 MBytes 696 Mbits/sec\r", "[ 6] 0.0-10.1 sec 832 MBytes 690 Mbits/sec\r", "[SUM] 0.0-10.1 sec 1.62 GBytes 1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 2049990268023. Starting simulation...", "info: Entering event queue @ 2049990278023. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 2049990278346. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.1.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.1.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65306", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.1. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.1. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1955982967435", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.870919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.872918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.872918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.872918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.872918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.872918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.872918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.872918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.872918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.872918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.872918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.872918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.872918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.872918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.873918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.873918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.878917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.878917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.878917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.878917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.878917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.878917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.878917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.878917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.878917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.878917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.878917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.878917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.878917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.878917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.879917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.879917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.103883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.103883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.103883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.103883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.173873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 34922\r", "[ 5] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 34920\r", "[ 5.427226] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.1 sec 832 MBytes 691 Mbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 686 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1955982957435. Starting simulation...", "info: Entering event queue @ 1955982967435. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1955982967758. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.2.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.2.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65307", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.2. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.2. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1946428809157", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.877918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.878918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.878918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.878918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.878918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.878918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.878918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.879918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.879918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.879918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.879918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.879918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.879918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.879918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.879918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.879918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.883917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.883917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.884917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.884917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.884917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.884917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.884917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.884917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.884917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.884917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.884917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.884917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.884917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.884917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.884917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.884917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.884917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.108883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.108883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.108883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.109883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.109883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.109883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.109883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.178872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.3/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 49422\r", "[ 6] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 49424\r", "[ 5.451223] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.1 sec 832 MBytes 690 Mbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 684 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1946428799157. Starting simulation...", "info: Entering event queue @ 1946428809157. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1946428817472. Starting simulation...", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.3.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.3.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65308", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.server.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.server.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.server.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.server.3. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.server.3. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1919614359448", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.856920] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.857920] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.857920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.857920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.857920] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.857920] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.857920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.857920] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.857920] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.857920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.858919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.858919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.858919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.858919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.858919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.858919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.862919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.862919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.862919] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.862919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.862919] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.863919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.863919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.863919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.863919] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.863919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.863919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.863919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.863919] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.863919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.863919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.863919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.863919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.087885] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.087885] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.087885] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.087885] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.087885] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.087885] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.088884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.157874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.4/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 53884\r", "[ 5] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 53882\r", "[ 5.332240] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.1 sec 832 MBytes 692 Mbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1919614349448. Starting simulation...", "info: Entering event queue @ 1919614359448. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1919614359771. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65309", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1956792032560", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.876917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.878917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.878917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.878917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.878917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.878917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.878917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.878917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.878917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.878917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.878917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.878917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.878917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.879917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.879917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.884916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.884916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.884916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.884916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.884916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.884916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.884916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.884916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.884916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.884916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.884916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.885916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.885916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.885916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.885916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.885916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.109882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.109882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.109882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.109882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.109882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.109882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.109882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.178871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.5/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.5 port 45778 connected with 10.0.0.1 port 5001\r", "[ 5] local 10.0.0.5 port 45780 connected with 10.0.0.1 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.451222] random: crng init done\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 0.0-10.0 sec 832 MBytes 697 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 691 Mbits/sec\r", "[SUM] 0.0-10.1 sec 1.62 GBytes 1.38 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1956792022560. Starting simulation...", "info: Entering event queue @ 1956792032560. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1956792032883. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.1.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.1.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65310", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.1. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.1. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1984700726263", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.878917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.879917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.879917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.879917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.879917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.879917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.879917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.879917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.879917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.880917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.880917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.880917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.880917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.880917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.880917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.880917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.884916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.884916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.884916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.884916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.885916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.885916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.885916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.885916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.885916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.885916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.885916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.885916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.885916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.885916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.109882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.109882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.109882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.109882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.109882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.110882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.179872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.6/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.2 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.2, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.6 port 34922 connected with 10.0.0.2 port 5001\r", "[ 4] local 10.0.0.6 port 34920 connected with 10.0.0.2 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5.305244] random: crng init done\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 692 Mbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 687 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1984700716263. Starting simulation...", "info: Entering event queue @ 1984700726263. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1984700726586. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.2.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.2.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65311", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.2. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.2. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 2020744312930", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.876918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.878918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.878918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.878918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.878918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.878918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.878918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.878918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.878918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.878918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.878918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.878918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.878918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.878918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.879918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.879918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.883917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.883917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.883917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.883917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.883917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.883917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.883917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.883917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.883917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.883917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.883917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.883917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.883917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.884917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.884917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.884917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.884917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.108883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.108883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.108883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.108883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.108883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.108883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.108883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.177872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.7/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.3 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.3, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.7 port 49422 connected with 10.0.0.3 port 5001\r", "[ 5] local 10.0.0.7 port 49424 connected with 10.0.0.3 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.379234] random: crng init done\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 690 Mbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 2020744302930. Starting simulation...", "info: Entering event queue @ 2020744312930. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 2020744313253. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.3.", "--cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.3.", "--cosim-sync", "--cosim-sync_mode=1", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 20:13:52", "gem5 executing on spyder07, pid 65312", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/gem5-out.client.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/modetcp-1-gt-cv-switch-4/0/gem5-cp.client.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/cfg.client.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.pci.client.3. --cosim-shm=/local/var/tmp/hejingli/modetcp-1-gt-cv-switch-4/1/nic.shm.client.3. --cosim-sync --cosim-sync_mode=1 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1914941770048", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.863918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.865918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.865918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.865918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.865918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.865918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.865918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.865918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.865918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.865918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.865918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.865918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.865918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.865918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.865918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.865918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.871917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.871917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.871917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.871917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.871917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.871917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.871917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.871917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.871917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.871917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.871917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.871917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.871917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.871917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.871917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.871917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.871917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.096883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.096883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.096883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.096883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.096883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.096883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.096883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.165872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.8/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.4 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.4, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.8 port 53884 connected with 10.0.0.4 port 5001\r", "[ 4] local 10.0.0.8 port 53882 connected with 10.0.0.4 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.302244] random: crng init done\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 692 Mbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19375897472901 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1914941760048. Starting simulation...", "info: Entering event queue @ 1914941770048. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1914941770371. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}
\ No newline at end of file
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