result: netperf microbenchmark gt-cv-sw data update

results/paper_data/netperf/netperf-gem5-switch-cd_verilator-1.json

+{"exp_name": "netperf-gem5-switch-cd_verilator", "metadata": {}, "start_time": 1607340318.3586326, "end_time": 1607387568.517588, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.pci.server.0.", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.eth.server.0.", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.shm.server.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9400565888", "    m_axis_ctrl_dma_read_desc_ram_addr = 512", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 4", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516286208", "    m_axis_ctrl_dma_write_desc_ram_addr = 320", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 10", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 18", "    m_axis_data_dma_write_desc_dma_addr = 8744402944", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 11", "    s_axil_rdata = 2147483674", "    m_axil_csr_awaddr = 7344972", "    m_axil_csr_wdata = 2147483674", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7344972", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:23768197092000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.pci.client.0.", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.eth.client.0.", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.shm.client.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9445507648", "    m_axis_ctrl_dma_read_desc_ram_addr = 640", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 5", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516384512", "    m_axis_ctrl_dma_write_desc_ram_addr = 960", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 30", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 24", "    m_axis_data_dma_write_desc_dma_addr = 8828338176", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 24", "    s_axil_rdata = 2147483676", "    m_axil_csr_awaddr = 4200332", "    m_axil_csr_wdata = 2147483676", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4200332", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:23768196532000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "0", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.eth.client.0."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/netperf-gem5-switch-cd_verilator/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  7 2020 12:25:19", "gem5 executing on spyder04, pid 36554", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/netperf-gem5-switch-cd_verilator/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1995769235341", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.865918] mqnic: loading out-of-tree module taints kernel.\r", "[    0.866918] mqnic 0000:00:02.0: mqnic probe\r", "[    0.866918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.866918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.866918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.866918] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.866918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.866918] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.866918] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.866918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.866918] mqnic 0000:00:02.0: IF count: 1\r", "[    0.866918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.866918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.867918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.867918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.867918] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.871917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.871917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.871917] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.871917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.871917] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.871917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.871917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.872917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.872917] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.872917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.872917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.872917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.872917] mqnic 0000:00:02.0: Port count: 1\r", "[    0.872917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.872917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.872917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.872917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.096883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.096883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.096883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.096883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.096883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.096883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.096883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.165872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ netserver\r", "Starting netserver with host 'IN(6)ADDR_ANY' port '12865' and family AF_UNSPEC\r", "+ sleep infinity\r", "[    3.240557] random: crng init done\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1995769225341.  Starting simulation...", "info: Entering event queue @ 1995769235341.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1995769235664.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14", "warn: MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/netperf-gem5-switch-cd_verilator/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  7 2020 12:25:19", "gem5 executing on spyder04, pid 36555", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/netperf-gem5-switch-cd_verilator/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/netperf-gem5-switch-cd_verilator/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 2115850938769", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.894915] mqnic: loading out-of-tree module taints kernel.\r", "[    0.895915] mqnic 0000:00:02.0: mqnic probe\r", "[    0.895915] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.895915] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.895915] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.895915] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.895915] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.895915] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.895915] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.895915] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.895915] mqnic 0000:00:02.0: IF count: 1\r", "[    0.895915] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.895915] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.896915] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.896915] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.896915] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.900915] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.900915] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.900915] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.900915] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.900915] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.900915] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.900915] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.900915] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.901914] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.901914] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.901914] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.901914] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.901914] mqnic 0000:00:02.0: Port count: 1\r", "[    0.901914] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.901914] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.901914] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.901914] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.125880] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.125880] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.125880] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.125880] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.125880] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.125880] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.125880] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.195870] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ netserver\r", "Starting netserver with host 'IN(6)ADDR_ANY' port '12865' and family AF_UNSPEC\r", "+ sleep 0.5\r", "+ netperf -H 10.0.0.1\r", "[    2.533666] random: netperf: uninitialized urandom read (4096 bytes read)\r", "MIGRATED TCP STREAM TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 10.0.0.1 () port 0 AF_INET : demo\r", "[    3.133575] random: crng init done\r", "Recv   Send    Send                          \r", "Socket Socket  Message  Elapsed              \r", "Size   Size    Size     Time     Throughput  \r", "bytes  bytes   bytes    secs.    10^6bits/sec  \r", "\r", "131072  16384  16384    10.00     537.78   \r", "+ netperf -H 10.0.0.1 -t TCP_RR -- -o mean_latency,p50_latency,p90_latency,p99_latency\r", "MIGRATED TCP REQUEST/RESPONSE TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 10.0.0.1 () port 0 AF_INET : demo : first burst 0\r", "Mean Latency Microseconds,50th Percentile Latency Microseconds,90th Percentile Latency Microseconds,99th Percentile Latency Microseconds\r", "168.27,-2147483648,1029,1093\r", "+ m5 exit\r", "Exiting @ tick 23768196384627 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 2115850928769.  Starting simulation...", "info: Entering event queue @ 2115850938769.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 2115850939092.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14", "warn: MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!"]}}, "success": true}
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