add corundum and verilator build files

corundum/Makefile

+CXXFLAGS = -Wall
+
+VERILATOR = verilator
+VFLAGS = +1364-2005ext+v \
+    -Wno-WIDTH -Wno-PINMISSING -Wno-LITENDIAN -Wno-IMPLICIT -Wno-SELRANGE \
+    -Wno-CASEINCOMPLETE -Wno-UNSIGNED
+
+SRCS = corundum_verilator.cpp
+
+all: corundum_verilator
+
+obj_dir/Vinterface.cpp: rtl/interface.v
+	$(VERILATOR) $(VFLAGS) --cc \
+	    -y rtl \
+	    -y lib/axi/rtl \
+	    -y lib/eth/lib/axis/rtl/ \
+	    -y ./lib/pcie/rtl \
+	    rtl/interface.v --exe $(SRCS)
+
+obj_dir/Vinterface: obj_dir/Vinterface.cpp $(SRCS)
+	 $(MAKE) -C obj_dir -f Vinterface.mk
+
+corundum_verilator: obj_dir/Vinterface
+	cp $< $@
+
+#obj_dir/%.o: CXXFLAGS += -Wno-all
+#obj_dir/%.o: CPPFLAGS += -I /usr/share/verilator/include/
+#
+#obj_dir/verilated.o: /usr/share/verilator/include/verilated.cpp
+#	$(CXX) $(CXXFLAGS) -c $< -o $@
+#
+#obj_dir/verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp
+#	$(CXX) $(CXXFLAGS) -c $< -o $@
+#
+#corundum_verilator: corundum_verilator.o obj_dir/verilated.o \
+#	    obj_dir/verilated_vcd_c.o obj_dir/Vinterface.o \
+#	    obj_dir/Vinterface__Syms.o obj_dir/Vinterface__Trace.o \
+#	    obj_dir/Vinterface__Trace__Slow.o
+#	$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ $(LDLIBS)
+
+clean:
+	rm -rf obj_dir corundum_verilator *.o
+
+.PHONY: all clean

corundum/README.md

+Commit `d0c9a83752cde7715787aa31a5bb951fc808e0cc` from https://github.com/ucsdsysnet/corundum.

corundum/corundum_verilator.cpp

+#include <iostream>
+
+#include "Vinterface.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+static uint64_t main_time = 0;
+
+double sc_time_stamp()
+{
+    return main_time;
+}
+
+int main(int argc, char *argv[])
+{
+    Verilated::commandArgs(argc, argv);
+    Vinterface *top = new Vinterface;
+
+    top->final();
+    delete top;
+    return 0;
+}

corundum/lib/axi/.gitignore

+*~
+*.lxt
+*.pyc
+*.vvp
+*.kate-swp
+

corundum/lib/axi/AUTHORS

+Alex Forencich <alex@alexforencich.com>

corundum/lib/axi/COPYING

+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

corundum/lib/axi/README

+README.md
\ No newline at end of file

corundum/lib/axi/README.md

+# Verilog AXI Components Readme
+
+For more information and updates: http://alexforencich.com/wiki/en/verilog/axi/start
+
+GitHub repository: https://github.com/alexforencich/verilog-axi
+
+## Introduction
+
+Collection of AXI4 and AXI4 lite bus components.  Most components are fully
+parametrizable in interface widths.  Includes full MyHDL testbench with
+intelligent bus cosimulation endpoints.
+
+## Documentation
+
+### axi_adapter module
+
+AXI width adapter module with parametrizable data and address interface widths.
+Supports INCR burst types and narrow bursts.  Wrapper for axi_adapter_rd and axi_adapter_wr.
+
+### axi_adapter_rd module
+
+AXI width adapter module with parametrizable data and address interface widths.
+Supports INCR burst types and narrow bursts.
+
+### axi_adapter_wr module
+
+AXI width adapter module with parametrizable data and address interface widths.
+Supports INCR burst types and narrow bursts.
+
+### axi_axil_adapter module
+
+AXI to AXI lite converter and width adapter module with parametrizable data
+and address interface widths.  Supports INCR burst types and narrow bursts.
+Wrapper for axi_axil_adapter_rd and axi_axil_adapter_wr.
+
+### axi_axil_adapter_rd module
+
+AXI to AXI lite converter and width adapter module with parametrizable data
+and address interface widths.  Supports INCR burst types and narrow bursts.
+
+### axi_axil_adapter_wr module
+
+AXI to AXI lite converter and width adapter module with parametrizable data
+and address interface widths.  Supports INCR burst types and narrow bursts.
+
+### axi_cdma module
+
+AXI to AXI DMA engine with parametrizable data and address interface widths.
+Generates full-width INCR bursts only, with parametrizable maximum burst
+length.  Supports unaligned transfers, which can be disabled via parameter
+to save on resource consumption.
+
+### axi_cdma_desc_mux module
+
+Descriptor multiplexer/demultiplexer for AXI CDMA module.  Enables sharing the
+AXI CDMA module between multiple request sources, interleaving requests and
+distributing responses.
+
+### axi_crossbar module
+
+AXI nonblocking crossbar interconnect with parametrizable data and address
+interface widths and master and slave interface counts.  Supports all burst
+types.  Fully nonblocking with completely separate read and write paths; ID
+based transaction ordering protection logic; and per-port address decode,
+admission control, and decode error handling.  Wrapper for axi_crossbar_rd and
+axi_crossbar_wr.  
+
+### axi_crossbar_addr module
+
+Address decode and admission control module for AXI nonblocking crossbar interconnect.
+
+### axi_crossbar_rd module
+
+AXI nonblocking crossbar interconnect with parametrizable data and address
+interface widths and master and slave interface counts.  Read interface only.
+Supports all burst types.  Fully nonblocking with completely separate read and
+write paths; ID based transaction ordering protection logic; and per-port
+address decode, admission control, and decode error handling.
+
+### axi_crossbar_wr module
+
+AXI nonblocking crossbar interconnect with parametrizable data and address
+interface widths and master and slave interface counts.  Write interface only.
+Supports all burst types.  Fully nonblocking with completely separate read and
+write paths; ID based transaction ordering protection logic; and per-port
+address decode, admission control, and decode error handling.
+
+### axi_dma module
+
+AXI to AXI stream DMA engine with parametrizable data and address interface
+widths.  Generates full-width INCR bursts only, with parametrizable maximum
+burst length.  Supports unaligned transfers, which can be disabled via
+parameter to save on resource consumption.  Wrapper for axi_dma_rd and
+axi_dma_wr.
+
+### axi_dma_desc_mux module
+
+Descriptor multiplexer/demultiplexer for AXI DMA module.  Enables sharing the
+AXI DMA module between multiple request sources, interleaving requests and
+distributing responses.
+
+### axi_dma_rd module
+
+AXI to AXI stream DMA engine with parametrizable data and address interface
+widths.  Generates full-width INCR bursts only, with parametrizable maximum
+burst length.  Supports unaligned transfers, which can be disabled via
+parameter to save on resource consumption.
+
+### axi_dma_wr module
+
+AXI stream to AXI DMA engine with parametrizable data and address interface
+widths.  Generates full-width INCR bursts only, with parametrizable maximum
+burst length.  Supports unaligned transfers, which can be disabled via
+parameter to save on resource consumption.
+
+### axi_fifo module
+
+AXI FIFO with parametrizable data and address interface widths.  Supports all
+burst types.  Optionally can delay the address channel until either the write
+data is completely shifted into the FIFO or the read data FIFO has enough
+capacity to fit the whole burst.  Wrapper for axi_fifo_rd and axi_fifo_wr.
+
+### axi_fifo_rd module
+
+AXI FIFO with parametrizable data and address interface widths.  AR and R
+channels only.  Supports all burst types.  Optionally can delay the address
+channel until either the read data FIFO is empty or has enough capacity to fit
+the whole burst.
+
+### axi_fifo_wr module
+
+AXI FIFO with parametrizable data and address interface widths.  WR, W, and B
+channels only.  Supports all burst types.  Optionally can delay the address
+channel until the write data is shifted completely into the write data FIFO,
+or the current burst completely fills the write data FIFO.
+
+### axi_interconnect module
+
+AXI shared interconnect with parametrizable data and address interface
+widths and master and slave interface counts.  Supports all burst types.
+Small in area, but does not support concurrent operations.
+
+### axi_ram module
+
+AXI RAM with parametrizable data and address interface widths. Supports FIXED
+and INCR burst types as well as narrow bursts.
+
+### axi_register module
+
+AXI register with parametrizable data and address interface widths.  Supports
+all burst types.  Inserts simple buffers or skid buffers into all channels.
+Channel register types can be individually changed or bypassed.  Wrapper for
+axi_register_rd and axi_register_wr.
+
+### axi_register_rd module
+
+AXI register with parametrizable data and address interface widths.  AR and R
+channels only.  Supports all burst types.  Inserts simple buffers or skid
+buffers into all channels.  Channel register types can be individually changed
+or bypassed.
+
+### axi_register_wr module
+
+AXI register with parametrizable data and address interface widths.  WR, W,
+and B channels only.  Supports all burst types.  Inserts simple buffers or
+skid buffers into all channels.  Channel register types can be individually
+changed or bypassed.
+
+### axil_adapter module
+
+AXI lite width adapter module with parametrizable data and address interface
+widths.  Wrapper for axi_adapter_rd and axi_adapter_wr.
+
+### axil_adapter_rd module
+
+AXI lite width adapter module with parametrizable data and address interface
+widths.
+
+### axil_adapter_wr module
+
+AXI lite width adapter module with parametrizable data and address interface
+widths.
+
+### axil_cdc module
+
+AXI lite clock domain crossing module with parametrizable data and address
+interface widths.  Wrapper for axi_cdc_rd and axi_cdc_wr.
+
+### axil_cdc_rd module
+
+AXI lite clock domain crossing module with parametrizable data and address
+interface widths.
+
+### axil_cdc_wr module
+
+AXI lite clock domain crossing module with parametrizable data and address
+interface widths.
+
+### axil_interconnect module
+
+AXI lite shared interconnect with parametrizable data and address interface
+widths and master and slave interface counts.  Small in area, but does not
+support concurrent operations.
+
+### axil_ram module
+
+AXI lite RAM with parametrizable data and address interface widths.
+
+### axil_register module
+
+AXI lite register with parametrizable data and address interface widths.
+Inserts skid buffers into all channels.  Channel registers can be individually
+bypassed.  Wrapper for axil_register_rd and axil_register_wr.
+
+### axil_register_rd module
+
+AXI lite register with parametrizable data and address interface widths.  AR
+and R channels only.  Inserts simple buffers into all channels.  Channel
+registers can be individually bypassed.
+
+### axil_register_wr module
+
+AXI lite register with parametrizable data and address interface widths.  WR,
+W, and B channels only.  Inserts simple buffers into all channels.  Channel
+registers can be individually bypassed.
+
+### Common signals
+
+    awid     : Write address ID
+    awaddr   : Write address
+    awlen    : Write burst length
+    awsize   : Write burst size
+    awburst  : Write burst type
+    awlock   : Write locking
+    awcache  : Write cache handling
+    awprot   : Write protection level
+    awqos    : Write QoS setting
+    awregion : Write region
+    awuser   : Write user sideband signal
+    awvalid  : Write address valid
+    awready  : Write address ready (from slave)
+    wdata    : Write data
+    wstrb    : Write data strobe (byte select)
+    wlast    : Write data last transfer in burst
+    wuser    : Write data user sideband signal
+    wvalid   : Write data valid
+    wready   : Write data ready (from slave)
+    bid      : Write response ID
+    bresp    : Write response
+    buser    : Write response user sideband signal
+    bvalid   : Write response valid
+    bready   : Write response ready (from master)
+    arid     : Read address ID
+    araddr   : Read address
+    arlen    : Read burst length
+    arsize   : Read burst size
+    arburst  : Read burst type
+    arlock   : Read locking
+    arcache  : Read cache handling
+    arprot   : Read protection level
+    arqos    : Read QoS setting
+    arregion : Read region
+    aruser   : Read user sideband signal
+    arvalid  : Read address valid
+    arready  : Read address ready (from slave)
+    rid      : Read data ID
+    rdata    : Read data
+    rresp    : Read response
+    rlast    : Read data last transfer in burst
+    ruser    : Read data user sideband signal
+    rvalid   : Read response valid
+    rready   : Read response ready (from master)
+
+### Common parameters
+
+    ADDR_WIDTH           : width of awaddr and araddr signals
+    DATA_WIDTH           : width of wdata and rdata signals
+    STRB_WIDTH           : width of wstrb signal
+    ID_WIDTH             : width of *id signals
+    AWUSER_ENABLE        : enable awuser signal
+    AWUSER_WIDTH         : width of awuser signal
+    WUSER_ENABLE         : enable wuser signal
+    WUSER_WIDTH          : width of wuser signal
+    BUSER_ENABLE         : enable buser signal
+    BUSER_WIDTH          : width of buser signal
+    ARUSER_ENABLE        : enable aruser signal
+    ARUSER_WIDTH         : width of aruser signal
+    RUSER_ENABLE         : enable ruser signal
+    RUSER_WIDTH          : width of ruser signal
+
+### Source Files
+
+    rtl/arbiter.v                   : Parametrizable arbiter
+    rtl/axi_adapter.v               : AXI lite width converter
+    rtl/axi_adapter_rd.v            : AXI lite width converter (read)
+    rtl/axi_adapter_wr.v            : AXI lite width converter (write)
+    rtl/axi_axil_adapter.v          : AXI to AXI lite converter
+    rtl/axi_axil_adapter_rd.v       : AXI to AXI lite converter (read)
+    rtl/axi_axil_adapter_wr.v       : AXI to AXI lite converter (write)
+    rtl/axi_cdma.v                  : AXI central DMA engine
+    rtl/axi_cdma_desc_mux.v         : AXI CDMA descriptor mux
+    rtl/axi_crossbar.v              : AXI nonblocking crossbar interconnect
+    rtl/axi_crossbar_addr.v         : AXI crossbar address module
+    rtl/axi_crossbar_rd.v           : AXI crossbar read module
+    rtl/axi_crossbar_wr.v           : AXI crossbar write module
+    rtl/axi_dma.v                   : AXI DMA engine
+    rtl/axi_dma_desc_mux.v          : AXI DMA descriptor mux
+    rtl/axi_dma_rd.v                : AXI DMA engine (read)
+    rtl/axi_dma_wr.v                : AXI DMA engine (write)
+    rtl/axi_fifo.v                  : AXI FIFO
+    rtl/axi_fifo_rd.v               : AXI FIFO (read)
+    rtl/axi_fifo_wr.v               : AXI FIFO (write)
+    rtl/axi_interconnect.v          : AXI shared interconnect
+    rtl/axi_ram.v                   : AXI RAM
+    rtl/axi_register.v              : AXI register
+    rtl/axi_register_rd.v           : AXI register (read)
+    rtl/axi_register_wr.v           : AXI register (write)
+    rtl/axil_adapter.v              : AXI lite width converter
+    rtl/axil_adapter_rd.v           : AXI lite width converter (read)
+    rtl/axil_adapter_wr.v           : AXI lite width converter (write)
+    rtl/axil_cdc.v                  : AXI lite CDC
+    rtl/axil_cdc_rd.v               : AXI lite CDC (read)
+    rtl/axil_cdc_wr.v               : AXI lite CDC (write)
+    rtl/axil_interconnect.v         : AXI lite shared interconnect
+    rtl/axil_ram.v                  : AXI lite RAM
+    rtl/axil_register.v             : AXI lite register
+    rtl/axil_register_rd.v          : AXI lite register (read)
+    rtl/axil_register_wr.v          : AXI lite register (write)
+    rtl/priority_encoder.v          : Parametrizable priority encoder
+
+### AXI4-Lite Interface Example
+
+Write
+
+                ___     ___     ___     ___     ___    
+    clk     ___/   \___/   \___/   \___/   \___/   \___
+                _______
+    awid    XXXX_ID____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awaddr  XXXX_ADDR__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awlen   XXXX_00____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awsize  XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awburst XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awprot  XXXX_PROT__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awvalid ___/       \_______________________________
+            ___________         _______________________
+    awready            \_______/
+                _______________
+    wdata   XXXX_DATA__________XXXXXXXXXXXXXXXXXXXXXXXX
+                _______________
+    wstrb   XXXX_STRB__________XXXXXXXXXXXXXXXXXXXXXXXX
+                _______________
+    wvalid  ___/               \_______________________
+                        _______
+    wready  ___________/       \_______________________
+                                        _______
+    bid     XXXXXXXXXXXXXXXXXXXXXXXXXXXX_ID____XXXXXXXX
+                                        _______
+    bresp   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_RESP__XXXXXXXX
+                                        _______
+    bvalid  ___________________________/       \_______
+            ___________________________________________
+    bready
+
+
+Read
+
+                ___     ___     ___     ___     ___    
+    clk     ___/   \___/   \___/   \___/   \___/   \___
+                _______
+    arid    XXXX_ID____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    araddr  XXXX_ADDR__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arlen   XXXX_00____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arsize  XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arburst XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arprot  XXXX_PROT__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arvalid ___/       \_______________________________
+            ___________________________________________
+    arready
+                                        _______
+    rid     XXXXXXXXXXXXXXXXXXXXXXXXXXXX_ID____XXXXXXXX
+                                        _______
+    rdata   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_DATA__XXXXXXXX
+                                        _______
+    rresp   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_RESP__XXXXXXXX
+                                        _______
+    rvalid  ___________________________/       \_______
+            ___________________________________________
+    rready
+
+
+## Testing
+
+Running the included testbenches requires MyHDL and Icarus Verilog.  Make sure
+that myhdl.vpi is installed properly for cosimulation to work correctly.  The
+testbenches can be run with a Python test runner like nose or py.test, or the
+individual test scripts can be run with python directly.
+
+### Testbench Files
+
+    tb/axi.py            : MyHDL AXI4 master and memory BFM
+    tb/axil.py           : MyHDL AXI4 lite master and memory BFM

corundum/lib/axi/rtl/arbiter.v

+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Arbiter module
+ */
+module arbiter #
+(
+    parameter PORTS = 4,
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter TYPE = "PRIORITY",
+    // block type: "NONE", "REQUEST", "ACKNOWLEDGE"
+    parameter BLOCK = "NONE",
+    // LSB priority: "LOW", "HIGH"
+    parameter LSB_PRIORITY = "LOW"
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    input  wire [PORTS-1:0]         request,
+    input  wire [PORTS-1:0]         acknowledge,
+
+    output wire [PORTS-1:0]         grant,
+    output wire                     grant_valid,
+    output wire [$clog2(PORTS)-1:0] grant_encoded
+);
+
+reg [PORTS-1:0] grant_reg = 0, grant_next;
+reg grant_valid_reg = 0, grant_valid_next;
+reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
+
+assign grant_valid = grant_valid_reg;
+assign grant = grant_reg;
+assign grant_encoded = grant_encoded_reg;
+
+wire request_valid;
+wire [$clog2(PORTS)-1:0] request_index;
+wire [PORTS-1:0] request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS),
+    .LSB_PRIORITY(LSB_PRIORITY)
+)
+priority_encoder_inst (
+    .input_unencoded(request),
+    .output_valid(request_valid),
+    .output_encoded(request_index),
+    .output_unencoded(request_mask)
+);
+
+reg [PORTS-1:0] mask_reg = 0, mask_next;
+
+wire masked_request_valid;
+wire [$clog2(PORTS)-1:0] masked_request_index;
+wire [PORTS-1:0] masked_request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS),
+    .LSB_PRIORITY(LSB_PRIORITY)
+)
+priority_encoder_masked (
+    .input_unencoded(request & mask_reg),
+    .output_valid(masked_request_valid),
+    .output_encoded(masked_request_index),
+    .output_unencoded(masked_request_mask)
+);
+
+always @* begin
+    grant_next = 0;
+    grant_valid_next = 0;
+    grant_encoded_next = 0;
+    mask_next = mask_reg;
+
+    if (BLOCK == "REQUEST" && grant_reg & request) begin
+        // granted request still asserted; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
+        // granted request not yet acknowledged; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (request_valid) begin
+        if (TYPE == "PRIORITY") begin
+            grant_valid_next = 1;
+            grant_next = request_mask;
+            grant_encoded_next = request_index;
+        end else if (TYPE == "ROUND_ROBIN") begin
+            if (masked_request_valid) begin
+                grant_valid_next = 1;
+                grant_next = masked_request_mask;
+                grant_encoded_next = masked_request_index;
+                if (LSB_PRIORITY == "LOW") begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
+                end else begin
+                    mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
+                end
+            end else begin
+                grant_valid_next = 1;
+                grant_next = request_mask;
+                grant_encoded_next = request_index;
+                if (LSB_PRIORITY == "LOW") begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
+                end else begin
+                    mask_next = {PORTS{1'b1}} << (request_index + 1);
+                end
+            end
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        grant_reg <= 0;
+        grant_valid_reg <= 0;
+        grant_encoded_reg <= 0;
+        mask_reg <= 0;
+    end else begin
+        grant_reg <= grant_next;
+        grant_valid_reg <= grant_valid_next;
+        grant_encoded_reg <= grant_encoded_next;
+        mask_reg <= mask_next;
+    end
+end
+
+endmodule

corundum/lib/axi/rtl/axi_adapter.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 width adapter
+ */
+module axi_adapter #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) interface data bus in bits
+    parameter S_DATA_WIDTH = 32,
+    // Width of input (slave) interface wstrb (width of data bus in words)
+    parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
+    // Width of output (master) interface data bus in bits
+    parameter M_DATA_WIDTH = 32,
+    // Width of output (master) interface wstrb (width of data bus in words)
+    parameter M_STRB_WIDTH = (M_DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0,
+    // Forward ID through adapter
+    parameter FORWARD_ID = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [7:0]               s_axi_awlen,
+    input  wire [2:0]               s_axi_awsize,
+    input  wire [1:0]               s_axi_awburst,
+    input  wire                     s_axi_awlock,
+    input  wire [3:0]               s_axi_awcache,
+    input  wire [2:0]               s_axi_awprot,
+    input  wire [3:0]               s_axi_awqos,
+    input  wire [3:0]               s_axi_awregion,
+    input  wire [AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire                     s_axi_awvalid,
+    output wire                     s_axi_awready,
+    input  wire [S_DATA_WIDTH-1:0]  s_axi_wdata,
+    input  wire [S_STRB_WIDTH-1:0]  s_axi_wstrb,
+    input  wire                     s_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire                     s_axi_wvalid,
+    output wire                     s_axi_wready,
+    output wire [ID_WIDTH-1:0]      s_axi_bid,
+    output wire [1:0]               s_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire                     s_axi_bvalid,
+    input  wire                     s_axi_bready,
+    input  wire [ID_WIDTH-1:0]      s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [7:0]               s_axi_arlen,
+    input  wire [2:0]               s_axi_arsize,
+    input  wire [1:0]               s_axi_arburst,
+    input  wire                     s_axi_arlock,
+    input  wire [3:0]               s_axi_arcache,
+    input  wire [2:0]               s_axi_arprot,
+    input  wire [3:0]               s_axi_arqos,
+    input  wire [3:0]               s_axi_arregion,
+    input  wire [ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire                     s_axi_arvalid,
+    output wire                     s_axi_arready,
+    output wire [ID_WIDTH-1:0]      s_axi_rid,
+    output wire [S_DATA_WIDTH-1:0]  s_axi_rdata,
+    output wire [1:0]               s_axi_rresp,
+    output wire                     s_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire                     s_axi_rvalid,
+    input  wire                     s_axi_rready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_awid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [7:0]               m_axi_awlen,
+    output wire [2:0]               m_axi_awsize,
+    output wire [1:0]               m_axi_awburst,
+    output wire                     m_axi_awlock,
+    output wire [3:0]               m_axi_awcache,
+    output wire [2:0]               m_axi_awprot,
+    output wire [3:0]               m_axi_awqos,
+    output wire [3:0]               m_axi_awregion,
+    output wire [AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire                     m_axi_awvalid,
+    input  wire                     m_axi_awready,
+    output wire [M_DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [M_STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                     m_axi_wlast,
+    output wire [WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire                     m_axi_wvalid,
+    input  wire                     m_axi_wready,
+    input  wire [ID_WIDTH-1:0]      m_axi_bid,
+    input  wire [1:0]               m_axi_bresp,
+    input  wire [BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire                     m_axi_bvalid,
+    output wire                     m_axi_bready,
+    output wire [ID_WIDTH-1:0]      m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [7:0]               m_axi_arlen,
+    output wire [2:0]               m_axi_arsize,
+    output wire [1:0]               m_axi_arburst,
+    output wire                     m_axi_arlock,
+    output wire [3:0]               m_axi_arcache,
+    output wire [2:0]               m_axi_arprot,
+    output wire [3:0]               m_axi_arqos,
+    output wire [3:0]               m_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire                     m_axi_arvalid,
+    input  wire                     m_axi_arready,
+    input  wire [ID_WIDTH-1:0]      m_axi_rid,
+    input  wire [M_DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]               m_axi_rresp,
+    input  wire                     m_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire                     m_axi_rvalid,
+    output wire                     m_axi_rready
+);
+
+axi_adapter_wr #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .S_DATA_WIDTH(S_DATA_WIDTH),
+    .S_STRB_WIDTH(S_STRB_WIDTH),
+    .M_DATA_WIDTH(M_DATA_WIDTH),
+    .M_STRB_WIDTH(M_STRB_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .AWUSER_ENABLE(AWUSER_ENABLE),
+    .AWUSER_WIDTH(AWUSER_WIDTH),
+    .WUSER_ENABLE(WUSER_ENABLE),
+    .WUSER_WIDTH(WUSER_WIDTH),
+    .BUSER_ENABLE(BUSER_ENABLE),
+    .BUSER_WIDTH(BUSER_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
+    .FORWARD_ID(FORWARD_ID)
+)
+axi_adapter_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awuser(s_axi_awuser),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(s_axi_wuser),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(s_axi_buser),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*
+     * AXI master interface
+     */
+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awuser(m_axi_awuser),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(m_axi_wuser),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(m_axi_buser),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready)
+);
+
+axi_adapter_rd #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .S_DATA_WIDTH(S_DATA_WIDTH),
+    .S_STRB_WIDTH(S_STRB_WIDTH),
+    .M_DATA_WIDTH(M_DATA_WIDTH),
+    .M_STRB_WIDTH(M_STRB_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .ARUSER_ENABLE(ARUSER_ENABLE),
+    .ARUSER_WIDTH(ARUSER_WIDTH),
+    .RUSER_ENABLE(RUSER_ENABLE),
+    .RUSER_WIDTH(RUSER_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
+    .FORWARD_ID(FORWARD_ID)
+)
+axi_adapter_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_aruser(s_axi_aruser),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(s_axi_ruser),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*
+     * AXI master interface
+     */
+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_aruser(m_axi_aruser),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(m_axi_ruser),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+);
+
+endmodule

corundum/lib/axi/rtl/axi_adapter_rd.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 width adapter
+ */
+module axi_adapter_rd #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) interface data bus in bits
+    parameter S_DATA_WIDTH = 32,
+    // Width of input (slave) interface wstrb (width of data bus in words)
+    parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
+    // Width of output (master) interface data bus in bits
+    parameter M_DATA_WIDTH = 32,
+    // Width of output (master) interface wstrb (width of data bus in words)
+    parameter M_STRB_WIDTH = (M_DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0,
+    // Forward ID through adapter
+    parameter FORWARD_ID = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [7:0]               s_axi_arlen,
+    input  wire [2:0]               s_axi_arsize,
+    input  wire [1:0]               s_axi_arburst,
+    input  wire                     s_axi_arlock,
+    input  wire [3:0]               s_axi_arcache,
+    input  wire [2:0]               s_axi_arprot,
+    input  wire [3:0]               s_axi_arqos,
+    input  wire [3:0]               s_axi_arregion,
+    input  wire [ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire                     s_axi_arvalid,
+    output wire                     s_axi_arready,
+    output wire [ID_WIDTH-1:0]      s_axi_rid,
+    output wire [S_DATA_WIDTH-1:0]  s_axi_rdata,
+    output wire [1:0]               s_axi_rresp,
+    output wire                     s_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire                     s_axi_rvalid,
+    input  wire                     s_axi_rready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [7:0]               m_axi_arlen,
+    output wire [2:0]               m_axi_arsize,
+    output wire [1:0]               m_axi_arburst,
+    output wire                     m_axi_arlock,
+    output wire [3:0]               m_axi_arcache,
+    output wire [2:0]               m_axi_arprot,
+    output wire [3:0]               m_axi_arqos,
+    output wire [3:0]               m_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire                     m_axi_arvalid,
+    input  wire                     m_axi_arready,
+    input  wire [ID_WIDTH-1:0]      m_axi_rid,
+    input  wire [M_DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]               m_axi_rresp,
+    input  wire                     m_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire                     m_axi_rvalid,
+    output wire                     m_axi_rready
+);
+
+parameter S_ADDR_BIT_OFFSET = $clog2(S_STRB_WIDTH);
+parameter M_ADDR_BIT_OFFSET = $clog2(M_STRB_WIDTH);
+parameter S_WORD_WIDTH = S_STRB_WIDTH;
+parameter M_WORD_WIDTH = M_STRB_WIDTH;
+parameter S_WORD_SIZE = S_DATA_WIDTH/S_WORD_WIDTH;
+parameter M_WORD_SIZE = M_DATA_WIDTH/M_WORD_WIDTH;
+parameter S_BURST_SIZE = $clog2(S_STRB_WIDTH);
+parameter M_BURST_SIZE = $clog2(M_STRB_WIDTH);
+
+// output bus is wider
+parameter EXPAND = M_STRB_WIDTH > S_STRB_WIDTH;
+parameter DATA_WIDTH = EXPAND ? M_DATA_WIDTH : S_DATA_WIDTH;
+parameter STRB_WIDTH = EXPAND ? M_STRB_WIDTH : S_STRB_WIDTH;
+// required number of segments in wider bus
+parameter SEGMENT_COUNT = EXPAND ? (M_STRB_WIDTH / S_STRB_WIDTH) : (S_STRB_WIDTH / M_STRB_WIDTH);
+// data width and keep width per segment
+parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
+parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
+
+// bus width assertions
+initial begin
+    if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
+        $error("Error: AXI slave interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
+        $error("Error: AXI master interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (S_WORD_SIZE != M_WORD_SIZE) begin
+        $error("Error: word size mismatch (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
+        $error("Error: AXI slave interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
+        $error("Error: AXI master interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+end
+
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DATA = 2'd1,
+    STATE_DATA_READ = 2'd2,
+    STATE_DATA_SPLIT = 2'd3;
+
+reg [1:0] state_reg = STATE_IDLE, state_next;
+
+reg [ID_WIDTH-1:0] id_reg = {ID_WIDTH{1'b0}}, id_next;
+reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
+reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
+reg [1:0] resp_reg = 2'd0, resp_next;
+reg [RUSER_WIDTH-1:0] ruser_reg = {RUSER_WIDTH{1'b0}}, ruser_next;
+reg [7:0] burst_reg = 8'd0, burst_next;
+reg [2:0] burst_size_reg = 3'd0, burst_size_next;
+reg [7:0] master_burst_reg = 8'd0, master_burst_next;
+reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
+
+reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
+
+reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}}, m_axi_arid_next;
+reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}, m_axi_araddr_next;
+reg [7:0] m_axi_arlen_reg = 8'd0, m_axi_arlen_next;
+reg [2:0] m_axi_arsize_reg = 3'd0, m_axi_arsize_next;
+reg [1:0] m_axi_arburst_reg = 2'd0, m_axi_arburst_next;
+reg m_axi_arlock_reg = 1'b0, m_axi_arlock_next;
+reg [3:0] m_axi_arcache_reg = 4'd0, m_axi_arcache_next;
+reg [2:0] m_axi_arprot_reg = 3'd0, m_axi_arprot_next;
+reg [3:0] m_axi_arqos_reg = 4'd0, m_axi_arqos_next;
+reg [3:0] m_axi_arregion_reg = 4'd0, m_axi_arregion_next;
+reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}, m_axi_aruser_next;
+reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
+reg m_axi_rready_reg = 1'b0, m_axi_rready_next;
+
+// internal datapath
+reg  [ID_WIDTH-1:0]     s_axi_rid_int;
+reg  [S_DATA_WIDTH-1:0] s_axi_rdata_int;
+reg  [1:0]              s_axi_rresp_int;
+reg                     s_axi_rlast_int;
+reg  [RUSER_WIDTH-1:0]  s_axi_ruser_int;
+reg                     s_axi_rvalid_int;
+reg                     s_axi_rready_int_reg = 1'b0;
+wire                    s_axi_rready_int_early;
+
+assign s_axi_arready = s_axi_arready_reg;
+
+assign m_axi_arid = FORWARD_ID ? m_axi_arid_reg : {ID_WIDTH{1'b0}};
+assign m_axi_araddr = m_axi_araddr_reg;
+assign m_axi_arlen = m_axi_arlen_reg;
+assign m_axi_arsize = m_axi_arsize_reg;
+assign m_axi_arburst = m_axi_arburst_reg;
+assign m_axi_arlock = m_axi_arlock_reg;
+assign m_axi_arcache = m_axi_arcache_reg;
+assign m_axi_arprot = m_axi_arprot_reg;
+assign m_axi_arqos = m_axi_arqos_reg;
+assign m_axi_arregion = m_axi_arregion_reg;
+assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};
+assign m_axi_arvalid = m_axi_arvalid_reg;
+assign m_axi_rready = m_axi_rready_reg;
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    id_next = id_reg;
+    addr_next = addr_reg;
+    data_next = data_reg;
+    resp_next = resp_reg;
+    ruser_next = ruser_reg;
+    burst_next = burst_reg;
+    burst_size_next = burst_size_reg;
+    master_burst_next = master_burst_reg;
+    master_burst_size_next = master_burst_size_reg;
+
+    s_axi_arready_next = 1'b0;
+    m_axi_arid_next = m_axi_arid_reg;
+    m_axi_araddr_next = m_axi_araddr_reg;
+    m_axi_arlen_next = m_axi_arlen_reg;
+    m_axi_arsize_next = m_axi_arsize_reg;
+    m_axi_arburst_next = m_axi_arburst_reg;
+    m_axi_arlock_next = m_axi_arlock_reg;
+    m_axi_arcache_next = m_axi_arcache_reg;
+    m_axi_arprot_next = m_axi_arprot_reg;
+    m_axi_arqos_next = m_axi_arqos_reg;
+    m_axi_arregion_next = m_axi_arregion_reg;
+    m_axi_aruser_next = m_axi_aruser_reg;
+    m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_arready;
+    m_axi_rready_next = 1'b0;
+
+    if (SEGMENT_COUNT == 1) begin
+        // master output is same width; direct transfer with no splitting/merging
+        s_axi_rid_int = id_reg;
+        s_axi_rdata_int = m_axi_rdata;
+        s_axi_rresp_int = m_axi_rresp;
+        s_axi_rlast_int = m_axi_rlast;
+        s_axi_ruser_int = m_axi_ruser;
+        s_axi_rvalid_int = 0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axi_arvalid;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axi_arid_next = s_axi_arid;
+                    m_axi_araddr_next = s_axi_araddr;
+                    m_axi_arlen_next = s_axi_arlen;
+                    m_axi_arsize_next = s_axi_arsize;
+                    m_axi_arburst_next = s_axi_arburst;
+                    m_axi_arlock_next = s_axi_arlock;
+                    m_axi_arcache_next = s_axi_arcache;
+                    m_axi_arprot_next = s_axi_arprot;
+                    m_axi_arqos_next = s_axi_arqos;
+                    m_axi_arregion_next = s_axi_arregion;
+                    m_axi_aruser_next = s_axi_aruser;
+                    m_axi_arvalid_next = 1'b1;
+                    m_axi_rready_next = s_axi_rready_int_early;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer read data
+                m_axi_rready_next = s_axi_rready_int_early;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = m_axi_rdata;
+                    s_axi_rresp_int = m_axi_rresp;
+                    s_axi_rlast_int = m_axi_rlast;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b1;
+                    if (m_axi_rlast) begin
+                        // last data word, return to idle
+                        m_axi_rready_next = 1'b0;
+                        s_axi_arready_next = !m_axi_arvalid;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end else if (EXPAND) begin
+        // master output is wider; split reads
+        s_axi_rid_int = id_reg;
+        s_axi_rdata_int = m_axi_rdata;
+        s_axi_rresp_int = m_axi_rresp;
+        s_axi_rlast_int = m_axi_rlast;
+        s_axi_ruser_int = m_axi_ruser;
+        s_axi_rvalid_int = 0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axi_arvalid;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axi_arid_next = s_axi_arid;
+                    m_axi_araddr_next = s_axi_araddr;
+                    addr_next = s_axi_araddr;
+                    burst_next = s_axi_arlen;
+                    burst_size_next = s_axi_arsize;
+                    if (CONVERT_BURST && s_axi_arcache[1] && (CONVERT_NARROW_BURST || s_axi_arsize == S_BURST_SIZE)) begin
+                        // split reads
+                        // require CONVERT_BURST and arcache[1] set
+                        master_burst_size_next = M_BURST_SIZE;
+                        if (CONVERT_NARROW_BURST) begin
+                            m_axi_arlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_arlen} << s_axi_arsize) + s_axi_araddr[M_ADDR_BIT_OFFSET-1:0]) >> M_BURST_SIZE;
+                        end else begin
+                            m_axi_arlen_next = ({1'b0, s_axi_arlen} + s_axi_araddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]) >> $clog2(SEGMENT_COUNT);
+                        end
+                        m_axi_arsize_next = M_BURST_SIZE;
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        // output narrow burst
+                        master_burst_size_next = s_axi_arsize;
+                        m_axi_arlen_next = s_axi_arlen;
+                        m_axi_arsize_next = s_axi_arsize;
+                        state_next = STATE_DATA;
+                    end
+                    m_axi_arburst_next = s_axi_arburst;
+                    m_axi_arlock_next = s_axi_arlock;
+                    m_axi_arcache_next = s_axi_arcache;
+                    m_axi_arprot_next = s_axi_arprot;
+                    m_axi_arqos_next = s_axi_arqos;
+                    m_axi_arregion_next = s_axi_arregion;
+                    m_axi_aruser_next = s_axi_aruser;
+                    m_axi_arvalid_next = 1'b1;
+                    m_axi_rready_next = s_axi_rready_int_early;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_axi_rready_next = s_axi_rready_int_early;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = m_axi_rdata >> (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_WIDTH);
+                    s_axi_rresp_int = m_axi_rresp;
+                    s_axi_rlast_int = m_axi_rlast;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (m_axi_rlast) begin
+                        m_axi_rready_next = 1'b0;
+                        s_axi_arready_next = !m_axi_arvalid;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_READ: begin
+                m_axi_rready_next = s_axi_rready_int_early;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    s_axi_rid_int = id_reg;
+                    data_next = m_axi_rdata;
+                    resp_next = m_axi_rresp;
+                    ruser_next = m_axi_ruser;
+                    s_axi_rdata_int = m_axi_rdata >> (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_WIDTH);
+                    s_axi_rresp_int = m_axi_rresp;
+                    s_axi_rlast_int = 1'b0;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        m_axi_rready_next = 1'b0;
+                        s_axi_arready_next = !m_axi_arvalid;
+                        s_axi_rlast_int = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        m_axi_rready_next = 1'b0;
+                        state_next = STATE_DATA_SPLIT;
+                    end
+                end else begin
+                    state_next = STATE_DATA_READ;
+                end
+            end
+            STATE_DATA_SPLIT: begin
+                m_axi_rready_next = 1'b0;
+
+                if (s_axi_rready_int_reg) begin
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = data_reg >> (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_WIDTH);
+                    s_axi_rresp_int = resp_reg;
+                    s_axi_rlast_int = 1'b0;
+                    s_axi_ruser_int = ruser_reg;
+                    s_axi_rvalid_int = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        s_axi_arready_next = !m_axi_arvalid;
+                        s_axi_rlast_int = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        m_axi_rready_next = s_axi_rready_int_early;
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        state_next = STATE_DATA_SPLIT;
+                    end
+                end else begin
+                    state_next = STATE_DATA_SPLIT;
+                end
+            end
+        endcase
+    end else begin
+        // master output is narrower; merge reads and possibly split burst
+        s_axi_rid_int = id_reg;
+        s_axi_rdata_int = data_reg;
+        s_axi_rresp_int = resp_reg;
+        s_axi_rlast_int = 1'b0;
+        s_axi_ruser_int = m_axi_ruser;
+        s_axi_rvalid_int = 0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axi_arvalid;
+
+                resp_next = 2'd0;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axi_arid_next = s_axi_arid;
+                    m_axi_araddr_next = s_axi_araddr;
+                    addr_next = s_axi_araddr;
+                    burst_next = s_axi_arlen;
+                    burst_size_next = s_axi_arsize;
+                    if (s_axi_arsize > M_BURST_SIZE) begin
+                        // need to adjust burst size
+                        if ({s_axi_arlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_arsize) > 255) begin
+                            // limit burst length to max
+                            master_burst_next = 8'd255;
+                        end else begin
+                            master_burst_next = {s_axi_arlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_arsize);
+                        end
+                        master_burst_size_next = M_BURST_SIZE;
+                        m_axi_arlen_next = master_burst_next;
+                        m_axi_arsize_next = master_burst_size_next;
+                    end else begin
+                        // pass through narrow (enough) burst
+                        master_burst_next = s_axi_arlen;
+                        master_burst_size_next = s_axi_arsize;
+                        m_axi_arlen_next = s_axi_arlen;
+                        m_axi_arsize_next = s_axi_arsize;
+                    end
+                    m_axi_arburst_next = s_axi_arburst;
+                    m_axi_arlock_next = s_axi_arlock;
+                    m_axi_arcache_next = s_axi_arcache;
+                    m_axi_arprot_next = s_axi_arprot;
+                    m_axi_arqos_next = s_axi_arqos;
+                    m_axi_arregion_next = s_axi_arregion;
+                    m_axi_aruser_next = s_axi_aruser;
+                    m_axi_arvalid_next = 1'b1;
+                    m_axi_rready_next = 1'b0;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_axi_rready_next = s_axi_rready_int_early && !m_axi_arvalid;
+
+                if (m_axi_rready && m_axi_rvalid) begin
+                    data_next[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axi_rdata;
+                    if (m_axi_rresp) begin
+                        resp_next = m_axi_rresp;
+                    end
+                    s_axi_rid_int = id_reg;
+                    s_axi_rdata_int = data_next;
+                    s_axi_rresp_int = resp_next;
+                    s_axi_rlast_int = 1'b0;
+                    s_axi_ruser_int = m_axi_ruser;
+                    s_axi_rvalid_int = 1'b0;
+                    master_burst_next = master_burst_reg - 1;
+                    addr_next = addr_reg + (1 << master_burst_size_reg);
+                    if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
+                        data_next = {DATA_WIDTH{1'b0}};
+                        burst_next = burst_reg - 1;
+                        s_axi_rvalid_int = 1'b1;
+                    end
+                    if (master_burst_reg == 0) begin
+                        if (burst_reg == 0) begin
+                            m_axi_rready_next = 1'b0;
+                            s_axi_rlast_int = 1'b1;
+                            s_axi_rvalid_int = 1'b1;
+                            s_axi_arready_next = !m_axi_arvalid;
+                            state_next = STATE_IDLE;
+                        end else begin
+                            // start new burst
+                            m_axi_araddr_next = addr_next;
+                            if (burst_size_reg > M_BURST_SIZE) begin
+                                // need to adjust burst size
+                                if ({burst_next, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg) > 255) begin
+                                    // limit burst length to max
+                                    master_burst_next = 8'd255;
+                                end else begin
+                                    master_burst_next = {burst_next, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg);
+                                end
+                                master_burst_size_next = M_BURST_SIZE;
+                                m_axi_arlen_next = master_burst_next;
+                                m_axi_arsize_next = master_burst_size_next;
+                            end else begin
+                                // pass through narrow (enough) burst
+                                master_burst_next = burst_next;
+                                master_burst_size_next = burst_size_reg;
+                                m_axi_arlen_next = burst_next;
+                                m_axi_arsize_next = burst_size_reg;
+                            end
+                            m_axi_arvalid_next = 1'b1;
+                            m_axi_rready_next = 1'b0;
+                            state_next = STATE_DATA;
+                        end
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_arready_reg <= 1'b0;
+        m_axi_arvalid_reg <= 1'b0;
+        m_axi_rready_reg <= 1'b0;
+    end else begin
+        state_reg <= state_next;
+        s_axi_arready_reg <= s_axi_arready_next;
+        m_axi_arvalid_reg <= m_axi_arvalid_next;
+        m_axi_rready_reg <= m_axi_rready_next;
+    end
+
+    id_reg <= id_next;
+    addr_reg <= addr_next;
+    data_reg <= data_next;
+    resp_reg <= resp_next;
+    ruser_reg <= ruser_next;
+    burst_reg <= burst_next;
+    burst_size_reg <= burst_size_next;
+    master_burst_reg <= master_burst_next;
+    master_burst_size_reg <= master_burst_size_next;
+
+    m_axi_arid_reg <= m_axi_arid_next;
+    m_axi_araddr_reg <= m_axi_araddr_next;
+    m_axi_arlen_reg <= m_axi_arlen_next;
+    m_axi_arsize_reg <= m_axi_arsize_next;
+    m_axi_arburst_reg <= m_axi_arburst_next;
+    m_axi_arlock_reg <= m_axi_arlock_next;
+    m_axi_arcache_reg <= m_axi_arcache_next;
+    m_axi_arprot_reg <= m_axi_arprot_next;
+    m_axi_arqos_reg <= m_axi_arqos_next;
+    m_axi_arregion_reg <= m_axi_arregion_next;
+    m_axi_aruser_reg <= m_axi_aruser_next;
+end
+
+// output datapath logic
+reg [ID_WIDTH-1:0]     s_axi_rid_reg    = {ID_WIDTH{1'b0}};
+reg [S_DATA_WIDTH-1:0] s_axi_rdata_reg  = {S_DATA_WIDTH{1'b0}};
+reg [1:0]              s_axi_rresp_reg  = 2'd0;
+reg                    s_axi_rlast_reg  = 1'b0;
+reg [RUSER_WIDTH-1:0]  s_axi_ruser_reg  = 1'b0;
+reg                    s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+
+reg [ID_WIDTH-1:0]     temp_s_axi_rid_reg    = {ID_WIDTH{1'b0}};
+reg [S_DATA_WIDTH-1:0] temp_s_axi_rdata_reg  = {S_DATA_WIDTH{1'b0}};
+reg [1:0]              temp_s_axi_rresp_reg  = 2'd0;
+reg                    temp_s_axi_rlast_reg  = 1'b0;
+reg [RUSER_WIDTH-1:0]  temp_s_axi_ruser_reg  = 1'b0;
+reg                    temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;
+
+// datapath control
+reg store_axi_r_int_to_output;
+reg store_axi_r_int_to_temp;
+reg store_axi_r_temp_to_output;
+
+assign s_axi_rid    = s_axi_rid_reg;
+assign s_axi_rdata  = s_axi_rdata_reg;
+assign s_axi_rresp  = s_axi_rresp_reg;
+assign s_axi_rlast  = s_axi_rlast_reg;
+assign s_axi_ruser  = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}};
+assign s_axi_rvalid = s_axi_rvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign s_axi_rready_int_early = s_axi_rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~s_axi_rvalid_int));
+
+always @* begin
+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;
+    temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+
+    store_axi_r_int_to_output = 1'b0;
+    store_axi_r_int_to_temp = 1'b0;
+    store_axi_r_temp_to_output = 1'b0;
+
+    if (s_axi_rready_int_reg) begin
+        // input is ready
+        if (s_axi_rready | ~s_axi_rvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_temp = 1'b1;
+        end
+    end else if (s_axi_rready) begin
+        // input is not ready, but output is ready
+        s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+        temp_s_axi_rvalid_next = 1'b0;
+        store_axi_r_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_rvalid_reg <= 1'b0;
+        s_axi_rready_int_reg <= 1'b0;
+        temp_s_axi_rvalid_reg <= 1'b0;
+    end else begin
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+        s_axi_rready_int_reg <= s_axi_rready_int_early;
+        temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
+    end
+
+    // datapath
+    if (store_axi_r_int_to_output) begin
+        s_axi_rid_reg <= s_axi_rid_int;
+        s_axi_rdata_reg <= s_axi_rdata_int;
+        s_axi_rresp_reg <= s_axi_rresp_int;
+        s_axi_rlast_reg <= s_axi_rlast_int;
+        s_axi_ruser_reg <= s_axi_ruser_int;
+    end else if (store_axi_r_temp_to_output) begin
+        s_axi_rid_reg <= temp_s_axi_rid_reg;
+        s_axi_rdata_reg <= temp_s_axi_rdata_reg;
+        s_axi_rresp_reg <= temp_s_axi_rresp_reg;
+        s_axi_rlast_reg <= temp_s_axi_rlast_reg;
+        s_axi_ruser_reg <= temp_s_axi_ruser_reg;
+    end
+
+    if (store_axi_r_int_to_temp) begin
+        temp_s_axi_rid_reg <= s_axi_rid_int;
+        temp_s_axi_rdata_reg <= s_axi_rdata_int;
+        temp_s_axi_rresp_reg <= s_axi_rresp_int;
+        temp_s_axi_rlast_reg <= s_axi_rlast_int;
+        temp_s_axi_ruser_reg <= s_axi_ruser_int;
+    end
+end
+
+endmodule

corundum/lib/axi/rtl/axi_adapter_wr.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 width adapter
+ */
+module axi_adapter_wr #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) interface data bus in bits
+    parameter S_DATA_WIDTH = 32,
+    // Width of input (slave) interface wstrb (width of data bus in words)
+    parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
+    // Width of output (master) interface data bus in bits
+    parameter M_DATA_WIDTH = 32,
+    // Width of output (master) interface wstrb (width of data bus in words)
+    parameter M_STRB_WIDTH = (M_DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0,
+    // Forward ID through adapter
+    parameter FORWARD_ID = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [7:0]               s_axi_awlen,
+    input  wire [2:0]               s_axi_awsize,
+    input  wire [1:0]               s_axi_awburst,
+    input  wire                     s_axi_awlock,
+    input  wire [3:0]               s_axi_awcache,
+    input  wire [2:0]               s_axi_awprot,
+    input  wire [3:0]               s_axi_awqos,
+    input  wire [3:0]               s_axi_awregion,
+    input  wire [AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire                     s_axi_awvalid,
+    output wire                     s_axi_awready,
+    input  wire [S_DATA_WIDTH-1:0]  s_axi_wdata,
+    input  wire [S_STRB_WIDTH-1:0]  s_axi_wstrb,
+    input  wire                     s_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire                     s_axi_wvalid,
+    output wire                     s_axi_wready,
+    output wire [ID_WIDTH-1:0]      s_axi_bid,
+    output wire [1:0]               s_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire                     s_axi_bvalid,
+    input  wire                     s_axi_bready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_awid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [7:0]               m_axi_awlen,
+    output wire [2:0]               m_axi_awsize,
+    output wire [1:0]               m_axi_awburst,
+    output wire                     m_axi_awlock,
+    output wire [3:0]               m_axi_awcache,
+    output wire [2:0]               m_axi_awprot,
+    output wire [3:0]               m_axi_awqos,
+    output wire [3:0]               m_axi_awregion,
+    output wire [AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire                     m_axi_awvalid,
+    input  wire                     m_axi_awready,
+    output wire [M_DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [M_STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                     m_axi_wlast,
+    output wire [WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire                     m_axi_wvalid,
+    input  wire                     m_axi_wready,
+    input  wire [ID_WIDTH-1:0]      m_axi_bid,
+    input  wire [1:0]               m_axi_bresp,
+    input  wire [BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire                     m_axi_bvalid,
+    output wire                     m_axi_bready
+);
+
+parameter S_ADDR_BIT_OFFSET = $clog2(S_STRB_WIDTH);
+parameter M_ADDR_BIT_OFFSET = $clog2(M_STRB_WIDTH);
+parameter S_WORD_WIDTH = S_STRB_WIDTH;
+parameter M_WORD_WIDTH = M_STRB_WIDTH;
+parameter S_WORD_SIZE = S_DATA_WIDTH/S_WORD_WIDTH;
+parameter M_WORD_SIZE = M_DATA_WIDTH/M_WORD_WIDTH;
+parameter S_BURST_SIZE = $clog2(S_STRB_WIDTH);
+parameter M_BURST_SIZE = $clog2(M_STRB_WIDTH);
+
+// output bus is wider
+parameter EXPAND = M_STRB_WIDTH > S_STRB_WIDTH;
+parameter DATA_WIDTH = EXPAND ? M_DATA_WIDTH : S_DATA_WIDTH;
+parameter STRB_WIDTH = EXPAND ? M_STRB_WIDTH : S_STRB_WIDTH;
+// required number of segments in wider bus
+parameter SEGMENT_COUNT = EXPAND ? (M_STRB_WIDTH / S_STRB_WIDTH) : (S_STRB_WIDTH / M_STRB_WIDTH);
+// data width and keep width per segment
+parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
+parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
+
+// bus width assertions
+initial begin
+    if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
+        $error("Error: AXI slave interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
+        $error("Error: AXI master interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (S_WORD_SIZE != M_WORD_SIZE) begin
+        $error("Error: word size mismatch (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
+        $error("Error: AXI slave interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
+        $error("Error: AXI master interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+end
+
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DATA = 2'd1,
+    STATE_DATA_2 = 2'd2,
+    STATE_RESP = 2'd3;
+
+reg [1:0] state_reg = STATE_IDLE, state_next;
+
+reg [ID_WIDTH-1:0] id_reg = {ID_WIDTH{1'b0}}, id_next;
+reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
+reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
+reg [STRB_WIDTH-1:0] strb_reg = {STRB_WIDTH{1'b0}}, strb_next;
+reg [WUSER_WIDTH-1:0] wuser_reg = {WUSER_WIDTH{1'b0}}, wuser_next;
+reg [7:0] burst_reg = 8'd0, burst_next;
+reg [2:0] burst_size_reg = 3'd0, burst_size_next;
+reg [7:0] master_burst_reg = 8'd0, master_burst_next;
+reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
+reg burst_active_reg = 1'b0, burst_active_next;
+reg first_transfer_reg = 1'b0, first_transfer_next;
+
+reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
+reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
+reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next;
+reg [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
+reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}}, s_axi_buser_next;
+reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
+
+reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}}, m_axi_awid_next;
+reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}, m_axi_awaddr_next;
+reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;
+reg [2:0] m_axi_awsize_reg = 3'd0, m_axi_awsize_next;
+reg [1:0] m_axi_awburst_reg = 2'd0, m_axi_awburst_next;
+reg m_axi_awlock_reg = 1'b0, m_axi_awlock_next;
+reg [3:0] m_axi_awcache_reg = 4'd0, m_axi_awcache_next;
+reg [2:0] m_axi_awprot_reg = 3'd0, m_axi_awprot_next;
+reg [3:0] m_axi_awqos_reg = 4'd0, m_axi_awqos_next;
+reg [3:0] m_axi_awregion_reg = 4'd0, m_axi_awregion_next;
+reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}, m_axi_awuser_next;
+reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
+reg m_axi_bready_reg = 1'b0, m_axi_bready_next;
+
+// internal datapath
+reg  [M_DATA_WIDTH-1:0] m_axi_wdata_int;
+reg  [M_STRB_WIDTH-1:0] m_axi_wstrb_int;
+reg                     m_axi_wlast_int;
+reg  [WUSER_WIDTH-1:0]  m_axi_wuser_int;
+reg                     m_axi_wvalid_int;
+reg                     m_axi_wready_int_reg = 1'b0;
+wire                    m_axi_wready_int_early;
+
+assign s_axi_awready = s_axi_awready_reg;
+assign s_axi_wready = s_axi_wready_reg;
+assign s_axi_bid = s_axi_bid_reg;
+assign s_axi_bresp = s_axi_bresp_reg;
+assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
+assign s_axi_bvalid = s_axi_bvalid_reg;
+
+assign m_axi_awid = FORWARD_ID ? m_axi_awid_reg : {ID_WIDTH{1'b0}};
+assign m_axi_awaddr = m_axi_awaddr_reg;
+assign m_axi_awlen = m_axi_awlen_reg;
+assign m_axi_awsize = m_axi_awsize_reg;
+assign m_axi_awburst = m_axi_awburst_reg;
+assign m_axi_awlock = m_axi_awlock_reg;
+assign m_axi_awcache = m_axi_awcache_reg;
+assign m_axi_awprot = m_axi_awprot_reg;
+assign m_axi_awqos = m_axi_awqos_reg;
+assign m_axi_awregion = m_axi_awregion_reg;
+assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
+assign m_axi_awvalid = m_axi_awvalid_reg;
+assign m_axi_bready = m_axi_bready_reg;
+
+integer i;
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    id_next = id_reg;
+    addr_next = addr_reg;
+    data_next = data_reg;
+    strb_next = strb_reg;
+    wuser_next = wuser_reg;
+    burst_next = burst_reg;
+    burst_size_next = burst_size_reg;
+    master_burst_next = master_burst_reg;
+    master_burst_size_next = master_burst_size_reg;
+    burst_active_next = burst_active_reg;
+    first_transfer_next = first_transfer_reg;
+
+    s_axi_awready_next = 1'b0;
+    s_axi_wready_next = 1'b0;
+    s_axi_bid_next = s_axi_bid_reg;
+    s_axi_bresp_next = s_axi_bresp_reg;
+    s_axi_buser_next = s_axi_buser_reg;
+    s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
+    m_axi_awid_next = m_axi_awid_reg;
+    m_axi_awaddr_next = m_axi_awaddr_reg;
+    m_axi_awlen_next = m_axi_awlen_reg;
+    m_axi_awsize_next = m_axi_awsize_reg;
+    m_axi_awburst_next = m_axi_awburst_reg;
+    m_axi_awlock_next = m_axi_awlock_reg;
+    m_axi_awcache_next = m_axi_awcache_reg;
+    m_axi_awprot_next = m_axi_awprot_reg;
+    m_axi_awqos_next = m_axi_awqos_reg;
+    m_axi_awregion_next = m_axi_awregion_reg;
+    m_axi_awuser_next = m_axi_awuser_reg;
+    m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_awready;
+    m_axi_bready_next = 1'b0;
+
+    if (SEGMENT_COUNT == 1) begin
+        // master output is same width; direct transfer with no splitting/merging
+        m_axi_wdata_int = s_axi_wdata;
+        m_axi_wstrb_int = s_axi_wstrb;
+        m_axi_wlast_int = s_axi_wlast;
+        m_axi_wuser_int = s_axi_wuser;
+        m_axi_wvalid_int = 1'b0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axi_awvalid;
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axi_awid_next = s_axi_awid;
+                    m_axi_awaddr_next = s_axi_awaddr;
+                    m_axi_awlen_next = s_axi_awlen;
+                    m_axi_awsize_next = s_axi_awsize;
+                    m_axi_awburst_next = s_axi_awburst;
+                    m_axi_awlock_next = s_axi_awlock;
+                    m_axi_awcache_next = s_axi_awcache;
+                    m_axi_awprot_next = s_axi_awprot;
+                    m_axi_awqos_next = s_axi_awqos;
+                    m_axi_awregion_next = s_axi_awregion;
+                    m_axi_awuser_next = s_axi_awuser;
+                    m_axi_awvalid_next = 1'b1;
+                    s_axi_wready_next = m_axi_wready_int_early;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer write data
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    m_axi_wdata_int = s_axi_wdata;
+                    m_axi_wstrb_int = s_axi_wstrb;
+                    m_axi_wlast_int = s_axi_wlast;
+                    m_axi_wuser_int = s_axi_wuser;
+                    m_axi_wvalid_int = 1'b1;
+                    if (s_axi_wlast) begin
+                        // last data word, wait for response
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid;
+                        state_next = STATE_RESP;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axi_bready_next = !s_axi_bvalid;
+
+                if (m_axi_bready && m_axi_bvalid) begin
+                    m_axi_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    s_axi_bresp_next = m_axi_bresp;
+                    s_axi_buser_next = m_axi_buser;
+                    s_axi_bvalid_next = 1'b1;
+                    s_axi_awready_next = !m_axi_awvalid;
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end else if (EXPAND) begin
+        // master output is wider; merge writes
+        m_axi_wdata_int = {(M_WORD_WIDTH/S_WORD_WIDTH){s_axi_wdata}};
+        m_axi_wstrb_int = s_axi_wstrb;
+        m_axi_wlast_int = s_axi_wlast;
+        m_axi_wuser_int = s_axi_wuser;
+        m_axi_wvalid_int = 1'b0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axi_awvalid;
+
+                data_next = {DATA_WIDTH{1'b0}};
+                strb_next = {STRB_WIDTH{1'b0}};
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axi_awid_next = s_axi_awid;
+                    m_axi_awaddr_next = s_axi_awaddr;
+                    addr_next = s_axi_awaddr;
+                    burst_next = s_axi_awlen;
+                    burst_size_next = s_axi_awsize;
+                    if (CONVERT_BURST && s_axi_awcache[1] && (CONVERT_NARROW_BURST || s_axi_awsize == S_BURST_SIZE)) begin
+                        // merge writes
+                        // require CONVERT_BURST and awcache[1] set
+                        master_burst_size_next = M_BURST_SIZE;
+                        if (CONVERT_NARROW_BURST) begin
+                            m_axi_awlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_awlen} << s_axi_awsize) + s_axi_awaddr[M_ADDR_BIT_OFFSET-1:0]) >> M_BURST_SIZE;
+                        end else begin
+                            m_axi_awlen_next = ({1'b0, s_axi_awlen} + s_axi_awaddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]) >> $clog2(SEGMENT_COUNT);
+                        end
+                        m_axi_awsize_next = M_BURST_SIZE;
+                        state_next = STATE_DATA_2;
+                    end else begin
+                        // output narrow burst
+                        master_burst_size_next = s_axi_awsize;
+                        m_axi_awlen_next = s_axi_awlen;
+                        m_axi_awsize_next = s_axi_awsize;
+                        state_next = STATE_DATA;
+                    end
+                    m_axi_awburst_next = s_axi_awburst;
+                    m_axi_awlock_next = s_axi_awlock;
+                    m_axi_awcache_next = s_axi_awcache;
+                    m_axi_awprot_next = s_axi_awprot;
+                    m_axi_awqos_next = s_axi_awqos;
+                    m_axi_awregion_next = s_axi_awregion;
+                    m_axi_awuser_next = s_axi_awuser;
+                    m_axi_awvalid_next = 1'b1;
+                    s_axi_wready_next = m_axi_wready_int_early;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer write data
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    m_axi_wdata_int = {(M_WORD_WIDTH/S_WORD_WIDTH){s_axi_wdata}};
+                    m_axi_wstrb_int = s_axi_wstrb << (addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_STRB_WIDTH);
+                    m_axi_wlast_int = s_axi_wlast;
+                    m_axi_wuser_int = s_axi_wuser;
+                    m_axi_wvalid_int = 1'b1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (s_axi_wlast) begin
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid;
+                        state_next = STATE_RESP;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_2: begin
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    if (CONVERT_NARROW_BURST) begin
+                        for (i = 0; i < S_WORD_WIDTH; i = i + 1) begin
+                            if (s_axi_wstrb[i]) begin
+                                data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*M_WORD_SIZE +: M_WORD_SIZE] = s_axi_wdata[i*M_WORD_SIZE +: M_WORD_SIZE];
+                                strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1;
+                            end
+                        end
+                    end else begin
+                        data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
+                        strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
+                    end
+                    m_axi_wdata_int = data_next;
+                    m_axi_wstrb_int = strb_next;
+                    m_axi_wlast_int = s_axi_wlast;
+                    m_axi_wuser_int = s_axi_wuser;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        data_next = {DATA_WIDTH{1'b0}};
+                        strb_next = {STRB_WIDTH{1'b0}};
+                        m_axi_wvalid_int = 1'b1;
+                    end
+                    if (burst_reg == 0) begin
+                        m_axi_wvalid_int = 1'b1;
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid;
+                        state_next = STATE_RESP;
+                    end else begin
+                        state_next = STATE_DATA_2;
+                    end
+                end else begin
+                    state_next = STATE_DATA_2;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axi_bready_next = !s_axi_bvalid;
+
+                if (m_axi_bready && m_axi_bvalid) begin
+                    m_axi_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    s_axi_bresp_next = m_axi_bresp;
+                    s_axi_buser_next = m_axi_buser;
+                    s_axi_bvalid_next = 1'b1;
+                    s_axi_awready_next = !m_axi_awvalid;
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end else begin
+        // master output is narrower; split writes, and possibly split burst
+        m_axi_wdata_int = data_reg;
+        m_axi_wstrb_int = strb_reg;
+        m_axi_wlast_int = 1'b0;
+        m_axi_wuser_int = wuser_reg;
+        m_axi_wvalid_int = 1'b0;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axi_awvalid;
+
+                first_transfer_next = 1'b1;
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axi_awid_next = s_axi_awid;
+                    m_axi_awaddr_next = s_axi_awaddr;
+                    addr_next = s_axi_awaddr;
+                    burst_next = s_axi_awlen;
+                    burst_size_next = s_axi_awsize;
+                    burst_active_next = 1'b1;
+                    if (s_axi_awsize > M_BURST_SIZE) begin
+                        // need to adjust burst size
+                        if ({s_axi_awlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_awsize) > 255) begin
+                            // limit burst length to max
+                            master_burst_next = 8'd255;
+                        end else begin
+                            master_burst_next = {s_axi_awlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_awsize);
+                        end
+                        master_burst_size_next = M_BURST_SIZE;
+                        m_axi_awlen_next = master_burst_next;
+                        m_axi_awsize_next = master_burst_size_next;
+                    end else begin
+                        // pass through narrow (enough) burst
+                        master_burst_next = s_axi_awlen;
+                        master_burst_size_next = s_axi_awsize;
+                        m_axi_awlen_next = s_axi_awlen;
+                        m_axi_awsize_next = s_axi_awsize;
+                    end
+                    m_axi_awburst_next = s_axi_awburst;
+                    m_axi_awlock_next = s_axi_awlock;
+                    m_axi_awcache_next = s_axi_awcache;
+                    m_axi_awprot_next = s_axi_awprot;
+                    m_axi_awqos_next = s_axi_awqos;
+                    m_axi_awregion_next = s_axi_awregion;
+                    m_axi_awuser_next = s_axi_awuser;
+                    m_axi_awvalid_next = 1'b1;
+                    s_axi_wready_next = m_axi_wready_int_early;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                s_axi_wready_next = m_axi_wready_int_early;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    data_next = s_axi_wdata;
+                    strb_next = s_axi_wstrb;
+                    wuser_next = s_axi_wuser;
+                    m_axi_wdata_int = s_axi_wdata >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_DATA_WIDTH);
+                    m_axi_wstrb_int = s_axi_wstrb >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_STRB_WIDTH);
+                    m_axi_wlast_int = 1'b0;
+                    m_axi_wuser_int = s_axi_wuser;
+                    m_axi_wvalid_int = 1'b1;
+                    burst_next = burst_reg - 1;
+                    burst_active_next = burst_reg != 0;
+                    master_burst_next = master_burst_reg - 1;
+                    addr_next = addr_reg + (1 << master_burst_size_reg);
+                    if (master_burst_reg == 0) begin
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid && !s_axi_awvalid;
+                        m_axi_wlast_int = 1'b1;
+                        state_next = STATE_RESP;
+                    end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
+                        state_next = STATE_DATA;
+                    end else begin
+                        s_axi_wready_next = 1'b0;
+                        state_next = STATE_DATA_2;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_2: begin
+                s_axi_wready_next = 1'b0;
+
+                if (m_axi_wready_int_reg) begin
+                    m_axi_wdata_int = data_reg >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_DATA_WIDTH);
+                    m_axi_wstrb_int = strb_reg >> (addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_STRB_WIDTH);
+                    m_axi_wlast_int = 1'b0;
+                    m_axi_wuser_int = wuser_reg;
+                    m_axi_wvalid_int = 1'b1;
+                    master_burst_next = master_burst_reg - 1;
+                    addr_next = addr_reg + (1 << master_burst_size_reg);
+                    if (master_burst_reg == 0) begin
+                        // burst on master interface finished; transfer response
+                        s_axi_wready_next = 1'b0;
+                        m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
+                        m_axi_wlast_int = 1'b1;
+                        state_next = STATE_RESP;
+                    end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
+                        state_next = STATE_DATA;
+                    end else begin
+                        s_axi_wready_next = 1'b0;
+                        state_next = STATE_DATA_2;
+                    end
+                end else begin
+                    state_next = STATE_DATA_2;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
+
+                if (m_axi_bready && m_axi_bvalid) begin
+                    first_transfer_next = 1'b0;
+                    m_axi_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    if (first_transfer_reg || m_axi_bresp != 0) begin
+                        s_axi_bresp_next = m_axi_bresp;
+                    end
+                    if (burst_active_reg) begin
+                        // burst on slave interface still active; start new burst
+                        m_axi_awaddr_next = addr_reg;
+                        if (burst_size_reg > M_BURST_SIZE) begin
+                            // need to adjust burst size
+                            if ({burst_reg, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg) > 255) begin
+                                // limit burst length to max
+                                master_burst_next = 8'd255;
+                            end else begin
+                                master_burst_next = {burst_reg, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg);
+                            end
+                            master_burst_size_next = M_BURST_SIZE;
+                            m_axi_awlen_next = master_burst_next;
+                            m_axi_awsize_next = master_burst_size_next;
+                        end else begin
+                            // pass through narrow (enough) burst
+                            master_burst_next = burst_reg;
+                            master_burst_size_next = burst_size_reg;
+                            m_axi_awlen_next = burst_reg;
+                            m_axi_awsize_next = burst_size_reg;
+                        end
+                        m_axi_awvalid_next = 1'b1;
+                        state_next = STATE_DATA;
+                    end else begin
+                        // burst on slave interface finished; return to idle
+                        s_axi_bvalid_next = 1'b1;
+                        s_axi_awready_next = !m_axi_awvalid;
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_awready_reg <= 1'b0;
+        s_axi_wready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+        m_axi_awvalid_reg <= 1'b0;
+        m_axi_bready_reg <= 1'b0;
+    end else begin
+        state_reg <= state_next;
+        s_axi_awready_reg <= s_axi_awready_next;
+        s_axi_wready_reg <= s_axi_wready_next;
+        s_axi_bvalid_reg <= s_axi_bvalid_next;
+        m_axi_awvalid_reg <= m_axi_awvalid_next;
+        m_axi_bready_reg <= m_axi_bready_next;
+    end
+
+    id_reg <= id_next;
+    addr_reg <= addr_next;
+    data_reg <= data_next;
+    strb_reg <= strb_next;
+    wuser_reg <= wuser_next;
+    burst_reg <= burst_next;
+    burst_size_reg <= burst_size_next;
+    master_burst_reg <= master_burst_next;
+    master_burst_size_reg <= master_burst_size_next;
+    burst_active_reg <= burst_active_next;
+    first_transfer_reg <= first_transfer_next;
+
+    s_axi_bid_reg <= s_axi_bid_next;
+    s_axi_bresp_reg <= s_axi_bresp_next;
+    s_axi_buser_reg <= s_axi_buser_next;
+    m_axi_awid_reg <= m_axi_awid_next;
+    m_axi_awaddr_reg <= m_axi_awaddr_next;
+    m_axi_awlen_reg <= m_axi_awlen_next;
+    m_axi_awsize_reg <= m_axi_awsize_next;
+    m_axi_awburst_reg <= m_axi_awburst_next;
+    m_axi_awlock_reg <= m_axi_awlock_next;
+    m_axi_awcache_reg <= m_axi_awcache_next;
+    m_axi_awprot_reg <= m_axi_awprot_next;
+    m_axi_awqos_reg <= m_axi_awqos_next;
+    m_axi_awregion_reg <= m_axi_awregion_next;
+    m_axi_awuser_reg <= m_axi_awuser_next;
+end
+
+// output datapath logic
+reg [M_DATA_WIDTH-1:0] m_axi_wdata_reg  = {M_DATA_WIDTH{1'b0}};
+reg [M_STRB_WIDTH-1:0] m_axi_wstrb_reg  = {M_STRB_WIDTH{1'b0}};
+reg                    m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0]  m_axi_wuser_reg  = 1'b0;
+reg                    m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
+
+reg [M_DATA_WIDTH-1:0] temp_m_axi_wdata_reg  = {M_DATA_WIDTH{1'b0}};
+reg [M_STRB_WIDTH-1:0] temp_m_axi_wstrb_reg  = {M_STRB_WIDTH{1'b0}};
+reg                    temp_m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0]  temp_m_axi_wuser_reg  = 1'b0;
+reg                    temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
+
+// datapath control
+reg store_axi_w_int_to_output;
+reg store_axi_w_int_to_temp;
+reg store_axi_w_temp_to_output;
+
+assign m_axi_wdata  = m_axi_wdata_reg;
+assign m_axi_wstrb  = m_axi_wstrb_reg;
+assign m_axi_wlast  = m_axi_wlast_reg;
+assign m_axi_wuser  = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
+assign m_axi_wvalid = m_axi_wvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axi_wready_int_early = m_axi_wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~m_axi_wvalid_int));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;
+    temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+
+    store_axi_w_int_to_output = 1'b0;
+    store_axi_w_int_to_temp = 1'b0;
+    store_axi_w_temp_to_output = 1'b0;
+
+    if (m_axi_wready_int_reg) begin
+        // input is ready
+        if (m_axi_wready | ~m_axi_wvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_temp = 1'b1;
+        end
+    end else if (m_axi_wready) begin
+        // input is not ready, but output is ready
+        m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+        temp_m_axi_wvalid_next = 1'b0;
+        store_axi_w_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_wvalid_reg <= 1'b0;
+        m_axi_wready_int_reg <= 1'b0;
+        temp_m_axi_wvalid_reg <= 1'b0;
+    end else begin
+        m_axi_wvalid_reg <= m_axi_wvalid_next;
+        m_axi_wready_int_reg <= m_axi_wready_int_early;
+        temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
+    end
+
+    // datapath
+    if (store_axi_w_int_to_output) begin
+        m_axi_wdata_reg <= m_axi_wdata_int;
+        m_axi_wstrb_reg <= m_axi_wstrb_int;
+        m_axi_wlast_reg <= m_axi_wlast_int;
+        m_axi_wuser_reg <= m_axi_wuser_int;
+    end else if (store_axi_w_temp_to_output) begin
+        m_axi_wdata_reg <= temp_m_axi_wdata_reg;
+        m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
+        m_axi_wlast_reg <= temp_m_axi_wlast_reg;
+        m_axi_wuser_reg <= temp_m_axi_wuser_reg;
+    end
+
+    if (store_axi_w_int_to_temp) begin
+        temp_m_axi_wdata_reg <= m_axi_wdata_int;
+        temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
+        temp_m_axi_wlast_reg <= m_axi_wlast_int;
+        temp_m_axi_wuser_reg <= m_axi_wuser_int;
+    end
+end
+
+endmodule

corundum/lib/axi/rtl/axi_axil_adapter.v

+/*
+
+Copyright (c) 2019 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 to AXI4-Lite adapter
+ */
+module axi_axil_adapter #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) AXI interface data bus in bits
+    parameter AXI_DATA_WIDTH = 32,
+    // Width of input (slave) AXI interface wstrb (width of data bus in words)
+    parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
+    // Width of AXI ID signal
+    parameter AXI_ID_WIDTH = 8,
+    // Width of output (master) AXI lite interface data bus in bits
+    parameter AXIL_DATA_WIDTH = 32,
+    // Width of output (master) AXI lite interface wstrb (width of data bus in words)
+    parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0
+)
+(
+    input  wire                        clk,
+    input  wire                        rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [AXI_ID_WIDTH-1:0]     s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]       s_axi_awaddr,
+    input  wire [7:0]                  s_axi_awlen,
+    input  wire [2:0]                  s_axi_awsize,
+    input  wire [1:0]                  s_axi_awburst,
+    input  wire                        s_axi_awlock,
+    input  wire [3:0]                  s_axi_awcache,
+    input  wire [2:0]                  s_axi_awprot,
+    input  wire                        s_axi_awvalid,
+    output wire                        s_axi_awready,
+    input  wire [AXI_DATA_WIDTH-1:0]   s_axi_wdata,
+    input  wire [AXI_STRB_WIDTH-1:0]   s_axi_wstrb,
+    input  wire                        s_axi_wlast,
+    input  wire                        s_axi_wvalid,
+    output wire                        s_axi_wready,
+    output wire [AXI_ID_WIDTH-1:0]     s_axi_bid,
+    output wire [1:0]                  s_axi_bresp,
+    output wire                        s_axi_bvalid,
+    input  wire                        s_axi_bready,
+    input  wire [AXI_ID_WIDTH-1:0]     s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]       s_axi_araddr,
+    input  wire [7:0]                  s_axi_arlen,
+    input  wire [2:0]                  s_axi_arsize,
+    input  wire [1:0]                  s_axi_arburst,
+    input  wire                        s_axi_arlock,
+    input  wire [3:0]                  s_axi_arcache,
+    input  wire [2:0]                  s_axi_arprot,
+    input  wire                        s_axi_arvalid,
+    output wire                        s_axi_arready,
+    output wire [AXI_ID_WIDTH-1:0]     s_axi_rid,
+    output wire [AXI_DATA_WIDTH-1:0]   s_axi_rdata,
+    output wire [1:0]                  s_axi_rresp,
+    output wire                        s_axi_rlast,
+    output wire                        s_axi_rvalid,
+    input  wire                        s_axi_rready,
+
+    /*
+     * AXI lite master interface
+     */
+    output wire [ADDR_WIDTH-1:0]       m_axil_awaddr,
+    output wire [2:0]                  m_axil_awprot,
+    output wire                        m_axil_awvalid,
+    input  wire                        m_axil_awready,
+    output wire [AXIL_DATA_WIDTH-1:0]  m_axil_wdata,
+    output wire [AXIL_STRB_WIDTH-1:0]  m_axil_wstrb,
+    output wire                        m_axil_wvalid,
+    input  wire                        m_axil_wready,
+    input  wire [1:0]                  m_axil_bresp,
+    input  wire                        m_axil_bvalid,
+    output wire                        m_axil_bready,
+    output wire [ADDR_WIDTH-1:0]       m_axil_araddr,
+    output wire [2:0]                  m_axil_arprot,
+    output wire                        m_axil_arvalid,
+    input  wire                        m_axil_arready,
+    input  wire [AXIL_DATA_WIDTH-1:0]  m_axil_rdata,
+    input  wire [1:0]                  m_axil_rresp,
+    input  wire                        m_axil_rvalid,
+    output wire                        m_axil_rready
+);
+
+
+axi_axil_adapter_wr #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
+    .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
+)
+axi_axil_adapter_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*
+     * AXI lite master interface
+     */
+    .m_axil_awaddr(m_axil_awaddr),
+    .m_axil_awprot(m_axil_awprot),
+    .m_axil_awvalid(m_axil_awvalid),
+    .m_axil_awready(m_axil_awready),
+    .m_axil_wdata(m_axil_wdata),
+    .m_axil_wstrb(m_axil_wstrb),
+    .m_axil_wvalid(m_axil_wvalid),
+    .m_axil_wready(m_axil_wready),
+    .m_axil_bresp(m_axil_bresp),
+    .m_axil_bvalid(m_axil_bvalid),
+    .m_axil_bready(m_axil_bready)
+);
+
+axi_axil_adapter_rd #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
+    .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
+)
+axi_axil_adapter_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*
+     * AXI lite master interface
+     */
+    .m_axil_araddr(m_axil_araddr),
+    .m_axil_arprot(m_axil_arprot),
+    .m_axil_arvalid(m_axil_arvalid),
+    .m_axil_arready(m_axil_arready),
+    .m_axil_rdata(m_axil_rdata),
+    .m_axil_rresp(m_axil_rresp),
+    .m_axil_rvalid(m_axil_rvalid),
+    .m_axil_rready(m_axil_rready)
+);
+
+endmodule

corundum/lib/axi/rtl/axi_axil_adapter_rd.v

+/*
+
+Copyright (c) 2019 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 to AXI4-Lite adapter (read)
+ */
+module axi_axil_adapter_rd #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) AXI interface data bus in bits
+    parameter AXI_DATA_WIDTH = 32,
+    // Width of input (slave) AXI interface wstrb (width of data bus in words)
+    parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
+    // Width of AXI ID signal
+    parameter AXI_ID_WIDTH = 8,
+    // Width of output (master) AXI lite interface data bus in bits
+    parameter AXIL_DATA_WIDTH = 32,
+    // Width of output (master) AXI lite interface wstrb (width of data bus in words)
+    parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0
+)
+(
+    input  wire                        clk,
+    input  wire                        rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [AXI_ID_WIDTH-1:0]     s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]       s_axi_araddr,
+    input  wire [7:0]                  s_axi_arlen,
+    input  wire [2:0]                  s_axi_arsize,
+    input  wire [1:0]                  s_axi_arburst,
+    input  wire                        s_axi_arlock,
+    input  wire [3:0]                  s_axi_arcache,
+    input  wire [2:0]                  s_axi_arprot,
+    input  wire                        s_axi_arvalid,
+    output wire                        s_axi_arready,
+    output wire [AXI_ID_WIDTH-1:0]     s_axi_rid,
+    output wire [AXI_DATA_WIDTH-1:0]   s_axi_rdata,
+    output wire [1:0]                  s_axi_rresp,
+    output wire                        s_axi_rlast,
+    output wire                        s_axi_rvalid,
+    input  wire                        s_axi_rready,
+
+    /*
+     * AXI lite master interface
+     */
+    output wire [ADDR_WIDTH-1:0]       m_axil_araddr,
+    output wire [2:0]                  m_axil_arprot,
+    output wire                        m_axil_arvalid,
+    input  wire                        m_axil_arready,
+    input  wire [AXIL_DATA_WIDTH-1:0]  m_axil_rdata,
+    input  wire [1:0]                  m_axil_rresp,
+    input  wire                        m_axil_rvalid,
+    output wire                        m_axil_rready
+);
+
+parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH);
+parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH);
+parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
+parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH;
+parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
+parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH;
+parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
+parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH);
+
+// output bus is wider
+parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH;
+parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH;
+parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH;
+// required number of segments in wider bus
+parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH);
+// data width and keep width per segment
+parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
+parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
+
+// bus width assertions
+initial begin
+    if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
+        $error("Error: AXI slave interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
+        $error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
+        $error("Error: word size mismatch (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
+        $error("Error: AXI slave interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
+        $error("Error: AXI lite master interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+end
+
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DATA = 2'd1,
+    STATE_DATA_READ = 2'd2,
+    STATE_DATA_SPLIT = 2'd3;
+
+reg [1:0] state_reg = STATE_IDLE, state_next;
+
+reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next;
+reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
+reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
+reg [1:0] resp_reg = 2'd0, resp_next;
+reg [7:0] burst_reg = 8'd0, burst_next;
+reg [2:0] burst_size_reg = 3'd0, burst_size_next;
+reg [7:0] master_burst_reg = 8'd0, master_burst_next;
+reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
+
+reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
+reg [AXI_ID_WIDTH-1:0] s_axi_rid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_rid_next;
+reg [AXI_DATA_WIDTH-1:0] s_axi_rdata_reg = {AXI_DATA_WIDTH{1'b0}}, s_axi_rdata_next;
+reg [1:0] s_axi_rresp_reg = 2'd0, s_axi_rresp_next;
+reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
+reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+
+reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_araddr_next;
+reg [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next;
+reg m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
+reg m_axil_rready_reg = 1'b0, m_axil_rready_next;
+
+assign s_axi_arready = s_axi_arready_reg;
+assign s_axi_rid = s_axi_rid_reg;
+assign s_axi_rdata = s_axi_rdata_reg;
+assign s_axi_rresp = s_axi_rresp_reg;
+assign s_axi_rlast = s_axi_rlast_reg;
+assign s_axi_rvalid = s_axi_rvalid_reg;
+
+assign m_axil_araddr = m_axil_araddr_reg;
+assign m_axil_arprot = m_axil_arprot_reg;
+assign m_axil_arvalid = m_axil_arvalid_reg;
+assign m_axil_rready = m_axil_rready_reg;
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    id_next = id_reg;
+    addr_next = addr_reg;
+    data_next = data_reg;
+    resp_next = resp_reg;
+    burst_next = burst_reg;
+    burst_size_next = burst_size_reg;
+    master_burst_next = master_burst_reg;
+    master_burst_size_next = master_burst_size_reg;
+
+    s_axi_arready_next = 1'b0;
+    s_axi_rid_next = s_axi_rid_reg;
+    s_axi_rdata_next = s_axi_rdata_reg;
+    s_axi_rresp_next = s_axi_rresp_reg;
+    s_axi_rlast_next = s_axi_rlast_reg;
+    s_axi_rvalid_next = s_axi_rvalid_reg && !s_axi_rready;
+    m_axil_araddr_next = m_axil_araddr_reg;
+    m_axil_arprot_next = m_axil_arprot_reg;
+    m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_arready;
+    m_axil_rready_next = 1'b0;
+
+    if (SEGMENT_COUNT == 1) begin
+        // master output is same width; direct transfer with no splitting/merging
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axil_arvalid;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axil_araddr_next = s_axi_araddr;
+                    addr_next = s_axi_araddr;
+                    burst_next = s_axi_arlen;
+                    burst_size_next = s_axi_arsize;
+                    m_axil_arprot_next = s_axi_arprot;
+                    m_axil_arvalid_next = 1'b1;
+                    m_axil_rready_next = 1'b0;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer read data
+                m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
+
+                if (m_axil_rready && m_axil_rvalid) begin
+                    s_axi_rid_next = id_reg;
+                    s_axi_rdata_next = m_axil_rdata;
+                    s_axi_rresp_next = m_axil_rresp;
+                    s_axi_rlast_next = 1'b0;
+                    s_axi_rvalid_next = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        // last data word, return to idle
+                        m_axil_rready_next = 1'b0;
+                        s_axi_rlast_next = 1'b1;
+                        s_axi_arready_next = !m_axil_arvalid;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        // start new AXI lite read
+                        m_axil_araddr_next = addr_next;
+                        m_axil_arvalid_next = 1'b1;
+                        m_axil_rready_next = 1'b0;
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end else if (EXPAND) begin
+        // master output is wider; split reads
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axil_arvalid;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axil_araddr_next = s_axi_araddr;
+                    addr_next = s_axi_araddr;
+                    burst_next = s_axi_arlen;
+                    burst_size_next = s_axi_arsize;
+                    if (CONVERT_BURST && s_axi_arcache[1] && (CONVERT_NARROW_BURST || s_axi_arsize == AXI_BURST_SIZE)) begin
+                        // split reads
+                        // require CONVERT_BURST and arcache[1] set
+                        master_burst_size_next = AXIL_BURST_SIZE;
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        // output narrow burst
+                        master_burst_size_next = s_axi_arsize;
+                        state_next = STATE_DATA;
+                    end
+                    m_axil_arprot_next = s_axi_arprot;
+                    m_axil_arvalid_next = 1'b1;
+                    m_axil_rready_next = 1'b0;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
+
+                if (m_axil_rready && m_axil_rvalid) begin
+                    s_axi_rid_next = id_reg;
+                    s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
+                    s_axi_rresp_next = m_axil_rresp;
+                    s_axi_rlast_next = 1'b0;
+                    s_axi_rvalid_next = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        // last data word, return to idle
+                        m_axil_rready_next = 1'b0;
+                        s_axi_rlast_next = 1'b1;
+                        s_axi_arready_next = !m_axil_arvalid;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        // start new AXI lite read
+                        m_axil_araddr_next = addr_next;
+                        m_axil_arvalid_next = 1'b1;
+                        m_axil_rready_next = 1'b0;
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_READ: begin
+                m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
+
+                if (m_axil_rready && m_axil_rvalid) begin
+                    s_axi_rid_next = id_reg;
+                    data_next = m_axil_rdata;
+                    resp_next = m_axil_rresp;
+                    s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
+                    s_axi_rresp_next = m_axil_rresp;
+                    s_axi_rlast_next = 1'b0;
+                    s_axi_rvalid_next = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        m_axil_rready_next = 1'b0;
+                        s_axi_arready_next = !m_axil_arvalid;
+                        s_axi_rlast_next = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        // start new AXI lite read
+                        m_axil_araddr_next = addr_next;
+                        m_axil_arvalid_next = 1'b1;
+                        m_axil_rready_next = 1'b0;
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        m_axil_rready_next = 1'b0;
+                        state_next = STATE_DATA_SPLIT;
+                    end
+                end else begin
+                    state_next = STATE_DATA_READ;
+                end
+            end
+            STATE_DATA_SPLIT: begin
+                m_axil_rready_next = 1'b0;
+
+                if (s_axi_rready || !s_axi_rvalid) begin
+                    s_axi_rid_next = id_reg;
+                    s_axi_rdata_next = data_reg >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
+                    s_axi_rresp_next = resp_reg;
+                    s_axi_rlast_next = 1'b0;
+                    s_axi_rvalid_next = 1'b1;
+                    burst_next = burst_reg - 1;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0) begin
+                        s_axi_arready_next = !m_axil_arvalid;
+                        s_axi_rlast_next = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        // start new AXI lite read
+                        m_axil_araddr_next = addr_next;
+                        m_axil_arvalid_next = 1'b1;
+                        m_axil_rready_next = 1'b0;
+                        state_next = STATE_DATA_READ;
+                    end else begin
+                        state_next = STATE_DATA_SPLIT;
+                    end
+                end else begin
+                    state_next = STATE_DATA_SPLIT;
+                end
+            end
+        endcase
+    end else begin
+        // master output is narrower; merge reads and possibly split burst
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_arready_next = !m_axil_arvalid;
+
+                resp_next = 2'd0;
+
+                if (s_axi_arready && s_axi_arvalid) begin
+                    s_axi_arready_next = 1'b0;
+                    id_next = s_axi_arid;
+                    m_axil_araddr_next = s_axi_araddr;
+                    addr_next = s_axi_araddr;
+                    burst_next = s_axi_arlen;
+                    burst_size_next = s_axi_arsize;
+                    if (s_axi_arsize > AXIL_BURST_SIZE) begin
+                        // need to adjust burst size
+                        if ({s_axi_arlen, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-s_axi_arsize) > 255) begin
+                            // limit burst length to max
+                            master_burst_next = 8'd255;
+                        end else begin
+                            master_burst_next = {s_axi_arlen, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-s_axi_arsize);
+                        end
+                        master_burst_size_next = AXIL_BURST_SIZE;
+                    end else begin
+                        // pass through narrow (enough) burst
+                        master_burst_next = s_axi_arlen;
+                        master_burst_size_next = s_axi_arsize;
+                    end
+                    m_axil_arprot_next = s_axi_arprot;
+                    m_axil_arvalid_next = 1'b1;
+                    m_axil_rready_next = 1'b0;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
+
+                if (m_axil_rready && m_axil_rvalid) begin
+                    data_next[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
+                    if (m_axil_rresp) begin
+                        resp_next = m_axil_rresp;
+                    end
+                    s_axi_rid_next = id_reg;
+                    s_axi_rdata_next = data_next;
+                    s_axi_rresp_next = resp_next;
+                    s_axi_rlast_next = 1'b0;
+                    s_axi_rvalid_next = 1'b0;
+                    master_burst_next = master_burst_reg - 1;
+                    addr_next = addr_reg + (1 << master_burst_size_reg);
+                    if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
+                        data_next = {DATA_WIDTH{1'b0}};
+                        burst_next = burst_reg - 1;
+                        s_axi_rvalid_next = 1'b1;
+                    end
+                    if (master_burst_reg == 0) begin
+                        if (burst_reg == 0) begin
+                            m_axil_rready_next = 1'b0;
+                            s_axi_rlast_next = 1'b1;
+                            s_axi_rvalid_next = 1'b1;
+                            s_axi_arready_next = !m_axil_arvalid;
+                            state_next = STATE_IDLE;
+                        end else begin
+                            // start new burst
+                            m_axil_araddr_next = addr_next;
+                            if (burst_size_reg > AXIL_BURST_SIZE) begin
+                                // need to adjust burst size
+                                if ({burst_next, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-burst_size_reg) > 255) begin
+                                    // limit burst length to max
+                                    master_burst_next = 8'd255;
+                                end else begin
+                                    master_burst_next = {burst_next, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-burst_size_reg);
+                                end
+                                master_burst_size_next = AXIL_BURST_SIZE;
+                            end else begin
+                                // pass through narrow (enough) burst
+                                master_burst_next = burst_next;
+                                master_burst_size_next = burst_size_reg;
+                            end
+                            m_axil_arvalid_next = 1'b1;
+                            m_axil_rready_next = 1'b0;
+                            state_next = STATE_DATA;
+                        end
+                    end else begin
+                        m_axil_araddr_next = addr_next;
+                        m_axil_arvalid_next = 1'b1;
+                        m_axil_rready_next = 1'b0;
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_arready_reg <= 1'b0;
+        s_axi_rvalid_reg <= 1'b0;
+        m_axil_arvalid_reg <= 1'b0;
+        m_axil_rready_reg <= 1'b0;
+    end else begin
+        state_reg <= state_next;
+        s_axi_arready_reg <= s_axi_arready_next;
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+        m_axil_arvalid_reg <= m_axil_arvalid_next;
+        m_axil_rready_reg <= m_axil_rready_next;
+    end
+
+    id_reg <= id_next;
+    addr_reg <= addr_next;
+    data_reg <= data_next;
+    resp_reg <= resp_next;
+    burst_reg <= burst_next;
+    burst_size_reg <= burst_size_next;
+    master_burst_reg <= master_burst_next;
+    master_burst_size_reg <= master_burst_size_next;
+
+    s_axi_rid_reg <= s_axi_rid_next;
+    s_axi_rdata_reg <= s_axi_rdata_next;
+    s_axi_rresp_reg <= s_axi_rresp_next;
+    s_axi_rlast_reg <= s_axi_rlast_next;
+    m_axil_araddr_reg <= m_axil_araddr_next;
+    m_axil_arprot_reg <= m_axil_arprot_next;
+end
+
+endmodule

corundum/lib/axi/rtl/axi_axil_adapter_wr.v

+/*
+
+Copyright (c) 2019 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 to AXI4-Lite adapter (write)
+ */
+module axi_axil_adapter_wr #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) AXI interface data bus in bits
+    parameter AXI_DATA_WIDTH = 32,
+    // Width of input (slave) AXI interface wstrb (width of data bus in words)
+    parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
+    // Width of AXI ID signal
+    parameter AXI_ID_WIDTH = 8,
+    // Width of output (master) AXI lite interface data bus in bits
+    parameter AXIL_DATA_WIDTH = 32,
+    // Width of output (master) AXI lite interface wstrb (width of data bus in words)
+    parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0
+)
+(
+    input  wire                        clk,
+    input  wire                        rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [AXI_ID_WIDTH-1:0]     s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]       s_axi_awaddr,
+    input  wire [7:0]                  s_axi_awlen,
+    input  wire [2:0]                  s_axi_awsize,
+    input  wire [1:0]                  s_axi_awburst,
+    input  wire                        s_axi_awlock,
+    input  wire [3:0]                  s_axi_awcache,
+    input  wire [2:0]                  s_axi_awprot,
+    input  wire                        s_axi_awvalid,
+    output wire                        s_axi_awready,
+    input  wire [AXI_DATA_WIDTH-1:0]   s_axi_wdata,
+    input  wire [AXI_STRB_WIDTH-1:0]   s_axi_wstrb,
+    input  wire                        s_axi_wlast,
+    input  wire                        s_axi_wvalid,
+    output wire                        s_axi_wready,
+    output wire [AXI_ID_WIDTH-1:0]     s_axi_bid,
+    output wire [1:0]                  s_axi_bresp,
+    output wire                        s_axi_bvalid,
+    input  wire                        s_axi_bready,
+
+    /*
+     * AXI lite master interface
+     */
+    output wire [ADDR_WIDTH-1:0]       m_axil_awaddr,
+    output wire [2:0]                  m_axil_awprot,
+    output wire                        m_axil_awvalid,
+    input  wire                        m_axil_awready,
+    output wire [AXIL_DATA_WIDTH-1:0]  m_axil_wdata,
+    output wire [AXIL_STRB_WIDTH-1:0]  m_axil_wstrb,
+    output wire                        m_axil_wvalid,
+    input  wire                        m_axil_wready,
+    input  wire [1:0]                  m_axil_bresp,
+    input  wire                        m_axil_bvalid,
+    output wire                        m_axil_bready
+);
+
+parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH);
+parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH);
+parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
+parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH;
+parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
+parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH;
+parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
+parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH);
+
+// output bus is wider
+parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH;
+parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH;
+parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH;
+// required number of segments in wider bus
+parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH);
+// data width and keep width per segment
+parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
+parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
+
+// bus width assertions
+initial begin
+    if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
+        $error("Error: AXI slave interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
+        $error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
+        $error("Error: word size mismatch (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
+        $error("Error: AXI slave interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
+        $error("Error: AXI lite master interface word width must be even power of two (instance %m)");
+        $finish;
+    end
+end
+
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DATA = 2'd1,
+    STATE_DATA_2 = 2'd2,
+    STATE_RESP = 2'd3;
+
+reg [1:0] state_reg = STATE_IDLE, state_next;
+
+reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next;
+reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
+reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
+reg [STRB_WIDTH-1:0] strb_reg = {STRB_WIDTH{1'b0}}, strb_next;
+reg [7:0] burst_reg = 8'd0, burst_next;
+reg [2:0] burst_size_reg = 3'd0, burst_size_next;
+reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
+reg burst_active_reg = 1'b0, burst_active_next;
+reg convert_burst_reg = 1'b0, convert_burst_next;
+reg first_transfer_reg = 1'b0, first_transfer_next;
+reg last_segment_reg = 1'b0, last_segment_next;
+
+reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
+reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
+reg [AXI_ID_WIDTH-1:0] s_axi_bid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_bid_next;
+reg [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
+reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
+
+reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_awaddr_next;
+reg [2:0] m_axil_awprot_reg = 3'd0, m_axil_awprot_next;
+reg m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
+reg [AXIL_DATA_WIDTH-1:0] m_axil_wdata_reg = {AXIL_DATA_WIDTH{1'b0}}, m_axil_wdata_next;
+reg [AXIL_STRB_WIDTH-1:0] m_axil_wstrb_reg = {AXIL_STRB_WIDTH{1'b0}}, m_axil_wstrb_next;
+reg m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
+reg m_axil_bready_reg = 1'b0, m_axil_bready_next;
+
+assign s_axi_awready = s_axi_awready_reg;
+assign s_axi_wready = s_axi_wready_reg;
+assign s_axi_bid = s_axi_bid_reg;
+assign s_axi_bresp = s_axi_bresp_reg;
+assign s_axi_bvalid = s_axi_bvalid_reg;
+
+assign m_axil_awaddr = m_axil_awaddr_reg;
+//assign m_axil_awlen = m_axil_awlen_reg;
+//assign m_axil_awsize = m_axil_awsize_reg;
+//assign m_axil_awburst = m_axil_awburst_reg;
+assign m_axil_awprot = m_axil_awprot_reg;
+assign m_axil_awvalid = m_axil_awvalid_reg;
+assign m_axil_wdata = m_axil_wdata_reg;
+assign m_axil_wstrb = m_axil_wstrb_reg;
+assign m_axil_wvalid = m_axil_wvalid_reg;
+assign m_axil_bready = m_axil_bready_reg;
+
+integer i;
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    id_next = id_reg;
+    addr_next = addr_reg;
+    data_next = data_reg;
+    strb_next = strb_reg;
+    burst_next = burst_reg;
+    burst_size_next = burst_size_reg;
+    master_burst_size_next = master_burst_size_reg;
+    burst_active_next = burst_active_reg;
+    convert_burst_next = convert_burst_reg;
+    first_transfer_next = first_transfer_reg;
+    last_segment_next = last_segment_reg;
+
+    s_axi_awready_next = 1'b0;
+    s_axi_wready_next = 1'b0;
+    s_axi_bid_next = s_axi_bid_reg;
+    s_axi_bresp_next = s_axi_bresp_reg;
+    s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
+    m_axil_awaddr_next = m_axil_awaddr_reg;
+    m_axil_awprot_next = m_axil_awprot_reg;
+    m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_awready;
+    m_axil_wdata_next = m_axil_wdata_reg;
+    m_axil_wstrb_next = m_axil_wstrb_reg;
+    m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wready;
+    m_axil_bready_next = 1'b0;
+
+    if (SEGMENT_COUNT == 1) begin
+        // master output is same width; direct transfer with no splitting/merging
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axil_awvalid;
+                first_transfer_next = 1'b1;
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axil_awaddr_next = s_axi_awaddr;
+                    addr_next = s_axi_awaddr;
+                    burst_next = s_axi_awlen;
+                    burst_size_next = s_axi_awsize;
+                    burst_active_next = 1'b1;
+                    m_axil_awprot_next = s_axi_awprot;
+                    m_axil_awvalid_next = 1'b1;
+                    s_axi_wready_next = !m_axil_wvalid;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer write data
+                s_axi_wready_next = !m_axil_wvalid;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    m_axil_wdata_next = s_axi_wdata;
+                    m_axil_wstrb_next = s_axi_wstrb;
+                    m_axil_wvalid_next = 1'b1;
+                    burst_next = burst_reg - 1;
+                    burst_active_next = burst_reg != 0;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    s_axi_wready_next = 1'b0;
+                    m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+                    state_next = STATE_RESP;
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+
+                if (m_axil_bready && m_axil_bvalid) begin
+                    m_axil_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    first_transfer_next = 1'b0;
+                    if (first_transfer_reg || m_axil_bresp != 0) begin
+                        s_axi_bresp_next = m_axil_bresp;
+                    end
+                    if (burst_active_reg) begin
+                        // burst on slave interface still active; start new AXI lite write
+                        m_axil_awaddr_next = addr_reg;
+                        m_axil_awvalid_next = 1'b1;
+                        s_axi_wready_next = !m_axil_wvalid;
+                        state_next = STATE_DATA;
+                    end else begin
+                        // burst on slave interface finished; return to idle
+                        s_axi_bvalid_next = 1'b1;
+                        s_axi_awready_next = !m_axil_awvalid;
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end else if (EXPAND) begin
+        // master output is wider; merge writes
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axil_awvalid;
+
+                first_transfer_next = 1'b1;
+
+                data_next = {DATA_WIDTH{1'b0}};
+                strb_next = {STRB_WIDTH{1'b0}};
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axil_awaddr_next = s_axi_awaddr;
+                    addr_next = s_axi_awaddr;
+                    burst_next = s_axi_awlen;
+                    burst_size_next = s_axi_awsize;
+                    if (CONVERT_BURST && s_axi_awcache[1] && (CONVERT_NARROW_BURST || s_axi_awsize == AXI_BURST_SIZE)) begin
+                        // merge writes
+                        // require CONVERT_BURST and awcache[1] set
+                        convert_burst_next = 1'b1;
+                        master_burst_size_next = AXIL_BURST_SIZE;
+                        state_next = STATE_DATA_2;
+                    end else begin
+                        // output narrow burst
+                        convert_burst_next = 1'b0;
+                        master_burst_size_next = s_axi_awsize;
+                        state_next = STATE_DATA;
+                    end
+                    m_axil_awprot_next = s_axi_awprot;
+                    m_axil_awvalid_next = 1'b1;
+                    s_axi_wready_next = !m_axil_wvalid;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                // data state; transfer write data
+                s_axi_wready_next = !m_axil_wvalid || m_axil_wready;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    m_axil_wdata_next = {(AXIL_WORD_WIDTH/AXI_WORD_WIDTH){s_axi_wdata}};
+                    m_axil_wstrb_next = s_axi_wstrb << (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_STRB_WIDTH);
+                    m_axil_wvalid_next = 1'b1;
+                    burst_next = burst_reg - 1;
+                    burst_active_next = burst_reg != 0;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    s_axi_wready_next = 1'b0;
+                    m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+                    state_next = STATE_RESP;
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_2: begin
+                s_axi_wready_next = !m_axil_wvalid;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    if (CONVERT_NARROW_BURST) begin
+                        for (i = 0; i < AXI_WORD_WIDTH; i = i + 1) begin
+                            if (s_axi_wstrb[i]) begin
+                                data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE];
+                                strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1;
+                            end
+                        end
+                    end else begin
+                        data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
+                        strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
+                    end
+                    m_axil_wdata_next = data_next;
+                    m_axil_wstrb_next = strb_next;
+                    burst_next = burst_reg - 1;
+                    burst_active_next = burst_reg != 0;
+                    addr_next = addr_reg + (1 << burst_size_reg);
+                    if (burst_reg == 0 || addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
+                        data_next = {DATA_WIDTH{1'b0}};
+                        strb_next = {STRB_WIDTH{1'b0}};
+                        m_axil_wvalid_next = 1'b1;
+                        s_axi_wready_next = 1'b0;
+                        m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+                        state_next = STATE_RESP;
+                    end else begin
+                        state_next = STATE_DATA_2;
+                    end
+                end else begin
+                    state_next = STATE_DATA_2;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+
+                if (m_axil_bready && m_axil_bvalid) begin
+                    m_axil_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    first_transfer_next = 1'b0;
+                    if (first_transfer_reg || m_axil_bresp != 0) begin
+                        s_axi_bresp_next = m_axil_bresp;
+                    end
+                    if (burst_active_reg) begin
+                        // burst on slave interface still active; start new AXI lite write
+                        m_axil_awaddr_next = addr_reg;
+                        m_axil_awvalid_next = 1'b1;
+                        s_axi_wready_next = !m_axil_wvalid || m_axil_wready;
+                        if (convert_burst_reg) begin
+                            state_next = STATE_DATA_2;
+                        end else begin
+                            state_next = STATE_DATA;
+                        end
+                    end else begin
+                        // burst on slave interface finished; return to idle
+                        s_axi_bvalid_next = 1'b1;
+                        s_axi_awready_next = !m_axil_awvalid;
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end else begin
+        // master output is narrower; split writes, and possibly split burst
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state; wait for new burst
+                s_axi_awready_next = !m_axil_awvalid;
+
+                first_transfer_next = 1'b1;
+
+                if (s_axi_awready && s_axi_awvalid) begin
+                    s_axi_awready_next = 1'b0;
+                    id_next = s_axi_awid;
+                    m_axil_awaddr_next = s_axi_awaddr;
+                    addr_next = s_axi_awaddr;
+                    burst_next = s_axi_awlen;
+                    burst_size_next = s_axi_awsize;
+                    burst_active_next = 1'b1;
+                    if (s_axi_awsize > AXIL_BURST_SIZE) begin
+                        // need to adjust burst size
+                        master_burst_size_next = AXIL_BURST_SIZE;
+                    end else begin
+                        // pass through narrow (enough) burst
+                        master_burst_size_next = s_axi_awsize;
+                    end
+                    m_axil_awprot_next = s_axi_awprot;
+                    m_axil_awvalid_next = 1'b1;
+                    s_axi_wready_next = !m_axil_wvalid;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                s_axi_wready_next = !m_axil_wvalid;
+
+                if (s_axi_wready && s_axi_wvalid) begin
+                    data_next = s_axi_wdata;
+                    strb_next = s_axi_wstrb;
+                    m_axil_wdata_next = s_axi_wdata >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
+                    m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
+                    m_axil_wvalid_next = 1'b1;
+                    burst_next = burst_reg - 1;
+                    burst_active_next = burst_reg != 0;
+                    addr_next = addr_reg + (1 << master_burst_size_reg);
+                    last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
+                    s_axi_wready_next = 1'b0;
+                    m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+                    state_next = STATE_RESP;
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+            STATE_DATA_2: begin
+                s_axi_wready_next = 1'b0;
+
+                if (!m_axil_wvalid || m_axil_wready) begin
+                    m_axil_wdata_next = data_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
+                    m_axil_wstrb_next = strb_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
+                    m_axil_wvalid_next = 1'b1;
+                    addr_next = addr_reg + (1 << master_burst_size_reg);
+                    last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
+                    s_axi_wready_next = 1'b0;
+                    m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+                    state_next = STATE_RESP;
+                end else begin
+                    state_next = STATE_DATA_2;
+                end
+            end
+            STATE_RESP: begin
+                // resp state; transfer write response
+                m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
+
+                if (m_axil_bready && m_axil_bvalid) begin
+                    first_transfer_next = 1'b0;
+                    m_axil_bready_next = 1'b0;
+                    s_axi_bid_next = id_reg;
+                    if (first_transfer_reg || m_axil_bresp != 0) begin
+                        s_axi_bresp_next = m_axil_bresp;
+                    end
+                    if (burst_active_reg || !last_segment_reg) begin
+                        // burst on slave interface still active; start new burst
+                        m_axil_awaddr_next = addr_reg;
+                        m_axil_awvalid_next = 1'b1;
+                        if (last_segment_reg) begin
+                            s_axi_wready_next = !m_axil_wvalid;
+                            state_next = STATE_DATA;
+                        end else begin
+                            s_axi_wready_next = 1'b0;
+                            state_next = STATE_DATA_2;
+                        end
+                    end else begin
+                        // burst on slave interface finished; return to idle
+                        s_axi_bvalid_next = 1'b1;
+                        s_axi_awready_next = !m_axil_awvalid;
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    state_next = STATE_RESP;
+                end
+            end
+        endcase
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_awready_reg <= 1'b0;
+        s_axi_wready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+        m_axil_awvalid_reg <= 1'b0;
+        m_axil_wvalid_reg <= 1'b0;
+        m_axil_bready_reg <= 1'b0;
+    end else begin
+        state_reg <= state_next;
+        s_axi_awready_reg <= s_axi_awready_next;
+        s_axi_wready_reg <= s_axi_wready_next;
+        s_axi_bvalid_reg <= s_axi_bvalid_next;
+        m_axil_awvalid_reg <= m_axil_awvalid_next;
+        m_axil_wvalid_reg <= m_axil_wvalid_next;
+        m_axil_bready_reg <= m_axil_bready_next;
+    end
+
+    id_reg <= id_next;
+    addr_reg <= addr_next;
+    data_reg <= data_next;
+    strb_reg <= strb_next;
+    burst_reg <= burst_next;
+    burst_size_reg <= burst_size_next;
+    master_burst_size_reg <= master_burst_size_next;
+    burst_active_reg <= burst_active_next;
+    convert_burst_reg <= convert_burst_next;
+    first_transfer_reg <= first_transfer_next;
+    last_segment_reg <= last_segment_next;
+
+    s_axi_bid_reg <= s_axi_bid_next;
+    s_axi_bresp_reg <= s_axi_bresp_next;
+    m_axil_awaddr_reg <= m_axil_awaddr_next;
+    m_axil_awprot_reg <= m_axil_awprot_next;
+    m_axil_wdata_reg <= m_axil_wdata_next;
+    m_axil_wstrb_reg <= m_axil_wstrb_next;
+end
+
+endmodule

corundum/lib/axi/rtl/axi_cdma.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 Central DMA
+ */
+module axi_cdma #
+(
+    // Width of data bus in bits
+    parameter AXI_DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter AXI_ADDR_WIDTH = 16,
+    // Width of wstrb (width of data bus in words)
+    parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
+    // Width of AXI ID signal
+    parameter AXI_ID_WIDTH = 8,
+    // Maximum AXI burst length to generate
+    parameter AXI_MAX_BURST_LEN = 16,
+    // Width of length field
+    parameter LEN_WIDTH = 20,
+    // Width of tag field
+    parameter TAG_WIDTH = 8,
+    // Enable support for unaligned transfers
+    parameter ENABLE_UNALIGNED = 0
+)
+(
+    input  wire                       clk,
+    input  wire                       rst,
+
+    /*
+     * AXI descriptor input
+     */
+    input  wire [AXI_ADDR_WIDTH-1:0]  s_axis_desc_read_addr,
+    input  wire [AXI_ADDR_WIDTH-1:0]  s_axis_desc_write_addr,
+    input  wire [LEN_WIDTH-1:0]       s_axis_desc_len,
+    input  wire [TAG_WIDTH-1:0]       s_axis_desc_tag,
+    input  wire                       s_axis_desc_valid,
+    output wire                       s_axis_desc_ready,
+
+    /*
+     * AXI descriptor status output
+     */
+    output wire [TAG_WIDTH-1:0]       m_axis_desc_status_tag,
+    output wire                       m_axis_desc_status_valid,
+
+    /*
+     * AXI write master interface
+     */
+    output wire [AXI_ID_WIDTH-1:0]    m_axi_awid,
+    output wire [AXI_ADDR_WIDTH-1:0]  m_axi_awaddr,
+    output wire [7:0]                 m_axi_awlen,
+    output wire [2:0]                 m_axi_awsize,
+    output wire [1:0]                 m_axi_awburst,
+    output wire                       m_axi_awlock,
+    output wire [3:0]                 m_axi_awcache,
+    output wire [2:0]                 m_axi_awprot,
+    output wire                       m_axi_awvalid,
+    input  wire                       m_axi_awready,
+    output wire [AXI_DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [AXI_STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                       m_axi_wlast,
+    output wire                       m_axi_wvalid,
+    input  wire                       m_axi_wready,
+    input  wire [AXI_ID_WIDTH-1:0]    m_axi_bid,
+    input  wire [1:0]                 m_axi_bresp,
+    input  wire                       m_axi_bvalid,
+    output wire                       m_axi_bready,
+
+    /*
+     * AXI read master interface
+     */
+    output wire [AXI_ID_WIDTH-1:0]    m_axi_arid,
+    output wire [AXI_ADDR_WIDTH-1:0]  m_axi_araddr,
+    output wire [7:0]                 m_axi_arlen,
+    output wire [2:0]                 m_axi_arsize,
+    output wire [1:0]                 m_axi_arburst,
+    output wire                       m_axi_arlock,
+    output wire [3:0]                 m_axi_arcache,
+    output wire [2:0]                 m_axi_arprot,
+    output wire                       m_axi_arvalid,
+    input  wire                       m_axi_arready,
+    input  wire [AXI_ID_WIDTH-1:0]    m_axi_rid,
+    input  wire [AXI_DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]                 m_axi_rresp,
+    input  wire                       m_axi_rlast,
+    input  wire                       m_axi_rvalid,
+    output wire                       m_axi_rready,
+
+    /*
+     * Configuration
+     */
+    input  wire                       enable
+);
+
+parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
+parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
+parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
+parameter AXI_MAX_BURST_SIZE = AXI_MAX_BURST_LEN << AXI_BURST_SIZE;
+
+parameter OFFSET_WIDTH = AXI_STRB_WIDTH > 1 ? $clog2(AXI_STRB_WIDTH) : 1;
+parameter OFFSET_MASK = AXI_STRB_WIDTH > 1 ? {OFFSET_WIDTH{1'b1}} : 0;
+parameter ADDR_MASK = {AXI_ADDR_WIDTH{1'b1}} << $clog2(AXI_STRB_WIDTH);
+parameter CYCLE_COUNT_WIDTH = LEN_WIDTH - AXI_BURST_SIZE + 1;
+
+parameter STATUS_FIFO_ADDR_WIDTH = 5;
+
+// bus width assertions
+initial begin
+    if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
+        $error("Error: AXI data width not evenly divisble (instance %m)");
+        $finish;
+    end
+
+    if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
+        $error("Error: AXI word width must be even power of two (instance %m)");
+        $finish;
+    end
+
+    if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
+        $error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
+        $finish;
+    end
+end
+
+localparam [1:0]
+    READ_STATE_IDLE = 2'd0,
+    READ_STATE_START = 2'd1,
+    READ_STATE_REQ = 2'd2;
+
+reg [1:0] read_state_reg = READ_STATE_IDLE, read_state_next;
+
+localparam [0:0]
+    AXI_STATE_IDLE = 1'd0,
+    AXI_STATE_WRITE = 1'd1;
+
+reg [0:0] axi_state_reg = AXI_STATE_IDLE, axi_state_next;
+
+// datapath control signals
+reg transfer_in_save;
+reg axi_cmd_ready;
+reg status_fifo_we;
+
+reg [AXI_ADDR_WIDTH-1:0] read_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, read_addr_next;
+reg [AXI_ADDR_WIDTH-1:0] write_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, write_addr_next;
+reg [LEN_WIDTH-1:0] op_word_count_reg = {LEN_WIDTH{1'b0}}, op_word_count_next;
+reg [LEN_WIDTH-1:0] tr_word_count_reg = {LEN_WIDTH{1'b0}}, tr_word_count_next;
+reg [LEN_WIDTH-1:0] axi_word_count_reg = {LEN_WIDTH{1'b0}}, axi_word_count_next;
+
+reg [AXI_ADDR_WIDTH-1:0] axi_cmd_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, axi_cmd_addr_next;
+reg [OFFSET_WIDTH-1:0] axi_cmd_offset_reg = {OFFSET_WIDTH{1'b0}}, axi_cmd_offset_next;
+reg [OFFSET_WIDTH-1:0] axi_cmd_first_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, axi_cmd_first_cycle_offset_next;
+reg [OFFSET_WIDTH-1:0] axi_cmd_last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, axi_cmd_last_cycle_offset_next;
+reg [CYCLE_COUNT_WIDTH-1:0] axi_cmd_input_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, axi_cmd_input_cycle_count_next;
+reg [CYCLE_COUNT_WIDTH-1:0] axi_cmd_output_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, axi_cmd_output_cycle_count_next;
+reg axi_cmd_bubble_cycle_reg = 1'b0, axi_cmd_bubble_cycle_next;
+reg axi_cmd_last_transfer_reg = 1'b0, axi_cmd_last_transfer_next;
+reg [TAG_WIDTH-1:0] axi_cmd_tag_reg = {TAG_WIDTH{1'b0}}, axi_cmd_tag_next;
+reg axi_cmd_valid_reg = 1'b0, axi_cmd_valid_next;
+
+reg [OFFSET_WIDTH-1:0] offset_reg = {OFFSET_WIDTH{1'b0}}, offset_next;
+reg [OFFSET_WIDTH-1:0] first_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, first_cycle_offset_next;
+reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
+reg [CYCLE_COUNT_WIDTH-1:0] input_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, input_cycle_count_next;
+reg [CYCLE_COUNT_WIDTH-1:0] output_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, output_cycle_count_next;
+reg input_active_reg = 1'b0, input_active_next;
+reg output_active_reg = 1'b0, output_active_next;
+reg bubble_cycle_reg = 1'b0, bubble_cycle_next;
+reg first_input_cycle_reg = 1'b0, first_input_cycle_next;
+reg first_output_cycle_reg = 1'b0, first_output_cycle_next;
+reg output_last_cycle_reg = 1'b0, output_last_cycle_next;
+reg last_transfer_reg = 1'b0, last_transfer_next;
+
+reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}}, tag_next;
+
+reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_wr_ptr_reg = 0, status_fifo_wr_ptr_next;
+reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_rd_ptr_reg = 0, status_fifo_rd_ptr_next;
+reg [TAG_WIDTH-1:0] status_fifo_tag[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
+reg status_fifo_last[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
+reg [TAG_WIDTH-1:0] status_fifo_wr_tag;
+reg status_fifo_wr_last;
+
+reg s_axis_desc_ready_reg = 1'b0, s_axis_desc_ready_next;
+
+reg [TAG_WIDTH-1:0] m_axis_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_desc_status_tag_next;
+reg m_axis_desc_status_valid_reg = 1'b0, m_axis_desc_status_valid_next;
+
+reg [AXI_ADDR_WIDTH-1:0] m_axi_araddr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axi_araddr_next;
+reg [7:0] m_axi_arlen_reg = 8'd0, m_axi_arlen_next;
+reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
+reg m_axi_rready_reg = 1'b0, m_axi_rready_next;
+
+reg [AXI_ADDR_WIDTH-1:0] m_axi_awaddr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axi_awaddr_next;
+reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;
+reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
+reg m_axi_bready_reg = 1'b0, m_axi_bready_next;
+
+reg [AXI_DATA_WIDTH-1:0] save_axi_rdata_reg = {AXI_DATA_WIDTH{1'b0}};
+
+wire [AXI_DATA_WIDTH-1:0] shift_axi_rdata = {m_axi_rdata, save_axi_rdata_reg} >> ((AXI_STRB_WIDTH-offset_reg)*AXI_WORD_SIZE);
+
+// internal datapath
+reg  [AXI_DATA_WIDTH-1:0] m_axi_wdata_int;
+reg  [AXI_STRB_WIDTH-1:0] m_axi_wstrb_int;
+reg                       m_axi_wlast_int;
+reg                       m_axi_wvalid_int;
+reg                       m_axi_wready_int_reg = 1'b0;
+wire                      m_axi_wready_int_early;
+
+assign s_axis_desc_ready = s_axis_desc_ready_reg;
+
+assign m_axis_desc_status_tag = m_axis_desc_status_tag_reg;
+assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
+
+assign m_axi_arid = {AXI_ID_WIDTH{1'b0}};
+assign m_axi_araddr = m_axi_araddr_reg;
+assign m_axi_arlen = m_axi_arlen_reg;
+assign m_axi_arsize = AXI_BURST_SIZE;
+assign m_axi_arburst = 2'b01;
+assign m_axi_arlock = 1'b0;
+assign m_axi_arcache = 4'b0011;
+assign m_axi_arprot = 3'b010;
+assign m_axi_arvalid = m_axi_arvalid_reg;
+assign m_axi_rready = m_axi_rready_reg;
+
+assign m_axi_awid = {AXI_ID_WIDTH{1'b0}};
+assign m_axi_awaddr = m_axi_awaddr_reg;
+assign m_axi_awlen = m_axi_awlen_reg;
+assign m_axi_awsize = AXI_BURST_SIZE;
+assign m_axi_awburst = 2'b01;
+assign m_axi_awlock = 1'b0;
+assign m_axi_awcache = 4'b0011;
+assign m_axi_awprot = 3'b010;
+assign m_axi_awvalid = m_axi_awvalid_reg;
+assign m_axi_bready = m_axi_bready_reg;
+
+wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_max_burst = read_addr_reg + AXI_MAX_BURST_SIZE;
+wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_op_count = read_addr_reg + op_word_count_reg;
+wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_axi_count = read_addr_reg + axi_word_count_reg;
+
+wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_max_burst = write_addr_reg + AXI_MAX_BURST_SIZE;
+wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_op_count = write_addr_reg + op_word_count_reg;
+wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_axi_count = write_addr_reg + axi_word_count_reg;
+
+always @* begin
+    read_state_next = READ_STATE_IDLE;
+
+    s_axis_desc_ready_next = 1'b0;
+
+    m_axi_araddr_next = m_axi_araddr_reg;
+    m_axi_arlen_next = m_axi_arlen_reg;
+    m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_arready;
+
+    read_addr_next = read_addr_reg;
+    write_addr_next = write_addr_reg;
+    op_word_count_next = op_word_count_reg;
+    tr_word_count_next = tr_word_count_reg;
+    axi_word_count_next = axi_word_count_reg;
+
+    axi_cmd_addr_next = axi_cmd_addr_reg;
+    axi_cmd_offset_next = axi_cmd_offset_reg;
+    axi_cmd_first_cycle_offset_next = axi_cmd_first_cycle_offset_reg;
+    axi_cmd_last_cycle_offset_next = axi_cmd_last_cycle_offset_reg;
+    axi_cmd_input_cycle_count_next = axi_cmd_input_cycle_count_reg;
+    axi_cmd_output_cycle_count_next = axi_cmd_output_cycle_count_reg;
+    axi_cmd_bubble_cycle_next = axi_cmd_bubble_cycle_reg;
+    axi_cmd_last_transfer_next = axi_cmd_last_transfer_reg;
+    axi_cmd_tag_next = axi_cmd_tag_reg;
+    axi_cmd_valid_next = axi_cmd_valid_reg && !axi_cmd_ready;
+
+    case (read_state_reg)
+        READ_STATE_IDLE: begin
+            // idle state - load new descriptor to start operation
+            s_axis_desc_ready_next = !axi_cmd_valid_reg && enable;
+
+            if (s_axis_desc_ready && s_axis_desc_valid) begin
+                if (ENABLE_UNALIGNED) begin
+                    read_addr_next = s_axis_desc_read_addr;
+                    write_addr_next = s_axis_desc_write_addr;
+                end else begin
+                    read_addr_next = s_axis_desc_read_addr & ADDR_MASK;
+                    write_addr_next = s_axis_desc_write_addr & ADDR_MASK;
+                end
+                axi_cmd_tag_next = s_axis_desc_tag;
+                op_word_count_next = s_axis_desc_len;
+
+                s_axis_desc_ready_next = 1'b0;
+                read_state_next = READ_STATE_START;
+            end else begin
+                read_state_next = READ_STATE_IDLE;
+            end
+        end
+        READ_STATE_START: begin
+            // start state - compute write length
+            if (!axi_cmd_valid_reg) begin
+                if (op_word_count_reg <= AXI_MAX_BURST_SIZE - (write_addr_reg & OFFSET_MASK)) begin
+                    // packet smaller than max burst size
+                    if (write_addr_reg[12] != write_addr_plus_op_count[12]) begin
+                        // crosses 4k boundary
+                        axi_word_count_next = 13'h1000 - write_addr_reg[11:0];
+                    end else begin
+                        // does not cross 4k boundary
+                        axi_word_count_next = op_word_count_reg;
+                    end
+                end else begin
+                    // packet larger than max burst size
+                    if (write_addr_reg[12] != write_addr_plus_max_burst[12]) begin
+                        // crosses 4k boundary
+                        axi_word_count_next = 13'h1000 - write_addr_reg[11:0];
+                    end else begin
+                        // does not cross 4k boundary
+                        axi_word_count_next = AXI_MAX_BURST_SIZE - (write_addr_reg & OFFSET_MASK);
+                    end
+                end
+
+                write_addr_next = write_addr_reg + axi_word_count_next;
+                op_word_count_next = op_word_count_reg - axi_word_count_next;
+
+                axi_cmd_addr_next = write_addr_reg;
+                if (ENABLE_UNALIGNED) begin
+                    axi_cmd_input_cycle_count_next = (axi_word_count_next + (read_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
+                    axi_cmd_output_cycle_count_next = (axi_word_count_next + (write_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
+                    axi_cmd_offset_next = (write_addr_reg & OFFSET_MASK) - (read_addr_reg & OFFSET_MASK);
+                    axi_cmd_bubble_cycle_next = (read_addr_reg & OFFSET_MASK) > (write_addr_reg & OFFSET_MASK);
+                    axi_cmd_first_cycle_offset_next = write_addr_reg & OFFSET_MASK;
+                    axi_cmd_last_cycle_offset_next = axi_cmd_first_cycle_offset_next + axi_word_count_next & OFFSET_MASK;
+                end else begin
+                    axi_cmd_input_cycle_count_next = (axi_word_count_next - 1) >> AXI_BURST_SIZE;
+                    axi_cmd_output_cycle_count_next = (axi_word_count_next - 1) >> AXI_BURST_SIZE;
+                    axi_cmd_offset_next = 0;
+                    axi_cmd_bubble_cycle_next = 0;
+                    axi_cmd_first_cycle_offset_next = 0;
+                    axi_cmd_last_cycle_offset_next = axi_word_count_next & OFFSET_MASK;
+                end
+                axi_cmd_last_transfer_next = op_word_count_next == 0;
+                axi_cmd_valid_next = 1'b1;
+
+                read_state_next = READ_STATE_REQ;
+            end else begin
+                read_state_next = READ_STATE_START;
+            end
+        end
+        READ_STATE_REQ: begin
+            // request state - issue AXI read requests
+            if (!m_axi_arvalid) begin
+                if (axi_word_count_reg <= AXI_MAX_BURST_SIZE - (read_addr_reg & OFFSET_MASK)) begin
+                    // packet smaller than max burst size
+                    if (read_addr_reg[12] != read_addr_plus_axi_count[12]) begin
+                        // crosses 4k boundary
+                        tr_word_count_next = 13'h1000 - read_addr_reg[11:0];
+                    end else begin
+                        // does not cross 4k boundary
+                        tr_word_count_next = axi_word_count_reg;
+                    end
+                end else begin
+                    // packet larger than max burst size
+                    if (read_addr_reg[12] != read_addr_plus_max_burst[12]) begin
+                        // crosses 4k boundary
+                        tr_word_count_next = 13'h1000 - read_addr_reg[11:0];
+                    end else begin
+                        // does not cross 4k boundary
+                        tr_word_count_next = AXI_MAX_BURST_SIZE - (read_addr_reg & OFFSET_MASK);
+                    end
+                end
+
+                m_axi_araddr_next = read_addr_reg;
+                if (ENABLE_UNALIGNED) begin
+                    m_axi_arlen_next = (tr_word_count_next + (read_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE;
+                end else begin
+                    m_axi_arlen_next = (tr_word_count_next - 1) >> AXI_BURST_SIZE;
+                end
+                m_axi_arvalid_next = 1'b1;
+
+                read_addr_next = read_addr_reg + tr_word_count_next;
+                axi_word_count_next = axi_word_count_reg - tr_word_count_next;
+
+                if (axi_word_count_next > 0) begin
+                    read_state_next = READ_STATE_REQ;
+                end else if (op_word_count_next > 0) begin
+                    read_state_next = READ_STATE_START;
+                end else begin
+                    s_axis_desc_ready_next = !axi_cmd_valid_reg && enable;
+                    read_state_next = READ_STATE_IDLE;
+                end
+            end else begin
+                read_state_next = READ_STATE_REQ;
+            end
+        end
+    endcase
+end
+
+always @* begin
+    axi_state_next = AXI_STATE_IDLE;
+
+    m_axis_desc_status_tag_next = m_axis_desc_status_tag_reg;
+    m_axis_desc_status_valid_next = 1'b0;
+
+    m_axi_awaddr_next = m_axi_awaddr_reg;
+    m_axi_awlen_next = m_axi_awlen_reg;
+    m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_awready;
+    m_axi_wdata_int = shift_axi_rdata;
+    m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b0}};
+    m_axi_wlast_int = 1'b0;
+    m_axi_wvalid_int = 1'b0;
+    m_axi_bready_next = 1'b0;
+
+    m_axi_rready_next = 1'b0;
+
+    transfer_in_save = 1'b0;
+    axi_cmd_ready = 1'b0;
+    status_fifo_we = 1'b0;
+
+    offset_next = offset_reg;
+    first_cycle_offset_next = first_cycle_offset_reg;
+    last_cycle_offset_next = last_cycle_offset_reg;
+    input_cycle_count_next = input_cycle_count_reg;
+    output_cycle_count_next = output_cycle_count_reg;
+    input_active_next = input_active_reg;
+    output_active_next = output_active_reg;
+    bubble_cycle_next = bubble_cycle_reg;
+    first_input_cycle_next = first_input_cycle_reg;
+    first_output_cycle_next = first_output_cycle_reg;
+    output_last_cycle_next = output_last_cycle_reg;
+    last_transfer_next = last_transfer_reg;
+
+    tag_next = tag_reg;
+
+    status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg;
+
+    status_fifo_wr_tag = tag_reg;
+    status_fifo_wr_last = 1'b0;
+
+    case (axi_state_reg)
+        AXI_STATE_IDLE: begin
+            // idle state - load new descriptor to start operation
+            m_axi_rready_next = 1'b0;
+
+            // store transfer parameters
+            if (ENABLE_UNALIGNED) begin
+                offset_next = axi_cmd_offset_reg;
+                first_cycle_offset_next = axi_cmd_first_cycle_offset_reg;
+            end else begin
+                offset_next = 0;
+                first_cycle_offset_next = 0;
+            end
+            last_cycle_offset_next = axi_cmd_last_cycle_offset_reg;
+            input_cycle_count_next = axi_cmd_input_cycle_count_reg;
+            output_cycle_count_next = axi_cmd_output_cycle_count_reg;
+            bubble_cycle_next = axi_cmd_bubble_cycle_reg;
+            last_transfer_next = axi_cmd_last_transfer_reg;
+            tag_next = axi_cmd_tag_reg;
+
+            output_last_cycle_next = output_cycle_count_next == 0;
+            input_active_next = 1'b1;
+            output_active_next = 1'b1;
+            first_input_cycle_next = 1'b1;
+            first_output_cycle_next = 1'b1;
+
+            if (!m_axi_awvalid && axi_cmd_valid_reg) begin
+                axi_cmd_ready = 1'b1;
+
+                m_axi_awaddr_next = axi_cmd_addr_reg;
+                m_axi_awlen_next = axi_cmd_output_cycle_count_reg;
+                m_axi_awvalid_next = 1'b1;
+
+                m_axi_rready_next = m_axi_wready_int_early;
+                axi_state_next = AXI_STATE_WRITE;
+            end
+        end
+        AXI_STATE_WRITE: begin
+            // handle AXI read data
+            m_axi_rready_next = m_axi_wready_int_early && input_active_reg;
+
+            if (m_axi_wready_int_reg && ((m_axi_rready && m_axi_rvalid) || !input_active_reg)) begin
+                // transfer in AXI read data
+                transfer_in_save = m_axi_rready && m_axi_rvalid;
+
+                if (ENABLE_UNALIGNED && first_input_cycle_reg && bubble_cycle_reg) begin
+                    if (input_active_reg) begin
+                        input_cycle_count_next = input_cycle_count_reg - 1;
+                        input_active_next = input_cycle_count_reg > 0;
+                    end
+                    bubble_cycle_next = 1'b0;
+                    first_input_cycle_next = 1'b0;
+
+                    m_axi_rready_next = m_axi_wready_int_early && input_active_next;
+                    axi_state_next = AXI_STATE_WRITE;
+                end else begin
+                    // update counters
+                    if (input_active_reg) begin
+                        input_cycle_count_next = input_cycle_count_reg - 1;
+                        input_active_next = input_cycle_count_reg > 0;
+                    end
+                    if (output_active_reg) begin
+                        output_cycle_count_next = output_cycle_count_reg - 1;
+                        output_active_next = output_cycle_count_reg > 0;
+                    end
+                    output_last_cycle_next = output_cycle_count_next == 0;
+                    bubble_cycle_next = 1'b0;
+                    first_input_cycle_next = 1'b0;
+                    first_output_cycle_next = 1'b0;
+
+                    // pass through read data
+                    m_axi_wdata_int = shift_axi_rdata;
+                    if (first_output_cycle_reg) begin
+                        m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b1}} << first_cycle_offset_reg;
+                    end else begin
+                        m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b1}};
+                    end
+                    m_axi_wvalid_int = 1'b1;
+
+                    if (output_last_cycle_reg) begin
+                        // no more data to transfer, finish operation
+                        if (last_cycle_offset_reg > 0) begin
+                            m_axi_wstrb_int = m_axi_wstrb_int & {AXI_STRB_WIDTH{1'b1}} >> (AXI_STRB_WIDTH - last_cycle_offset_reg);
+                        end
+                        m_axi_wlast_int = 1'b1;
+
+                        status_fifo_we = 1'b1;
+                        status_fifo_wr_tag = tag_reg;
+                        status_fifo_wr_last = last_transfer_reg;
+
+                        m_axi_rready_next = 1'b0;
+                        axi_state_next = AXI_STATE_IDLE;
+                    end else begin
+                        // more cycles in AXI transfer
+                        axi_state_next = AXI_STATE_WRITE;
+                    end
+                end
+            end else begin
+                axi_state_next = AXI_STATE_WRITE;
+            end
+        end
+    endcase
+
+    if (status_fifo_rd_ptr_reg != status_fifo_wr_ptr_reg) begin
+        // status FIFO not empty
+        if (m_axi_bready && m_axi_bvalid) begin
+            // got write completion, pop and return status
+            m_axis_desc_status_tag_next = status_fifo_tag[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
+            m_axis_desc_status_valid_next = status_fifo_last[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
+            status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg + 1;
+            m_axi_bready_next = 1'b0;
+        end else begin
+            // wait for write completion
+            m_axi_bready_next = 1'b1;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        read_state_reg <= READ_STATE_IDLE;
+        axi_state_reg <= AXI_STATE_IDLE;
+        axi_cmd_valid_reg <= 1'b0;
+        s_axis_desc_ready_reg <= 1'b0;
+        m_axis_desc_status_valid_reg <= 1'b0;
+        m_axi_awvalid_reg <= 1'b0;
+        m_axi_bready_reg <= 1'b0;
+        m_axi_arvalid_reg <= 1'b0;
+        m_axi_rready_reg <= 1'b0;
+
+        status_fifo_wr_ptr_reg <= 0;
+        status_fifo_rd_ptr_reg <= 0;
+    end else begin
+        read_state_reg <= read_state_next;
+        axi_state_reg <= axi_state_next;
+        axi_cmd_valid_reg <= axi_cmd_valid_next;
+        s_axis_desc_ready_reg <= s_axis_desc_ready_next;
+        m_axis_desc_status_valid_reg <= m_axis_desc_status_valid_next;
+        m_axi_awvalid_reg <= m_axi_awvalid_next;
+        m_axi_bready_reg <= m_axi_bready_next;
+        m_axi_arvalid_reg <= m_axi_arvalid_next;
+        m_axi_rready_reg <= m_axi_rready_next;
+
+        if (status_fifo_we) begin
+            status_fifo_wr_ptr_reg <= status_fifo_wr_ptr_reg + 1;
+        end
+        status_fifo_rd_ptr_reg <= status_fifo_rd_ptr_next;
+    end
+
+    m_axis_desc_status_tag_reg <= m_axis_desc_status_tag_next;
+
+    m_axi_awaddr_reg <= m_axi_awaddr_next;
+    m_axi_awlen_reg <= m_axi_awlen_next;
+    m_axi_araddr_reg <= m_axi_araddr_next;
+    m_axi_arlen_reg <= m_axi_arlen_next;
+
+    read_addr_reg <= read_addr_next;
+    write_addr_reg <= write_addr_next;
+    op_word_count_reg <= op_word_count_next;
+    tr_word_count_reg <= tr_word_count_next;
+    axi_word_count_reg <= axi_word_count_next;
+
+    axi_cmd_addr_reg <= axi_cmd_addr_next;
+    axi_cmd_offset_reg <= axi_cmd_offset_next;
+    axi_cmd_first_cycle_offset_reg <= axi_cmd_first_cycle_offset_next;
+    axi_cmd_last_cycle_offset_reg <= axi_cmd_last_cycle_offset_next;
+    axi_cmd_input_cycle_count_reg <= axi_cmd_input_cycle_count_next;
+    axi_cmd_output_cycle_count_reg <= axi_cmd_output_cycle_count_next;
+    axi_cmd_bubble_cycle_reg <= axi_cmd_bubble_cycle_next;
+    axi_cmd_last_transfer_reg <= axi_cmd_last_transfer_next;
+    axi_cmd_tag_reg <= axi_cmd_tag_next;
+    axi_cmd_valid_reg <= axi_cmd_valid_next;
+
+    offset_reg <= offset_next;
+    first_cycle_offset_reg <= first_cycle_offset_next;
+    last_cycle_offset_reg <= last_cycle_offset_next;
+    input_cycle_count_reg <= input_cycle_count_next;
+    output_cycle_count_reg <= output_cycle_count_next;
+    input_active_reg <= input_active_next;
+    output_active_reg <= output_active_next;
+    bubble_cycle_reg <= bubble_cycle_next;
+    first_input_cycle_reg <= first_input_cycle_next;
+    first_output_cycle_reg <= first_output_cycle_next;
+    output_last_cycle_reg <= output_last_cycle_next;
+    last_transfer_reg <= last_transfer_next;
+
+    tag_reg <= tag_next;
+
+    if (transfer_in_save) begin
+        save_axi_rdata_reg <= m_axi_rdata;
+    end
+
+    if (status_fifo_we) begin
+        status_fifo_tag[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_tag;
+        status_fifo_last[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_last;
+        status_fifo_wr_ptr_reg <= status_fifo_wr_ptr_reg + 1;
+    end
+end
+
+// output datapath logic
+reg [AXI_DATA_WIDTH-1:0] m_axi_wdata_reg  = {AXI_DATA_WIDTH{1'b0}};
+reg [AXI_STRB_WIDTH-1:0] m_axi_wstrb_reg  = {AXI_STRB_WIDTH{1'b0}};
+reg                      m_axi_wlast_reg  = 1'b0;
+reg                      m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
+
+reg [AXI_DATA_WIDTH-1:0] temp_m_axi_wdata_reg  = {AXI_DATA_WIDTH{1'b0}};
+reg [AXI_STRB_WIDTH-1:0] temp_m_axi_wstrb_reg  = {AXI_STRB_WIDTH{1'b0}};
+reg                      temp_m_axi_wlast_reg  = 1'b0;
+reg                      temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
+
+// datapath control
+reg store_axi_w_int_to_output;
+reg store_axi_w_int_to_temp;
+reg store_axi_w_temp_to_output;
+
+assign m_axi_wdata  = m_axi_wdata_reg;
+assign m_axi_wstrb  = m_axi_wstrb_reg;
+assign m_axi_wvalid = m_axi_wvalid_reg;
+assign m_axi_wlast  = m_axi_wlast_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axi_wready_int_early = m_axi_wready || (!temp_m_axi_wvalid_reg && (!m_axi_wvalid_reg || !m_axi_wvalid_int));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;
+    temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+
+    store_axi_w_int_to_output = 1'b0;
+    store_axi_w_int_to_temp = 1'b0;
+    store_axi_w_temp_to_output = 1'b0;
+
+    if (m_axi_wready_int_reg) begin
+        // input is ready
+        if (m_axi_wready || !m_axi_wvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_temp = 1'b1;
+        end
+    end else if (m_axi_wready) begin
+        // input is not ready, but output is ready
+        m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+        temp_m_axi_wvalid_next = 1'b0;
+        store_axi_w_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_wvalid_reg <= 1'b0;
+        m_axi_wready_int_reg <= 1'b0;
+        temp_m_axi_wvalid_reg <= 1'b0;
+    end else begin
+        m_axi_wvalid_reg <= m_axi_wvalid_next;
+        m_axi_wready_int_reg <= m_axi_wready_int_early;
+        temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
+    end
+
+    // datapath
+    if (store_axi_w_int_to_output) begin
+        m_axi_wdata_reg <= m_axi_wdata_int;
+        m_axi_wstrb_reg <= m_axi_wstrb_int;
+        m_axi_wlast_reg <= m_axi_wlast_int;
+    end else if (store_axi_w_temp_to_output) begin
+        m_axi_wdata_reg <= temp_m_axi_wdata_reg;
+        m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
+        m_axi_wlast_reg <= temp_m_axi_wlast_reg;
+    end
+
+    if (store_axi_w_int_to_temp) begin
+        temp_m_axi_wdata_reg <= m_axi_wdata_int;
+        temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
+        temp_m_axi_wlast_reg <= m_axi_wlast_int;
+    end
+end
+
+endmodule

corundum/lib/axi/rtl/axi_cdma_desc_mux.v

+/*
+
+Copyright (c) 2019 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI CDMA descriptor mux
+ */
+module axi_cdma_desc_mux #
+(
+    // Number of ports
+    parameter PORTS = 2,
+    // AXI address width
+    parameter AXI_ADDR_WIDTH = 16,
+    // Length field width
+    parameter LEN_WIDTH = 20,
+    // Input tag field width
+    parameter S_TAG_WIDTH = 8,
+    // Output tag field width (towards CDMA module)
+    // Additional bits required for response routing
+    parameter M_TAG_WIDTH = S_TAG_WIDTH+$clog2(PORTS),
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter ARB_TYPE = "PRIORITY",
+    // LSB priority: "LOW", "HIGH"
+    parameter LSB_PRIORITY = "HIGH"
+)
+(
+    input  wire                            clk,
+    input  wire                            rst,
+
+    /*
+     * Descriptor output (to AXI CDMA core)
+     */
+    output wire [AXI_ADDR_WIDTH-1:0]       m_axis_desc_read_addr,
+    output wire [AXI_ADDR_WIDTH-1:0]       m_axis_desc_write_addr,
+    output wire [LEN_WIDTH-1:0]            m_axis_desc_len,
+    output wire [M_TAG_WIDTH-1:0]          m_axis_desc_tag,
+    output wire                            m_axis_desc_valid,
+    input  wire                            m_axis_desc_ready,
+
+    /*
+     * Descriptor status input (from AXI CDMA core)
+     */
+    input  wire [M_TAG_WIDTH-1:0]          s_axis_desc_status_tag,
+    input  wire                            s_axis_desc_status_valid,
+
+    /*
+     * Descriptor input
+     */
+    input  wire [PORTS*AXI_ADDR_WIDTH-1:0] s_axis_desc_read_addr,
+    input  wire [PORTS*AXI_ADDR_WIDTH-1:0] s_axis_desc_write_addr,
+    input  wire [PORTS*LEN_WIDTH-1:0]      s_axis_desc_len,
+    input  wire [PORTS*S_TAG_WIDTH-1:0]    s_axis_desc_tag,
+    input  wire [PORTS-1:0]                s_axis_desc_valid,
+    output wire [PORTS-1:0]                s_axis_desc_ready,
+
+    /*
+     * Descriptor status output
+     */
+    output wire [PORTS*S_TAG_WIDTH-1:0]    m_axis_desc_status_tag,
+    output wire [PORTS-1:0]                m_axis_desc_status_valid
+);
+
+parameter CL_PORTS = $clog2(PORTS);
+
+// check configuration
+initial begin
+    if (M_TAG_WIDTH < S_TAG_WIDTH+$clog2(PORTS)) begin
+        $error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH (instance %m)");
+        $finish;
+    end
+end
+
+// descriptor mux
+wire [PORTS-1:0] request;
+wire [PORTS-1:0] acknowledge;
+wire [PORTS-1:0] grant;
+wire grant_valid;
+wire [CL_PORTS-1:0] grant_encoded;
+
+// internal datapath
+reg  [AXI_ADDR_WIDTH-1:0] m_axis_desc_read_addr_int;
+reg  [AXI_ADDR_WIDTH-1:0] m_axis_desc_write_addr_int;
+reg  [LEN_WIDTH-1:0]      m_axis_desc_len_int;
+reg  [M_TAG_WIDTH-1:0]    m_axis_desc_tag_int;
+reg                       m_axis_desc_valid_int;
+reg                       m_axis_desc_ready_int_reg = 1'b0;
+wire                      m_axis_desc_ready_int_early;
+
+assign s_axis_desc_ready = (m_axis_desc_ready_int_reg && grant_valid) << grant_encoded;
+
+// mux for incoming packet
+wire [AXI_ADDR_WIDTH-1:0] current_s_desc_read_addr   = s_axis_desc_read_addr[grant_encoded*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH];
+wire [AXI_ADDR_WIDTH-1:0] current_s_desc_write_addr  = s_axis_desc_write_addr[grant_encoded*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH];
+wire [LEN_WIDTH-1:0]      current_s_desc_len         = s_axis_desc_len[grant_encoded*LEN_WIDTH +: LEN_WIDTH];
+wire [S_TAG_WIDTH-1:0]    current_s_desc_tag         = s_axis_desc_tag[grant_encoded*S_TAG_WIDTH +: S_TAG_WIDTH];
+wire                      current_s_desc_valid       = s_axis_desc_valid[grant_encoded];
+wire                      current_s_desc_ready       = s_axis_desc_ready[grant_encoded];
+
+// arbiter instance
+arbiter #(
+    .PORTS(PORTS),
+    .TYPE(ARB_TYPE),
+    .BLOCK("ACKNOWLEDGE"),
+    .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_valid(grant_valid),
+    .grant_encoded(grant_encoded)
+);
+
+assign request = s_axis_desc_valid & ~grant;
+assign acknowledge = grant & s_axis_desc_valid & s_axis_desc_ready;
+
+always @* begin
+    m_axis_desc_read_addr_int   = current_s_desc_read_addr;
+    m_axis_desc_write_addr_int  = current_s_desc_write_addr;
+    m_axis_desc_len_int         = current_s_desc_len;
+    m_axis_desc_tag_int         = {grant_encoded, current_s_desc_tag};
+    m_axis_desc_valid_int       = current_s_desc_valid && m_axis_desc_ready_int_reg && grant_valid;
+end
+
+// output datapath logic
+reg [AXI_ADDR_WIDTH-1:0]  m_axis_desc_read_addr_reg   = {AXI_ADDR_WIDTH{1'b0}};
+reg [AXI_ADDR_WIDTH-1:0]  m_axis_desc_write_addr_reg  = {AXI_ADDR_WIDTH{1'b0}};
+reg [LEN_WIDTH-1:0]       m_axis_desc_len_reg         = {LEN_WIDTH{1'b0}};
+reg [M_TAG_WIDTH-1:0]     m_axis_desc_tag_reg         = {M_TAG_WIDTH{1'b0}};
+reg                       m_axis_desc_valid_reg       = 1'b0, m_axis_desc_valid_next;
+
+reg [AXI_ADDR_WIDTH-1:0]  temp_m_axis_desc_read_addr_reg   = {AXI_ADDR_WIDTH{1'b0}};
+reg [AXI_ADDR_WIDTH-1:0]  temp_m_axis_desc_write_addr_reg  = {AXI_ADDR_WIDTH{1'b0}};
+reg [LEN_WIDTH-1:0]       temp_m_axis_desc_len_reg         = {LEN_WIDTH{1'b0}};
+reg [M_TAG_WIDTH-1:0]     temp_m_axis_desc_tag_reg         = {M_TAG_WIDTH{1'b0}};
+reg                       temp_m_axis_desc_valid_reg       = 1'b0, temp_m_axis_desc_valid_next;
+
+// datapath control
+reg store_axis_int_to_output;
+reg store_axis_int_to_temp;
+reg store_axis_temp_to_output;
+
+assign m_axis_desc_read_addr   = m_axis_desc_read_addr_reg;
+assign m_axis_desc_write_addr  = m_axis_desc_write_addr_reg;
+assign m_axis_desc_len         = m_axis_desc_len_reg;
+assign m_axis_desc_tag         = m_axis_desc_tag_reg;
+assign m_axis_desc_valid       = m_axis_desc_valid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axis_desc_ready_int_early = m_axis_desc_ready || (!temp_m_axis_desc_valid_reg && (!m_axis_desc_valid_reg || !m_axis_desc_valid_int));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axis_desc_valid_next = m_axis_desc_valid_reg;
+    temp_m_axis_desc_valid_next = temp_m_axis_desc_valid_reg;
+
+    store_axis_int_to_output = 1'b0;
+    store_axis_int_to_temp = 1'b0;
+    store_axis_temp_to_output = 1'b0;
+
+    if (m_axis_desc_ready_int_reg) begin
+        // input is ready
+        if (m_axis_desc_ready || !m_axis_desc_valid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axis_desc_valid_next = m_axis_desc_valid_int;
+            store_axis_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axis_desc_valid_next = m_axis_desc_valid_int;
+            store_axis_int_to_temp = 1'b1;
+        end
+    end else if (m_axis_desc_ready) begin
+        // input is not ready, but output is ready
+        m_axis_desc_valid_next = temp_m_axis_desc_valid_reg;
+        temp_m_axis_desc_valid_next = 1'b0;
+        store_axis_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axis_desc_valid_reg <= 1'b0;
+        m_axis_desc_ready_int_reg <= 1'b0;
+        temp_m_axis_desc_valid_reg <= 1'b0;
+    end else begin
+        m_axis_desc_valid_reg <= m_axis_desc_valid_next;
+        m_axis_desc_ready_int_reg <= m_axis_desc_ready_int_early;
+        temp_m_axis_desc_valid_reg <= temp_m_axis_desc_valid_next;
+    end
+
+    // datapath
+    if (store_axis_int_to_output) begin
+        m_axis_desc_read_addr_reg <= m_axis_desc_read_addr_int;
+        m_axis_desc_write_addr_reg <= m_axis_desc_write_addr_int;
+        m_axis_desc_len_reg <= m_axis_desc_len_int;
+        m_axis_desc_tag_reg <= m_axis_desc_tag_int;
+    end else if (store_axis_temp_to_output) begin
+        m_axis_desc_read_addr_reg <= temp_m_axis_desc_read_addr_reg;
+        m_axis_desc_write_addr_reg <= temp_m_axis_desc_write_addr_reg;
+        m_axis_desc_len_reg <= temp_m_axis_desc_len_reg;
+        m_axis_desc_tag_reg <= temp_m_axis_desc_tag_reg;
+    end
+
+    if (store_axis_int_to_temp) begin
+        temp_m_axis_desc_read_addr_reg <= m_axis_desc_read_addr_int;
+        temp_m_axis_desc_write_addr_reg <= m_axis_desc_write_addr_int;
+        temp_m_axis_desc_len_reg <= m_axis_desc_len_int;
+        temp_m_axis_desc_tag_reg <= m_axis_desc_tag_int;
+    end
+end
+
+// descriptor status demux
+reg [S_TAG_WIDTH-1:0] m_axis_desc_status_tag_reg = {S_TAG_WIDTH{1'b0}};
+reg [PORTS-1:0] m_axis_desc_status_valid_reg = {PORTS{1'b0}};
+
+assign m_axis_desc_status_tag = {PORTS{m_axis_desc_status_tag_reg}};
+assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axis_desc_status_valid_reg <= {PORTS{1'b0}};
+    end else begin
+        m_axis_desc_status_valid_reg <= s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[S_TAG_WIDTH+CL_PORTS-1:S_TAG_WIDTH] : 0);
+    end
+
+    m_axis_desc_status_tag_reg <= s_axis_desc_status_tag;
+end
+
+endmodule

corundum/lib/axi/rtl/axi_crossbar.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 crossbar
+ */
+module axi_crossbar #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Input ID field width (from AXI masters)
+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
+    // set to zero for default addressing based on M_ADDR_WIDTH
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire                             clk,
+    input  wire                             rst,
+
+    /*
+     * AXI slave interfaces
+     */
+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_awid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_awlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_awsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_awburst,
+    input  wire [S_COUNT-1:0]               s_axi_awlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_awcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_awprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_awqos,
+    input  wire [S_COUNT*AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire [S_COUNT-1:0]               s_axi_awvalid,
+    output wire [S_COUNT-1:0]               s_axi_awready,
+    input  wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_wdata,
+    input  wire [S_COUNT*STRB_WIDTH-1:0]    s_axi_wstrb,
+    input  wire [S_COUNT-1:0]               s_axi_wlast,
+    input  wire [S_COUNT*WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire [S_COUNT-1:0]               s_axi_wvalid,
+    output wire [S_COUNT-1:0]               s_axi_wready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_bid,
+    output wire [S_COUNT*2-1:0]             s_axi_bresp,
+    output wire [S_COUNT*BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire [S_COUNT-1:0]               s_axi_bvalid,
+    input  wire [S_COUNT-1:0]               s_axi_bready,
+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_arid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_arlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_arsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_arburst,
+    input  wire [S_COUNT-1:0]               s_axi_arlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_arcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_arprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_arqos,
+    input  wire [S_COUNT*ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire [S_COUNT-1:0]               s_axi_arvalid,
+    output wire [S_COUNT-1:0]               s_axi_arready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_rid,
+    output wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_rdata,
+    output wire [S_COUNT*2-1:0]             s_axi_rresp,
+    output wire [S_COUNT-1:0]               s_axi_rlast,
+    output wire [S_COUNT*RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire [S_COUNT-1:0]               s_axi_rvalid,
+    input  wire [S_COUNT-1:0]               s_axi_rready,
+
+    /*
+     * AXI master interfaces
+     */
+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_awid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [M_COUNT*8-1:0]             m_axi_awlen,
+    output wire [M_COUNT*3-1:0]             m_axi_awsize,
+    output wire [M_COUNT*2-1:0]             m_axi_awburst,
+    output wire [M_COUNT-1:0]               m_axi_awlock,
+    output wire [M_COUNT*4-1:0]             m_axi_awcache,
+    output wire [M_COUNT*3-1:0]             m_axi_awprot,
+    output wire [M_COUNT*4-1:0]             m_axi_awqos,
+    output wire [M_COUNT*4-1:0]             m_axi_awregion,
+    output wire [M_COUNT*AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire [M_COUNT-1:0]               m_axi_awvalid,
+    input  wire [M_COUNT-1:0]               m_axi_awready,
+    output wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_wdata,
+    output wire [M_COUNT*STRB_WIDTH-1:0]    m_axi_wstrb,
+    output wire [M_COUNT-1:0]               m_axi_wlast,
+    output wire [M_COUNT*WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire [M_COUNT-1:0]               m_axi_wvalid,
+    input  wire [M_COUNT-1:0]               m_axi_wready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_bid,
+    input  wire [M_COUNT*2-1:0]             m_axi_bresp,
+    input  wire [M_COUNT*BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire [M_COUNT-1:0]               m_axi_bvalid,
+    output wire [M_COUNT-1:0]               m_axi_bready,
+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_arid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [M_COUNT*8-1:0]             m_axi_arlen,
+    output wire [M_COUNT*3-1:0]             m_axi_arsize,
+    output wire [M_COUNT*2-1:0]             m_axi_arburst,
+    output wire [M_COUNT-1:0]               m_axi_arlock,
+    output wire [M_COUNT*4-1:0]             m_axi_arcache,
+    output wire [M_COUNT*3-1:0]             m_axi_arprot,
+    output wire [M_COUNT*4-1:0]             m_axi_arqos,
+    output wire [M_COUNT*4-1:0]             m_axi_arregion,
+    output wire [M_COUNT*ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire [M_COUNT-1:0]               m_axi_arvalid,
+    input  wire [M_COUNT-1:0]               m_axi_arready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_rid,
+    input  wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_rdata,
+    input  wire [M_COUNT*2-1:0]             m_axi_rresp,
+    input  wire [M_COUNT-1:0]               m_axi_rlast,
+    input  wire [M_COUNT*RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire [M_COUNT-1:0]               m_axi_rvalid,
+    output wire [M_COUNT-1:0]               m_axi_rready
+);
+
+axi_crossbar_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .STRB_WIDTH(STRB_WIDTH),
+    .S_ID_WIDTH(S_ID_WIDTH),
+    .M_ID_WIDTH(M_ID_WIDTH),
+    .AWUSER_ENABLE(AWUSER_ENABLE),
+    .AWUSER_WIDTH(AWUSER_WIDTH),
+    .WUSER_ENABLE(WUSER_ENABLE),
+    .WUSER_WIDTH(WUSER_WIDTH),
+    .BUSER_ENABLE(BUSER_ENABLE),
+    .BUSER_WIDTH(BUSER_WIDTH),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_WIDTH(M_ADDR_WIDTH),
+    .M_CONNECT(M_CONNECT_WRITE),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE (S_W_REG_TYPE),
+    .S_B_REG_TYPE (S_B_REG_TYPE)
+)
+axi_crossbar_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(s_axi_awuser),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(s_axi_wuser),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(s_axi_buser),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awuser(m_axi_awuser),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(m_axi_wuser),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(m_axi_buser),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready)
+);
+
+axi_crossbar_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .STRB_WIDTH(STRB_WIDTH),
+    .S_ID_WIDTH(S_ID_WIDTH),
+    .M_ID_WIDTH(M_ID_WIDTH),
+    .ARUSER_ENABLE(ARUSER_ENABLE),
+    .ARUSER_WIDTH(ARUSER_WIDTH),
+    .RUSER_ENABLE(RUSER_ENABLE),
+    .RUSER_WIDTH(RUSER_WIDTH),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_WIDTH(M_ADDR_WIDTH),
+    .M_CONNECT(M_CONNECT_READ),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE (S_R_REG_TYPE)
+)
+axi_crossbar_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(s_axi_aruser),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(s_axi_ruser),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_aruser(m_axi_aruser),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(m_axi_ruser),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+);
+
+endmodule

corundum/lib/axi/rtl/axi_crossbar_addr.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 crossbar address decode and admission control
+ */
+module axi_crossbar_addr #
+(
+    // Slave interface index
+    parameter S = 0,
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // ID field width
+    parameter ID_WIDTH = 8,
+    // Number of concurrent unique IDs
+    parameter S_THREADS = 32'd2,
+    // Number of concurrent operations
+    parameter S_ACCEPT = 32'd16,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
+    // set to zero for default addressing based on M_ADDR_WIDTH
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Enable write command output
+    parameter WC_OUTPUT = 0
+)
+(
+    input  wire                       clk,
+    input  wire                       rst,
+
+    /*
+     * Address input
+     */
+    input  wire [ID_WIDTH-1:0]        s_axi_aid,
+    input  wire [ADDR_WIDTH-1:0]      s_axi_aaddr,
+    input  wire [2:0]                 s_axi_aprot,
+    input  wire [3:0]                 s_axi_aqos,
+    input  wire                       s_axi_avalid,
+    output wire                       s_axi_aready,
+
+    /*
+     * Address output
+     */
+    output wire [3:0]                 m_axi_aregion,
+    output wire [$clog2(M_COUNT)-1:0] m_select,
+    output wire                       m_axi_avalid,
+    input  wire                       m_axi_aready,
+
+    /*
+     * Write command output
+     */
+    output wire [$clog2(M_COUNT)-1:0] m_wc_select,
+    output wire                       m_wc_decerr,
+    output wire                       m_wc_valid,
+    input  wire                       m_wc_ready,
+
+    /*
+     * Reply command output
+     */
+    output wire                       m_rc_decerr,
+    output wire                       m_rc_valid,
+    input  wire                       m_rc_ready,
+
+    /*
+     * Completion input
+     */
+    input  wire [ID_WIDTH-1:0]        s_cpl_id,
+    input  wire                       s_cpl_valid
+);
+
+parameter CL_S_COUNT = $clog2(S_COUNT);
+parameter CL_M_COUNT = $clog2(M_COUNT);
+
+parameter S_INT_THREADS = S_THREADS > S_ACCEPT ? S_ACCEPT : S_THREADS;
+parameter CL_S_INT_THREADS = $clog2(S_INT_THREADS);
+parameter CL_S_ACCEPT = $clog2(S_ACCEPT);
+
+// default address computation
+function [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy);
+    integer i;
+    reg [ADDR_WIDTH-1:0] base;
+    begin
+        calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}};
+        base = 0;
+        for (i = 1; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            if (M_ADDR_WIDTH[i*32 +: 32]) begin
+                base = base + 2**M_ADDR_WIDTH[(i-1)*32 +: 32]; // increment
+                base = base - (base % 2**M_ADDR_WIDTH[i*32 +: 32]); // align
+                calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base;
+            end
+        end
+    end
+endfunction
+
+parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0);
+
+integer i, j;
+
+// check configuration
+initial begin
+    if (S_ACCEPT < 1) begin
+        $error("Error: need at least 1 accept (instance %m)");
+        $finish;
+    end
+
+    if (S_THREADS < 1) begin
+        $error("Error: need at least 1 thread (instance %m)");
+        $finish;
+    end
+
+    if (S_THREADS > S_ACCEPT) begin
+        $warning("Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)");
+    end
+
+    if (M_REGIONS < 1) begin
+        $error("Error: need at least 1 region (instance %m)");
+        $finish;
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+    end
+
+    $display("Addressing configuration for axi_crossbar_addr instance %m");
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_WIDTH[i*32 +: 32]) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x", i/M_REGIONS, i%M_REGIONS, M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[i*32 +: 32], M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])));
+        end
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin
+                if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])))) && ((M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x", i/M_REGIONS, i%M_REGIONS, M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[i*32 +: 32], M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])));
+                    $display("%2d (%2d): %x / %2d -- %x-%x", j/M_REGIONS, j%M_REGIONS, M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[j*32 +: 32], M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]), M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])));
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1;
+
+reg [2:0] state_reg = STATE_IDLE, state_next;
+
+reg s_axi_aready_reg = 0, s_axi_aready_next;
+
+reg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;
+reg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next;
+reg m_axi_avalid_reg = 1'b0, m_axi_avalid_next;
+reg m_decerr_reg = 1'b0, m_decerr_next;
+reg m_wc_valid_reg = 1'b0, m_wc_valid_next;
+reg m_rc_valid_reg = 1'b0, m_rc_valid_next;
+
+assign s_axi_aready = s_axi_aready_reg;
+
+assign m_axi_aregion = m_axi_aregion_reg;
+assign m_select = m_select_reg;
+assign m_axi_avalid = m_axi_avalid_reg;
+
+assign m_wc_select = m_select_reg;
+assign m_wc_decerr = m_decerr_reg;
+assign m_wc_valid = m_wc_valid_reg;
+
+assign m_rc_decerr = m_decerr_reg;
+assign m_rc_valid = m_rc_valid_reg;
+
+reg match;
+reg trans_start;
+reg trans_complete;
+
+reg [$clog2(S_ACCEPT+1)-1:0] trans_count_reg = 0;
+wire trans_limit = trans_count_reg >= S_ACCEPT && !trans_complete;
+
+// transfer ID thread tracking
+reg [ID_WIDTH-1:0] thread_id_reg[S_INT_THREADS-1:0];
+reg [CL_M_COUNT-1:0] thread_m_reg[S_INT_THREADS-1:0];
+reg [3:0] thread_region_reg[S_INT_THREADS-1:0];
+reg [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0];
+
+wire [S_INT_THREADS-1:0] thread_active;
+wire [S_INT_THREADS-1:0] thread_match;
+wire [S_INT_THREADS-1:0] thread_match_dest;
+wire [S_INT_THREADS-1:0] thread_cpl_match;
+wire [S_INT_THREADS-1:0] thread_trans_start;
+wire [S_INT_THREADS-1:0] thread_trans_complete;
+
+generate
+    genvar n;
+
+    for (n = 0; n < S_INT_THREADS; n = n + 1) begin
+        initial begin
+            thread_count_reg[n] <= 0;
+        end
+
+        assign thread_active[n] = thread_count_reg[n] != 0;
+        assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid;
+        assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next);
+        assign thread_cpl_match[n] = thread_active[n] && thread_id_reg[n] == s_cpl_id;
+        assign thread_trans_start[n] = (thread_match[n] || (!thread_active[n] && !thread_match && !(thread_trans_start & ({S_INT_THREADS{1'b1}} >> (S_INT_THREADS-n))))) && trans_start;
+        assign thread_trans_complete[n] = thread_cpl_match[n] && trans_complete;
+
+        always @(posedge clk) begin
+            if (rst) begin
+                thread_count_reg[n] <= 0;
+            end else begin
+                if (thread_trans_start[n] && !thread_trans_complete[n]) begin
+                    thread_count_reg[n] <= thread_count_reg[n] + 1;
+                end else if (!thread_trans_start[n] && thread_trans_complete[n]) begin
+                    thread_count_reg[n] <= thread_count_reg[n] - 1;
+                end
+            end
+
+            if (thread_trans_start[n]) begin
+                thread_id_reg[n] <= s_axi_aid;
+                thread_m_reg[n] <= m_select_next;
+                thread_region_reg[n] <= m_axi_aregion_next;
+            end
+        end
+    end
+endgenerate
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+    trans_start = 1'b0;
+    trans_complete = 1'b0;
+
+    s_axi_aready_next = 1'b0;
+
+    m_axi_aregion_next = m_axi_aregion_reg;
+    m_select_next = m_select_reg;
+    m_select_next = m_select_reg;
+    m_axi_avalid_next = m_axi_avalid_reg && !m_axi_aready;
+    m_decerr_next = m_decerr_reg;
+    m_wc_valid_next = m_wc_valid_reg && !m_wc_ready;
+    m_rc_valid_next = m_rc_valid_reg && !m_rc_ready;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state, store values
+            s_axi_aready_next = 1'b0;
+
+            if (s_axi_avalid && !s_axi_aready) begin
+                match = 1'b0;
+                for (i = 0; i < M_COUNT; i = i + 1) begin
+                    for (j = 0; j < M_REGIONS; j = j + 1) begin
+                        if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !s_axi_aprot[1]) && (M_CONNECT & (1 << (S+i*S_COUNT))) && (s_axi_aaddr >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin
+                            m_select_next = i;
+                            m_axi_aregion_next = j;
+                            match = 1'b1;
+                        end
+                    end
+                end
+
+                if (match) begin
+                    // address decode successful
+                    if (!trans_limit && (thread_match_dest || (!(&thread_active) && !thread_match))) begin
+                        // transaction limit not reached
+                        m_axi_avalid_next = 1'b1;
+                        m_decerr_next = 1'b0;
+                        m_wc_valid_next = WC_OUTPUT;
+                        m_rc_valid_next = 1'b0;
+                        trans_start = 1'b1;
+                        state_next = STATE_DECODE;
+                    end else begin
+                        // transaction limit reached; block in idle
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    // decode error
+                    m_axi_avalid_next = 1'b0;
+                    m_decerr_next = 1'b1;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            if (!m_axi_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin
+                s_axi_aready_next = 1'b1;
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_DECODE;
+            end
+        end
+    endcase
+
+    // manage completions
+    trans_complete = s_cpl_valid;
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_aready_reg <= 1'b0;
+        m_axi_avalid_reg <= 1'b0;
+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;
+
+        trans_count_reg <= 0;
+    end else begin
+        state_reg <= state_next;
+        s_axi_aready_reg <= s_axi_aready_next;
+        m_axi_avalid_reg <= m_axi_avalid_next;
+        m_wc_valid_reg <= m_wc_valid_next;
+        m_rc_valid_reg <= m_rc_valid_next;
+
+        if (trans_start && !trans_complete) begin
+            trans_count_reg <= trans_count_reg + 1;
+        end else if (!trans_start && trans_complete) begin
+            trans_count_reg <= trans_count_reg - 1;
+        end
+    end
+
+    m_axi_aregion_reg <= m_axi_aregion_next;
+    m_select_reg <= m_select_next;
+    m_decerr_reg <= m_decerr_next;
+end
+
+endmodule

corundum/lib/axi/rtl/axi_crossbar_rd.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 crossbar (read)
+ */
+module axi_crossbar_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Input ID field width (from AXI masters)
+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
+    // set to zero for default addressing based on M_ADDR_WIDTH
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire                             clk,
+    input  wire                             rst,
+
+    /*
+     * AXI slave interfaces
+     */
+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_arid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_arlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_arsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_arburst,
+    input  wire [S_COUNT-1:0]               s_axi_arlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_arcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_arprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_arqos,
+    input  wire [S_COUNT*ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire [S_COUNT-1:0]               s_axi_arvalid,
+    output wire [S_COUNT-1:0]               s_axi_arready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_rid,
+    output wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_rdata,
+    output wire [S_COUNT*2-1:0]             s_axi_rresp,
+    output wire [S_COUNT-1:0]               s_axi_rlast,
+    output wire [S_COUNT*RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire [S_COUNT-1:0]               s_axi_rvalid,
+    input  wire [S_COUNT-1:0]               s_axi_rready,
+
+    /*
+     * AXI master interfaces
+     */
+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_arid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [M_COUNT*8-1:0]             m_axi_arlen,
+    output wire [M_COUNT*3-1:0]             m_axi_arsize,
+    output wire [M_COUNT*2-1:0]             m_axi_arburst,
+    output wire [M_COUNT-1:0]               m_axi_arlock,
+    output wire [M_COUNT*4-1:0]             m_axi_arcache,
+    output wire [M_COUNT*3-1:0]             m_axi_arprot,
+    output wire [M_COUNT*4-1:0]             m_axi_arqos,
+    output wire [M_COUNT*4-1:0]             m_axi_arregion,
+    output wire [M_COUNT*ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire [M_COUNT-1:0]               m_axi_arvalid,
+    input  wire [M_COUNT-1:0]               m_axi_arready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_rid,
+    input  wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_rdata,
+    input  wire [M_COUNT*2-1:0]             m_axi_rresp,
+    input  wire [M_COUNT-1:0]               m_axi_rlast,
+    input  wire [M_COUNT*RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire [M_COUNT-1:0]               m_axi_rvalid,
+    output wire [M_COUNT-1:0]               m_axi_rready
+);
+
+parameter CL_S_COUNT = $clog2(S_COUNT);
+parameter CL_M_COUNT = $clog2(M_COUNT);
+parameter M_COUNT_P1 = M_COUNT+1;
+parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
+
+integer i;
+
+// check configuration
+initial begin
+    if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin
+        $error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)");
+        $finish;
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
+            $error("Error: value out of range (instance %m)");
+            $finish;
+        end
+    end
+end
+
+wire [S_COUNT*S_ID_WIDTH-1:0]    int_s_axi_arid;
+wire [S_COUNT*ADDR_WIDTH-1:0]    int_s_axi_araddr;
+wire [S_COUNT*8-1:0]             int_s_axi_arlen;
+wire [S_COUNT*3-1:0]             int_s_axi_arsize;
+wire [S_COUNT*2-1:0]             int_s_axi_arburst;
+wire [S_COUNT-1:0]               int_s_axi_arlock;
+wire [S_COUNT*4-1:0]             int_s_axi_arcache;
+wire [S_COUNT*3-1:0]             int_s_axi_arprot;
+wire [S_COUNT*4-1:0]             int_s_axi_arqos;
+wire [S_COUNT*4-1:0]             int_s_axi_arregion;
+wire [S_COUNT*ARUSER_WIDTH-1:0]  int_s_axi_aruser;
+wire [S_COUNT-1:0]               int_s_axi_arvalid;
+wire [S_COUNT-1:0]               int_s_axi_arready;
+
+wire [S_COUNT*M_COUNT-1:0]       int_axi_arvalid;
+wire [M_COUNT*S_COUNT-1:0]       int_axi_arready;
+
+wire [M_COUNT*M_ID_WIDTH-1:0]    int_m_axi_rid;
+wire [M_COUNT*DATA_WIDTH-1:0]    int_m_axi_rdata;
+wire [M_COUNT*2-1:0]             int_m_axi_rresp;
+wire [M_COUNT-1:0]               int_m_axi_rlast;
+wire [M_COUNT*RUSER_WIDTH-1:0]   int_m_axi_ruser;
+wire [M_COUNT-1:0]               int_m_axi_rvalid;
+wire [M_COUNT-1:0]               int_m_axi_rready;
+
+wire [M_COUNT*S_COUNT-1:0]       int_axi_rvalid;
+wire [S_COUNT*M_COUNT-1:0]       int_axi_rready;
+
+generate
+
+    genvar m, n;
+
+    for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+        // address decode and admission control
+        wire [CL_M_COUNT-1:0] a_select;
+
+        wire m_axi_avalid;
+        wire m_axi_aready;
+
+        wire m_rc_decerr;
+        wire m_rc_valid;
+        wire m_rc_ready;
+
+        wire [S_ID_WIDTH-1:0] s_cpl_id;
+        wire s_cpl_valid;
+
+        axi_crossbar_addr #(
+            .S(m),
+            .S_COUNT(S_COUNT),
+            .M_COUNT(M_COUNT),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .ID_WIDTH(S_ID_WIDTH),
+            .S_THREADS(S_THREADS[m*32 +: 32]),
+            .S_ACCEPT(S_ACCEPT[m*32 +: 32]),
+            .M_REGIONS(M_REGIONS),
+            .M_BASE_ADDR(M_BASE_ADDR),
+            .M_ADDR_WIDTH(M_ADDR_WIDTH),
+            .M_CONNECT(M_CONNECT),
+            .M_SECURE(M_SECURE),
+            .WC_OUTPUT(0)
+        )
+        addr_inst (
+            .clk(clk),
+            .rst(rst),
+
+            /*
+             * Address input
+             */
+            .s_axi_aid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_aaddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .s_axi_aprot(int_s_axi_arprot[m*3 +: 3]),
+            .s_axi_aqos(int_s_axi_arqos[m*4 +: 4]),
+            .s_axi_avalid(int_s_axi_arvalid[m]),
+            .s_axi_aready(int_s_axi_arready[m]),
+
+            /*
+             * Address output
+             */
+            .m_axi_aregion(int_s_axi_arregion[m*4 +: 4]),
+            .m_select(a_select),
+            .m_axi_avalid(m_axi_avalid),
+            .m_axi_aready(m_axi_aready),
+
+            /*
+             * Write command output
+             */
+            .m_wc_select(),
+            .m_wc_decerr(),
+            .m_wc_valid(),
+            .m_wc_ready(1'b1),
+
+            /*
+             * Response command output
+             */
+            .m_rc_decerr(m_rc_decerr),
+            .m_rc_valid(m_rc_valid),
+            .m_rc_ready(m_rc_ready),
+
+            /*
+             * Completion input
+             */
+            .s_cpl_id(s_cpl_id),
+            .s_cpl_valid(s_cpl_valid)
+        );
+
+        assign int_axi_arvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select;
+        assign m_axi_aready = int_axi_arready[a_select*S_COUNT+m];
+
+        // decode error handling
+        reg [S_ID_WIDTH-1:0]  decerr_m_axi_rid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_rid_next;
+        reg                   decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next;
+        reg                   decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next;
+        wire                  decerr_m_axi_rready;
+
+        reg [7:0] decerr_len_reg = 8'd0, decerr_len_next;
+
+        assign m_rc_ready = !decerr_m_axi_rvalid_reg;
+
+        always @* begin
+            decerr_len_next = decerr_len_reg;
+            decerr_m_axi_rid_next = decerr_m_axi_rid_reg;
+            decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg;
+            decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg;
+
+            if (decerr_m_axi_rvalid_reg) begin
+                if (decerr_m_axi_rready) begin
+                    if (decerr_len_reg > 0) begin
+                        decerr_len_next = decerr_len_reg-1;
+                        decerr_m_axi_rlast_next = (decerr_len_next == 0);
+                        decerr_m_axi_rvalid_next = 1'b1;
+                    end else begin
+                        decerr_m_axi_rvalid_next = 1'b0;
+                    end
+                end
+            end else if (m_rc_valid && m_rc_ready) begin
+                decerr_len_next = int_s_axi_arlen[m*8 +: 8];
+                decerr_m_axi_rid_next = int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH];
+                decerr_m_axi_rlast_next = (decerr_len_next == 0);
+                decerr_m_axi_rvalid_next = 1'b1;
+            end
+        end
+
+        always @(posedge clk) begin
+            if (rst) begin
+                decerr_m_axi_rvalid_reg <= 1'b0;
+            end else begin
+                decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next;
+            end
+
+            decerr_m_axi_rid_reg <= decerr_m_axi_rid_next;
+            decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next;
+            decerr_len_reg <= decerr_len_next;
+        end
+
+        // read response arbitration
+        wire [M_COUNT_P1-1:0] r_request;
+        wire [M_COUNT_P1-1:0] r_acknowledge;
+        wire [M_COUNT_P1-1:0] r_grant;
+        wire r_grant_valid;
+        wire [CL_M_COUNT_P1-1:0] r_grant_encoded;
+
+        arbiter #(
+            .PORTS(M_COUNT_P1),
+            .TYPE("ROUND_ROBIN"),
+            .BLOCK("ACKNOWLEDGE"),
+            .LSB_PRIORITY("HIGH")
+        )
+        r_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .request(r_request),
+            .acknowledge(r_acknowledge),
+            .grant(r_grant),
+            .grant_valid(r_grant_valid),
+            .grant_encoded(r_grant_encoded)
+        );
+
+        // read response mux
+        wire [S_ID_WIDTH-1:0]  m_axi_rid_mux    = {decerr_m_axi_rid_reg, int_m_axi_rid} >> r_grant_encoded*M_ID_WIDTH;
+        wire [DATA_WIDTH-1:0]  m_axi_rdata_mux  = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded*DATA_WIDTH;
+        wire [1:0]             m_axi_rresp_mux  = {2'b11, int_m_axi_rresp} >> r_grant_encoded*2;
+        wire                   m_axi_rlast_mux  = {decerr_m_axi_rlast_reg, int_m_axi_rlast} >> r_grant_encoded;
+        wire [RUSER_WIDTH-1:0] m_axi_ruser_mux  = {{RUSER_WIDTH{1'b0}}, int_m_axi_ruser} >> r_grant_encoded*RUSER_WIDTH;
+        wire                   m_axi_rvalid_mux = ({decerr_m_axi_rvalid_reg, int_m_axi_rvalid} >> r_grant_encoded) & r_grant_valid;
+        wire                   m_axi_rready_mux;
+
+        assign int_axi_rready[m*M_COUNT +: M_COUNT] = (r_grant_valid && m_axi_rready_mux) << r_grant_encoded;
+        assign decerr_m_axi_rready = (r_grant_valid && m_axi_rready_mux) && (r_grant_encoded == M_COUNT_P1-1);
+
+        for (n = 0; n < M_COUNT; n = n + 1) begin
+            assign r_request[n] = int_axi_rvalid[n*S_COUNT+m] && !r_grant[n];
+            assign r_acknowledge[n] = r_grant[n] && int_axi_rvalid[n*S_COUNT+m] && m_axi_rlast_mux && m_axi_rready_mux;
+        end
+
+        assign r_request[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1];
+        assign r_acknowledge[M_COUNT_P1-1] = r_grant[M_COUNT_P1-1] && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && m_axi_rready_mux;
+
+        assign s_cpl_id = m_axi_rid_mux;
+        assign s_cpl_valid = m_axi_rvalid_mux && m_axi_rready_mux && m_axi_rlast_mux;
+
+        // S side register
+        axi_register_rd #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(S_ID_WIDTH),
+            .ARUSER_ENABLE(ARUSER_ENABLE),
+            .ARUSER_WIDTH(ARUSER_WIDTH),
+            .RUSER_ENABLE(RUSER_ENABLE),
+            .RUSER_WIDTH(RUSER_WIDTH),
+            .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
+            .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_arid(s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_araddr(s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .s_axi_arlen(s_axi_arlen[m*8 +: 8]),
+            .s_axi_arsize(s_axi_arsize[m*3 +: 3]),
+            .s_axi_arburst(s_axi_arburst[m*2 +: 2]),
+            .s_axi_arlock(s_axi_arlock[m]),
+            .s_axi_arcache(s_axi_arcache[m*4 +: 4]),
+            .s_axi_arprot(s_axi_arprot[m*3 +: 3]),
+            .s_axi_arqos(s_axi_arqos[m*4 +: 4]),
+            .s_axi_arregion(4'd0),
+            .s_axi_aruser(s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),
+            .s_axi_arvalid(s_axi_arvalid[m]),
+            .s_axi_arready(s_axi_arready[m]),
+            .s_axi_rid(s_axi_rid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_rdata(s_axi_rdata[m*DATA_WIDTH +: DATA_WIDTH]),
+            .s_axi_rresp(s_axi_rresp[m*2 +: 2]),
+            .s_axi_rlast(s_axi_rlast[m]),
+            .s_axi_ruser(s_axi_ruser[m*RUSER_WIDTH +: RUSER_WIDTH]),
+            .s_axi_rvalid(s_axi_rvalid[m]),
+            .s_axi_rready(s_axi_rready[m]),
+            .m_axi_arid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .m_axi_araddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_arlen(int_s_axi_arlen[m*8 +: 8]),
+            .m_axi_arsize(int_s_axi_arsize[m*3 +: 3]),
+            .m_axi_arburst(int_s_axi_arburst[m*2 +: 2]),
+            .m_axi_arlock(int_s_axi_arlock[m]),
+            .m_axi_arcache(int_s_axi_arcache[m*4 +: 4]),
+            .m_axi_arprot(int_s_axi_arprot[m*3 +: 3]),
+            .m_axi_arqos(int_s_axi_arqos[m*4 +: 4]),
+            .m_axi_arregion(),
+            .m_axi_aruser(int_s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),
+            .m_axi_arvalid(int_s_axi_arvalid[m]),
+            .m_axi_arready(int_s_axi_arready[m]),
+            .m_axi_rid(m_axi_rid_mux),
+            .m_axi_rdata(m_axi_rdata_mux),
+            .m_axi_rresp(m_axi_rresp_mux),
+            .m_axi_rlast(m_axi_rlast_mux),
+            .m_axi_ruser(m_axi_ruser_mux),
+            .m_axi_rvalid(m_axi_rvalid_mux),
+            .m_axi_rready(m_axi_rready_mux)
+        );
+    end // s_ifaces
+
+    for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+        // in-flight transaction count
+        wire trans_start;
+        wire trans_complete;
+        reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;
+
+        wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;
+
+        always @(posedge clk) begin
+            if (rst) begin
+                trans_count_reg <= 0;
+            end else begin
+                if (trans_start && !trans_complete) begin
+                    trans_count_reg <= trans_count_reg + 1;
+                end else if (!trans_start && trans_complete) begin
+                    trans_count_reg <= trans_count_reg - 1;
+                end
+            end
+        end
+
+        // address arbitration
+        wire [S_COUNT-1:0] a_request;
+        wire [S_COUNT-1:0] a_acknowledge;
+        wire [S_COUNT-1:0] a_grant;
+        wire a_grant_valid;
+        wire [CL_S_COUNT-1:0] a_grant_encoded;
+
+        arbiter #(
+            .PORTS(S_COUNT),
+            .TYPE("ROUND_ROBIN"),
+            .BLOCK("ACKNOWLEDGE"),
+            .LSB_PRIORITY("HIGH")
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .request(a_request),
+            .acknowledge(a_acknowledge),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_encoded(a_grant_encoded)
+        );
+
+        // address mux
+        wire [M_ID_WIDTH-1:0]   s_axi_arid_mux     = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);
+        wire [ADDR_WIDTH-1:0]   s_axi_araddr_mux   = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
+        wire [7:0]              s_axi_arlen_mux    = int_s_axi_arlen[a_grant_encoded*8 +: 8];
+        wire [2:0]              s_axi_arsize_mux   = int_s_axi_arsize[a_grant_encoded*3 +: 3];
+        wire [1:0]              s_axi_arburst_mux  = int_s_axi_arburst[a_grant_encoded*2 +: 2];
+        wire                    s_axi_arlock_mux   = int_s_axi_arlock[a_grant_encoded];
+        wire [3:0]              s_axi_arcache_mux  = int_s_axi_arcache[a_grant_encoded*4 +: 4];
+        wire [2:0]              s_axi_arprot_mux   = int_s_axi_arprot[a_grant_encoded*3 +: 3];
+        wire [3:0]              s_axi_arqos_mux    = int_s_axi_arqos[a_grant_encoded*4 +: 4];
+        wire [3:0]              s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4];
+        wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux   = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH];
+        wire                    s_axi_arvalid_mux  = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;
+        wire                    s_axi_arready_mux;
+
+        assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded;
+
+        for (m = 0; m < S_COUNT; m = m + 1) begin
+            assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit;
+            assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux;
+        end
+
+        assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid;
+
+        // read response forwarding
+        wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;
+
+        assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select;
+        assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n];
+
+        assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n];
+
+        // M side register
+        axi_register_rd #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(M_ID_WIDTH),
+            .ARUSER_ENABLE(ARUSER_ENABLE),
+            .ARUSER_WIDTH(ARUSER_WIDTH),
+            .RUSER_ENABLE(RUSER_ENABLE),
+            .RUSER_WIDTH(RUSER_WIDTH),
+            .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
+            .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_arid(s_axi_arid_mux),
+            .s_axi_araddr(s_axi_araddr_mux),
+            .s_axi_arlen(s_axi_arlen_mux),
+            .s_axi_arsize(s_axi_arsize_mux),
+            .s_axi_arburst(s_axi_arburst_mux),
+            .s_axi_arlock(s_axi_arlock_mux),
+            .s_axi_arcache(s_axi_arcache_mux),
+            .s_axi_arprot(s_axi_arprot_mux),
+            .s_axi_arqos(s_axi_arqos_mux),
+            .s_axi_arregion(s_axi_arregion_mux),
+            .s_axi_aruser(s_axi_aruser_mux),
+            .s_axi_arvalid(s_axi_arvalid_mux),
+            .s_axi_arready(s_axi_arready_mux),
+            .s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .s_axi_rresp(int_m_axi_rresp[n*2 +: 2]),
+            .s_axi_rlast(int_m_axi_rlast[n]),
+            .s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
+            .s_axi_rvalid(int_m_axi_rvalid[n]),
+            .s_axi_rready(int_m_axi_rready[n]),
+            .m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_arlen(m_axi_arlen[n*8 +: 8]),
+            .m_axi_arsize(m_axi_arsize[n*3 +: 3]),
+            .m_axi_arburst(m_axi_arburst[n*2 +: 2]),
+            .m_axi_arlock(m_axi_arlock[n]),
+            .m_axi_arcache(m_axi_arcache[n*4 +: 4]),
+            .m_axi_arprot(m_axi_arprot[n*3 +: 3]),
+            .m_axi_arqos(m_axi_arqos[n*4 +: 4]),
+            .m_axi_arregion(m_axi_arregion[n*4 +: 4]),
+            .m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]),
+            .m_axi_arvalid(m_axi_arvalid[n]),
+            .m_axi_arready(m_axi_arready[n]),
+            .m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .m_axi_rresp(m_axi_rresp[n*2 +: 2]),
+            .m_axi_rlast(m_axi_rlast[n]),
+            .m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
+            .m_axi_rvalid(m_axi_rvalid[n]),
+            .m_axi_rready(m_axi_rready[n])
+        );
+    end // m_ifaces
+
+endgenerate
+
+endmodule