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Commit 738c1fef authored by Antoine Kaufmann's avatar Antoine Kaufmann
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add corundum and verilator build files

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corundum/lib/eth/rtl/eth_axis_tx.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream ethernet frame transmitter (Ethernet frame in, AXI out)
*/
module eth_axis_tx #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status signals
*/
output wire busy
);
parameter CYCLE_COUNT = (14+KEEP_WIDTH-1)/KEEP_WIDTH;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = 14 % KEEP_WIDTH;
// bus width assertions
initial begin
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame with header fields in parallel along
with the payload in an AXI stream, combines the header with the payload, and
transmits the complete Ethernet frame on the output AXI stream interface.
*/
// datapath control signals
reg store_eth_hdr;
reg send_eth_header_reg = 1'b0, send_eth_header_next;
reg send_eth_payload_reg = 1'b0, send_eth_payload_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg flush_save;
reg transfer_in_save;
reg [47:0] eth_dest_mac_reg = 48'd0;
reg [47:0] eth_src_mac_reg = 48'd0;
reg [15:0] eth_type_reg = 16'd0;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg busy_reg = 1'b0;
reg [DATA_WIDTH-1:0] save_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] save_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg save_eth_payload_axis_tlast_reg = 1'b0;
reg save_eth_payload_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] shift_eth_payload_axis_tdata;
reg [KEEP_WIDTH-1:0] shift_eth_payload_axis_tkeep;
reg shift_eth_payload_axis_tvalid;
reg shift_eth_payload_axis_tlast;
reg shift_eth_payload_axis_tuser;
reg shift_eth_payload_axis_input_tready;
reg shift_eth_payload_axis_extra_cycle_reg = 1'b0;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign busy = busy_reg;
always @* begin
if (OFFSET == 0) begin
// passthrough if no overlap
shift_eth_payload_axis_tdata = s_eth_payload_axis_tdata;
shift_eth_payload_axis_tkeep = s_eth_payload_axis_tkeep;
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = s_eth_payload_axis_tlast;
shift_eth_payload_axis_tuser = s_eth_payload_axis_tuser;
shift_eth_payload_axis_input_tready = 1'b1;
end else if (shift_eth_payload_axis_extra_cycle_reg) begin
shift_eth_payload_axis_tdata = {s_eth_payload_axis_tdata, save_eth_payload_axis_tdata_reg} >> ((KEEP_WIDTH-OFFSET)*8);
shift_eth_payload_axis_tkeep = {{KEEP_WIDTH{1'b0}}, save_eth_payload_axis_tkeep_reg} >> (KEEP_WIDTH-OFFSET);
shift_eth_payload_axis_tvalid = 1'b1;
shift_eth_payload_axis_tlast = save_eth_payload_axis_tlast_reg;
shift_eth_payload_axis_tuser = save_eth_payload_axis_tuser_reg;
shift_eth_payload_axis_input_tready = flush_save;
end else begin
shift_eth_payload_axis_tdata = {s_eth_payload_axis_tdata, save_eth_payload_axis_tdata_reg} >> ((KEEP_WIDTH-OFFSET)*8);
shift_eth_payload_axis_tkeep = {s_eth_payload_axis_tkeep, save_eth_payload_axis_tkeep_reg} >> (KEEP_WIDTH-OFFSET);
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = (s_eth_payload_axis_tlast && ((s_eth_payload_axis_tkeep & ({KEEP_WIDTH{1'b1}} << (KEEP_WIDTH-OFFSET))) == 0));
shift_eth_payload_axis_tuser = (s_eth_payload_axis_tuser && ((s_eth_payload_axis_tkeep & ({KEEP_WIDTH{1'b1}} << (KEEP_WIDTH-OFFSET))) == 0));
shift_eth_payload_axis_input_tready = !(s_eth_payload_axis_tlast && s_eth_payload_axis_tready && s_eth_payload_axis_tvalid);
end
end
always @* begin
send_eth_header_next = send_eth_header_reg;
send_eth_payload_next = send_eth_payload_reg;
ptr_next = ptr_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
flush_save = 1'b0;
transfer_in_save = 1'b0;
m_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
store_eth_hdr = 1'b1;
ptr_next = 0;
send_eth_header_next = 1'b1;
send_eth_payload_next = (OFFSET != 0) && (CYCLE_COUNT == 1);
s_eth_payload_axis_tready_next = send_eth_payload_next && m_axis_tready_int_early;
end
if (send_eth_payload_reg) begin
s_eth_payload_axis_tready_next = m_axis_tready_int_early && shift_eth_payload_axis_input_tready;
if ((s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) || (m_axis_tready_int_reg && shift_eth_payload_axis_extra_cycle_reg)) begin
transfer_in_save = 1'b1;
m_axis_tdata_int = shift_eth_payload_axis_tdata;
m_axis_tkeep_int = shift_eth_payload_axis_tkeep;
m_axis_tvalid_int = 1'b1;
m_axis_tlast_int = shift_eth_payload_axis_tlast;
m_axis_tuser_int = shift_eth_payload_axis_tuser;
if (shift_eth_payload_axis_tlast) begin
flush_save = 1'b1;
s_eth_payload_axis_tready_next = 1'b0;
ptr_next = 0;
send_eth_payload_next = 1'b0;
end
end
end
if (m_axis_tready_int_reg && (!OFFSET || !send_eth_payload_reg || m_axis_tvalid_int)) begin
if (send_eth_header_reg) begin
ptr_next = ptr_reg + 1;
if ((OFFSET != 0) && (CYCLE_COUNT == 1 || ptr_next == CYCLE_COUNT-1) && !send_eth_payload_reg) begin
send_eth_payload_next = 1'b1;
s_eth_payload_axis_tready_next = m_axis_tready_int_early && shift_eth_payload_axis_input_tready;
end
m_axis_tvalid_int = 1'b1;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/KEEP_WIDTH) begin \
m_axis_tdata_int[(offset%KEEP_WIDTH)*8 +: 8] = field; \
m_axis_tkeep_int[offset%KEEP_WIDTH] = 1'b1; \
end
`_HEADER_FIELD_(0, eth_dest_mac_reg[5*8 +: 8])
`_HEADER_FIELD_(1, eth_dest_mac_reg[4*8 +: 8])
`_HEADER_FIELD_(2, eth_dest_mac_reg[3*8 +: 8])
`_HEADER_FIELD_(3, eth_dest_mac_reg[2*8 +: 8])
`_HEADER_FIELD_(4, eth_dest_mac_reg[1*8 +: 8])
`_HEADER_FIELD_(5, eth_dest_mac_reg[0*8 +: 8])
`_HEADER_FIELD_(6, eth_src_mac_reg[5*8 +: 8])
`_HEADER_FIELD_(7, eth_src_mac_reg[4*8 +: 8])
`_HEADER_FIELD_(8, eth_src_mac_reg[3*8 +: 8])
`_HEADER_FIELD_(9, eth_src_mac_reg[2*8 +: 8])
`_HEADER_FIELD_(10, eth_src_mac_reg[1*8 +: 8])
`_HEADER_FIELD_(11, eth_src_mac_reg[0*8 +: 8])
`_HEADER_FIELD_(12, eth_type_reg[1*8 +: 8])
`_HEADER_FIELD_(13, eth_type_reg[0*8 +: 8])
if (ptr_reg == 13/KEEP_WIDTH) begin
if (!send_eth_payload_reg) begin
s_eth_payload_axis_tready_next = m_axis_tready_int_early;
send_eth_payload_next = 1'b1;
end
send_eth_header_next = 1'b0;
end
`undef _HEADER_FIELD_
end
end
s_eth_hdr_ready_next = !(send_eth_header_next || send_eth_payload_next);
end
always @(posedge clk) begin
send_eth_header_reg <= send_eth_header_next;
send_eth_payload_reg <= send_eth_payload_next;
ptr_reg <= ptr_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
busy_reg <= send_eth_header_next || send_eth_payload_next;
if (store_eth_hdr) begin
eth_dest_mac_reg <= s_eth_dest_mac;
eth_src_mac_reg <= s_eth_src_mac;
eth_type_reg <= s_eth_type;
end
if (transfer_in_save) begin
save_eth_payload_axis_tdata_reg <= s_eth_payload_axis_tdata;
save_eth_payload_axis_tkeep_reg <= s_eth_payload_axis_tkeep;
save_eth_payload_axis_tuser_reg <= s_eth_payload_axis_tuser;
end
if (flush_save) begin
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_axis_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_eth_payload_axis_tlast_reg <= s_eth_payload_axis_tlast;
shift_eth_payload_axis_extra_cycle_reg <= OFFSET ? s_eth_payload_axis_tlast && ((s_eth_payload_axis_tkeep & ({KEEP_WIDTH{1'b1}} << (KEEP_WIDTH-OFFSET))) != 0) : 1'b0;
end
if (rst) begin
send_eth_header_reg <= 1'b0;
send_eth_payload_reg <= 1'b0;
ptr_reg <= 0;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
corundum/lib/eth/rtl/eth_demux.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet demultiplexer
*/
module eth_demux #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire [ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame outputs
*/
output wire [M_COUNT-1:0] m_eth_hdr_valid,
input wire [M_COUNT-1:0] m_eth_hdr_ready,
output wire [M_COUNT*48-1:0] m_eth_dest_mac,
output wire [M_COUNT*48-1:0] m_eth_src_mac,
output wire [M_COUNT*16-1:0] m_eth_type,
output wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire [M_COUNT-1:0] m_eth_payload_axis_tvalid,
input wire [M_COUNT-1:0] m_eth_payload_axis_tready,
output wire [M_COUNT-1:0] m_eth_payload_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
parameter CL_M_COUNT = $clog2(M_COUNT);
reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg [M_COUNT-1:0] m_eth_hdr_valid_reg = 0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg && enable;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg && enable;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = {M_COUNT{m_eth_dest_mac_reg}};
assign m_eth_src_mac = {M_COUNT{m_eth_src_mac_reg}};
assign m_eth_type = {M_COUNT{m_eth_type_reg}};
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg & ~m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready) begin
// end of frame detection
if (s_eth_payload_axis_tlast) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && s_eth_hdr_valid && s_eth_hdr_ready) begin
// start of frame, grab select value
select_ctl = select;
drop_ctl = drop;
frame_ctl = 1'b1;
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = frame_ctl;
s_eth_hdr_ready_next = 1'b0;
m_eth_hdr_valid_next = (!drop_ctl) << select_ctl;
m_eth_dest_mac_next = s_eth_dest_mac;
m_eth_src_mac_next = s_eth_src_mac;
m_eth_type_next = s_eth_type;
end
s_eth_hdr_ready_next = !frame_next && !m_eth_hdr_valid_next;
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early || drop_ctl) && frame_ctl;
m_eth_payload_axis_tdata_int = s_eth_payload_axis_tdata;
m_eth_payload_axis_tkeep_int = s_eth_payload_axis_tkeep;
m_eth_payload_axis_tvalid_int = (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready && !drop_ctl) << select_ctl;
m_eth_payload_axis_tlast_int = s_eth_payload_axis_tlast;
m_eth_payload_axis_tid_int = s_eth_payload_axis_tid;
m_eth_payload_axis_tdest_int = s_eth_payload_axis_tdest;
m_eth_payload_axis_tuser_int = s_eth_payload_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 0;
end else begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] temp_m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = {M_COUNT{m_eth_payload_axis_tdata_reg}};
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_eth_payload_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = {M_COUNT{m_eth_payload_axis_tlast_reg}};
assign m_eth_payload_axis_tid = ID_ENABLE ? {M_COUNT{m_eth_payload_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? {M_COUNT{m_eth_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? {M_COUNT{m_eth_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if ((m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || !m_eth_payload_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
corundum/lib/eth/rtl/eth_mac_10g.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC
*/
module eth_mac_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
// bus width assertions
initial begin
if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin
$error("Error: Interface width must be 32 or 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
generate
if (DATA_WIDTH == 64) begin
axis_xgmii_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_xgmii_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
end else begin
axis_xgmii_rx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet[0]),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
assign rx_start_packet[1] = 1'b0;
axis_xgmii_tx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet[0])
);
assign tx_start_packet[1] = 1'b0;
end
endgenerate
endmodule
corundum/lib/eth/rtl/eth_mac_10g_fifo.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC with TX and RX FIFOs
*/
module eth_mac_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO,
parameter LOGIC_PTP_PERIOD_NS = 4'h6,
parameter LOGIC_PTP_PERIOD_FNS = 16'h6666,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter TX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter RX_PTP_TS_FIFO_DEPTH = 64,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 0,
parameter PTP_TAG_WIDTH = 16
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* Transmit timestamp tag input
*/
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* Receive timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96,
output wire m_axis_rx_ptp_ts_valid,
input wire m_axis_rx_ptp_ts_ready,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
localparam TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
localparam RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
wire tx_axis_tvalid_int;
wire tx_axis_tready_int;
wire tx_axis_tlast_int;
wire [TX_USER_WIDTH-1:0] tx_axis_tuser_int;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
wire [PTP_TS_WIDTH-1:0] rx_axis_ptp_ts_96;
wire rx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (TX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
if (TX_PTP_TAG_ENABLE) begin
ptp_tag_insert #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.TAG_WIDTH(PTP_TAG_WIDTH),
.TAG_OFFSET(1),
.USER_WIDTH(TX_USER_WIDTH)
)
tx_ptp_tag_insert (
.clk(logic_clk),
.rst(logic_rst),
// AXI stream input
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
// AXI stream input
.m_axis_tdata(tx_axis_tdata_int),
.m_axis_tkeep(tx_axis_tkeep_int),
.m_axis_tvalid(tx_axis_tvalid_int),
.m_axis_tready(tx_axis_tready_int),
.m_axis_tlast(tx_axis_tlast_int),
.m_axis_tuser(tx_axis_tuser_int),
// Tag input
.s_axis_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tag_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tag_ready(s_axis_tx_ptp_ts_ready)
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TAG_WIDTH+PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata({tx_axis_ptp_ts_tag, tx_axis_ptp_ts_96}),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata({m_axis_tx_ptp_ts_tag, m_axis_tx_ptp_ts_96}),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign tx_axis_tdata_int = tx_axis_tdata;
assign tx_axis_tkeep_int = tx_axis_tkeep;
assign tx_axis_tvalid_int = tx_axis_tvalid;
assign tx_axis_tready = tx_axis_tready_int;
assign tx_axis_tlast_int = tx_axis_tlast;
assign tx_axis_tuser_int = tx_axis_tuser;
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
assign s_axis_tx_ptp_ts_ready = 1'b0;
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
end
end else begin
assign s_axis_tx_ptp_ts_ready = 1'b0;
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign tx_axis_tdata_int = tx_axis_tdata;
assign tx_axis_tkeep_int = tx_axis_tkeep;
assign tx_axis_tvalid_int = tx_axis_tvalid;
assign tx_axis_tready = tx_axis_tready_int;
assign tx_axis_tlast_int = tx_axis_tlast;
assign tx_axis_tuser_int = tx_axis_tuser;
end
if (RX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
axis_fifo #(
.DEPTH(RX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_ptp_ts_fifo (
.clk(logic_clk),
.rst(logic_rst),
// AXI input
.s_axis_tdata(rx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(m_axis_rx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_rx_ptp_ts_valid),
.m_axis_tready(m_axis_rx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
ptp_ts_extract #(
.TS_WIDTH(PTP_TS_WIDTH),
.TS_OFFSET(1),
.USER_WIDTH(RX_USER_WIDTH)
)
rx_ptp_ts_extract (
.clk(logic_clk),
.rst(logic_rst),
// AXI stream input
.s_axis_tvalid(rx_axis_tvalid && rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser_int),
// Timestamp output
.m_axis_ts(rx_axis_ptp_ts_96),
.m_axis_ts_valid(rx_axis_ptp_ts_valid)
);
end else begin
assign m_axis_rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_rx_ptp_ts_valid = 1'b0;
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
assign rx_axis_tuser = rx_axis_tuser_int[0];
endgenerate
eth_mac_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH)
)
eth_mac_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata_int),
.s_axis_tkeep(tx_axis_tkeep_int),
.s_axis_tvalid(tx_axis_tvalid_int),
.s_axis_tready(tx_axis_tready_int),
.s_axis_tlast(tx_axis_tlast_int),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser_int),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser_int),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
corundum/lib/eth/rtl/eth_mac_1g.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC
*/
module eth_mac_1g #
(
parameter DATA_WIDTH = 8,
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* GMII interface
*/
input wire [DATA_WIDTH-1:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [DATA_WIDTH-1:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_start_packet,
output wire tx_error_underflow,
output wire rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
axis_gmii_rx #(
.DATA_WIDTH(DATA_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_gmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.clk_enable(rx_clk_enable),
.mii_select(rx_mii_select),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_gmii_tx #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_gmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.clk_enable(tx_clk_enable),
.mii_select(tx_mii_select),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
endmodule
corundum/lib/eth/rtl/eth_mac_1g_fifo.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC with TX and RX FIFOs
*/
module eth_mac_1g_fifo #
(
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.rx_clk_enable(rx_clk_enable),
.tx_clk_enable(tx_clk_enable),
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
corundum/lib/eth/rtl/eth_mac_1g_gmii.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC with GMII interface
*/
module eth_mac_1g_gmii #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire gtx_clk,
input wire gtx_rst,
output wire rx_clk,
output wire rx_rst,
output wire tx_clk,
output wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire gmii_rx_clk,
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
input wire mii_tx_clk,
output wire gmii_tx_clk,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Status
*/
output wire tx_error_underflow,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] mac_gmii_rxd;
wire mac_gmii_rx_dv;
wire mac_gmii_rx_er;
wire [7:0] mac_gmii_txd;
wire mac_gmii_tx_en;
wire mac_gmii_tx_er;
reg [1:0] speed_reg = 2'b10;
reg mii_select_reg = 1'b0;
(* srl_style = "register" *)
reg [1:0] tx_mii_select_sync = 2'd0;
always @(posedge tx_clk) begin
tx_mii_select_sync <= {tx_mii_select_sync[0], mii_select_reg};
end
(* srl_style = "register" *)
reg [1:0] rx_mii_select_sync = 2'd0;
always @(posedge rx_clk) begin
rx_mii_select_sync <= {rx_mii_select_sync[0], mii_select_reg};
end
// PHY speed detection
reg [2:0] rx_prescale = 3'd0;
always @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1;
end
(* srl_style = "register" *)
reg [2:0] rx_prescale_sync = 3'd0;
always @(posedge gtx_clk) begin
rx_prescale_sync <= {rx_prescale_sync[1:0], rx_prescale[2]};
end
reg [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0;
always @(posedge gtx_clk) begin
if (gtx_rst) begin
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end else begin
rx_speed_count_1 <= rx_speed_count_1 + 1;
if (rx_prescale_sync[1] ^ rx_prescale_sync[2]) begin
rx_speed_count_2 <= rx_speed_count_2 + 1;
end
if (&rx_speed_count_1) begin
// reference count overflow - 10M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b00;
mii_select_reg <= 1'b1;
end
if (&rx_speed_count_2) begin
// prescaled count overflow - 100M or 1000M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
if (rx_speed_count_1[6:5]) begin
// large reference count - 100M
speed_reg <= 2'b01;
mii_select_reg <= 1'b1;
end else begin
// small reference count - 1000M
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end
end
end
end
assign speed = speed_reg;
gmii_phy_if #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE)
)
gmii_phy_if_inst (
.clk(gtx_clk),
.rst(gtx_rst),
.mac_gmii_rx_clk(rx_clk),
.mac_gmii_rx_rst(rx_rst),
.mac_gmii_rxd(mac_gmii_rxd),
.mac_gmii_rx_dv(mac_gmii_rx_dv),
.mac_gmii_rx_er(mac_gmii_rx_er),
.mac_gmii_tx_clk(tx_clk),
.mac_gmii_tx_rst(tx_rst),
.mac_gmii_txd(mac_gmii_txd),
.mac_gmii_tx_en(mac_gmii_tx_en),
.mac_gmii_tx_er(mac_gmii_tx_er),
.phy_gmii_rx_clk(gmii_rx_clk),
.phy_gmii_rxd(gmii_rxd),
.phy_gmii_rx_dv(gmii_rx_dv),
.phy_gmii_rx_er(gmii_rx_er),
.phy_mii_tx_clk(mii_tx_clk),
.phy_gmii_tx_clk(gmii_tx_clk),
.phy_gmii_txd(gmii_txd),
.phy_gmii_tx_en(gmii_tx_en),
.phy_gmii_tx_er(gmii_tx_er),
.mii_select(mii_select_reg)
);
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(mac_gmii_rxd),
.gmii_rx_dv(mac_gmii_rx_dv),
.gmii_rx_er(mac_gmii_rx_er),
.gmii_txd(mac_gmii_txd),
.gmii_tx_en(mac_gmii_tx_en),
.gmii_tx_er(mac_gmii_tx_er),
.rx_clk_enable(1'b1),
.tx_clk_enable(1'b1),
.rx_mii_select(rx_mii_select_sync[1]),
.tx_mii_select(tx_mii_select_sync[1]),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
corundum/lib/eth/rtl/eth_mac_1g_gmii_fifo.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC with GMII interface and TX and RX FIFOs
*/
module eth_mac_1g_gmii_fifo #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
)
(
input wire gtx_clk,
input wire gtx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire gmii_rx_clk,
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
input wire mii_tx_clk,
output wire gmii_tx_clk,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire tx_clk;
wire rx_clk;
wire tx_rst;
wire rx_rst;
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
wire [1:0] speed_int;
reg [1:0] speed_sync_reg_1 = 2'b10;
reg [1:0] speed_sync_reg_2 = 2'b10;
assign speed = speed_sync_reg_2;
always @(posedge logic_clk) begin
speed_sync_reg_1 <= speed_int;
speed_sync_reg_2 <= speed_sync_reg_1;
end
eth_mac_1g_gmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_gmii_inst (
.gtx_clk(gtx_clk),
.gtx_rst(gtx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.gmii_rx_clk(gmii_rx_clk),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_tx_clk(gmii_tx_clk),
.mii_tx_clk(mii_tx_clk),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.speed(speed_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
corundum/lib/eth/rtl/eth_mac_1g_rgmii.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC with RGMII interface
*/
module eth_mac_1g_rgmii #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire gtx_clk,
input wire gtx_clk90,
input wire gtx_rst,
output wire rx_clk,
output wire rx_rst,
output wire tx_clk,
output wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* RGMII interface
*/
input wire rgmii_rx_clk,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
output wire rgmii_tx_clk,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
/*
* Status
*/
output wire tx_error_underflow,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] mac_gmii_rxd;
wire mac_gmii_rx_dv;
wire mac_gmii_rx_er;
wire mac_gmii_tx_clk_en;
wire [7:0] mac_gmii_txd;
wire mac_gmii_tx_en;
wire mac_gmii_tx_er;
reg [1:0] speed_reg = 2'b10;
reg mii_select_reg = 1'b0;
(* srl_style = "register" *)
reg [1:0] tx_mii_select_sync = 2'd0;
always @(posedge tx_clk) begin
tx_mii_select_sync <= {tx_mii_select_sync[0], mii_select_reg};
end
(* srl_style = "register" *)
reg [1:0] rx_mii_select_sync = 2'd0;
always @(posedge rx_clk) begin
rx_mii_select_sync <= {rx_mii_select_sync[0], mii_select_reg};
end
// PHY speed detection
reg [2:0] rx_prescale = 3'd0;
always @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1;
end
(* srl_style = "register" *)
reg [2:0] rx_prescale_sync = 3'd0;
always @(posedge gtx_clk) begin
rx_prescale_sync <= {rx_prescale_sync[1:0], rx_prescale[2]};
end
reg [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0;
always @(posedge gtx_clk) begin
if (gtx_rst) begin
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end else begin
rx_speed_count_1 <= rx_speed_count_1 + 1;
if (rx_prescale_sync[1] ^ rx_prescale_sync[2]) begin
rx_speed_count_2 <= rx_speed_count_2 + 1;
end
if (&rx_speed_count_1) begin
// reference count overflow - 10M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b00;
mii_select_reg <= 1'b1;
end
if (&rx_speed_count_2) begin
// prescaled count overflow - 100M or 1000M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
if (rx_speed_count_1[6:5]) begin
// large reference count - 100M
speed_reg <= 2'b01;
mii_select_reg <= 1'b1;
end else begin
// small reference count - 1000M
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end
end
end
end
assign speed = speed_reg;
rgmii_phy_if #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90)
)
rgmii_phy_if_inst (
.clk(gtx_clk),
.clk90(gtx_clk90),
.rst(gtx_rst),
.mac_gmii_rx_clk(rx_clk),
.mac_gmii_rx_rst(rx_rst),
.mac_gmii_rxd(mac_gmii_rxd),
.mac_gmii_rx_dv(mac_gmii_rx_dv),
.mac_gmii_rx_er(mac_gmii_rx_er),
.mac_gmii_tx_clk(tx_clk),
.mac_gmii_tx_rst(tx_rst),
.mac_gmii_tx_clk_en(mac_gmii_tx_clk_en),
.mac_gmii_txd(mac_gmii_txd),
.mac_gmii_tx_en(mac_gmii_tx_en),
.mac_gmii_tx_er(mac_gmii_tx_er),
.phy_rgmii_rx_clk(rgmii_rx_clk),
.phy_rgmii_rxd(rgmii_rxd),
.phy_rgmii_rx_ctl(rgmii_rx_ctl),
.phy_rgmii_tx_clk(rgmii_tx_clk),
.phy_rgmii_txd(rgmii_txd),
.phy_rgmii_tx_ctl(rgmii_tx_ctl),
.speed(speed)
);
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(mac_gmii_rxd),
.gmii_rx_dv(mac_gmii_rx_dv),
.gmii_rx_er(mac_gmii_rx_er),
.gmii_txd(mac_gmii_txd),
.gmii_tx_en(mac_gmii_tx_en),
.gmii_tx_er(mac_gmii_tx_er),
.rx_clk_enable(1'b1),
.tx_clk_enable(mac_gmii_tx_clk_en),
.rx_mii_select(rx_mii_select_sync[1]),
.tx_mii_select(tx_mii_select_sync[1]),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
corundum/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC with RGMII interface and TX and RX FIFOs
*/
module eth_mac_1g_rgmii_fifo #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
)
(
input wire gtx_clk,
input wire gtx_clk90,
input wire gtx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* RGMII interface
*/
input wire rgmii_rx_clk,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
output wire rgmii_tx_clk,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire tx_clk;
wire rx_clk;
wire tx_rst;
wire rx_rst;
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
wire [1:0] speed_int;
reg [1:0] speed_sync_reg_1 = 2'b10;
reg [1:0] speed_sync_reg_2 = 2'b10;
assign speed = speed_sync_reg_2;
always @(posedge logic_clk) begin
speed_sync_reg_1 <= speed_int;
speed_sync_reg_2 <= speed_sync_reg_1;
end
eth_mac_1g_rgmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_rgmii_inst (
.gtx_clk(gtx_clk),
.gtx_clk90(gtx_clk90),
.gtx_rst(gtx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.rgmii_rx_clk(rgmii_rx_clk),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_tx_clk(rgmii_tx_clk),
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.speed(speed_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
corundum/lib/eth/rtl/eth_mac_mii.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10M/100M Ethernet MAC with MII interface
*/
module eth_mac_mii #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire rst,
output wire rx_clk,
output wire rx_rst,
output wire tx_clk,
output wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* MII interface
*/
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
/*
* Status
*/
output wire tx_start_packet,
output wire tx_error_underflow,
output wire rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [3:0] mac_mii_rxd;
wire mac_mii_rx_dv;
wire mac_mii_rx_er;
wire [3:0] mac_mii_txd;
wire mac_mii_tx_en;
wire mac_mii_tx_er;
mii_phy_if #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE)
)
mii_phy_if_inst (
.rst(rst),
.mac_mii_rx_clk(rx_clk),
.mac_mii_rx_rst(rx_rst),
.mac_mii_rxd(mac_mii_rxd),
.mac_mii_rx_dv(mac_mii_rx_dv),
.mac_mii_rx_er(mac_mii_rx_er),
.mac_mii_tx_clk(tx_clk),
.mac_mii_tx_rst(tx_rst),
.mac_mii_txd(mac_mii_txd),
.mac_mii_tx_en(mac_mii_tx_en),
.mac_mii_tx_er(mac_mii_tx_er),
.phy_mii_rx_clk(mii_rx_clk),
.phy_mii_rxd(mii_rxd),
.phy_mii_rx_dv(mii_rx_dv),
.phy_mii_rx_er(mii_rx_er),
.phy_mii_tx_clk(mii_tx_clk),
.phy_mii_txd(mii_txd),
.phy_mii_tx_en(mii_tx_en),
.phy_mii_tx_er(mii_tx_er)
);
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(mac_mii_rxd),
.gmii_rx_dv(mac_mii_rx_dv),
.gmii_rx_er(mac_mii_rx_er),
.gmii_txd(mac_mii_txd),
.gmii_tx_en(mac_mii_tx_en),
.gmii_tx_er(mac_mii_tx_er),
.rx_clk_enable(1'b1),
.tx_clk_enable(1'b1),
.rx_mii_select(1'b1),
.tx_mii_select(1'b1),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
corundum/lib/eth/rtl/eth_mac_mii_fifo.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10M/100M Ethernet MAC with MII interface and TX and RX FIFOs
*/
module eth_mac_mii_fifo #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
)
(
input wire rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* MII interface
*/
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire tx_clk;
wire rx_clk;
wire tx_rst;
wire rx_rst;
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_mii #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_mii_inst (
.rst(rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.mii_rx_clk(mii_rx_clk),
.mii_rxd(mii_rxd),
.mii_rx_dv(mii_rx_dv),
.mii_rx_er(mii_rx_er),
.mii_tx_clk(mii_tx_clk),
.mii_txd(mii_txd),
.mii_tx_en(mii_tx_en),
.mii_tx_er(mii_tx_er),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
corundum/lib/eth/rtl/eth_mac_phy_10g.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire [6:0] rx_error_count,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
eth_mac_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.ptp_ts(rx_ptp_ts),
.rx_start_packet(rx_start_packet),
.rx_error_count(rx_error_count),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
eth_mac_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_mac_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
corundum/lib/eth/rtl/eth_mac_phy_10g_fifo.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination with TX and RX FIFOs
*/
module eth_mac_phy_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter COUNT_125US = 125000/6.4,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO,
parameter LOGIC_PTP_PERIOD_NS = 4'h6,
parameter LOGIC_PTP_PERIOD_FNS = 16'h6666,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter TX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter RX_PTP_TS_FIFO_DEPTH = 64,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 0,
parameter PTP_TAG_WIDTH = 16
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* Transmit timestamp tag input
*/
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* Receive timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96,
output wire m_axis_rx_ptp_ts_valid,
input wire m_axis_rx_ptp_ts_ready,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
localparam TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
localparam RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
wire tx_axis_tvalid_int;
wire tx_axis_tready_int;
wire tx_axis_tlast_int;
wire [TX_USER_WIDTH-1:0] tx_axis_tuser_int;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
wire [PTP_TS_WIDTH-1:0] rx_axis_ptp_ts_96;
wire rx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [4:0] rx_sync_reg_1 = 5'd0;
reg [4:0] rx_sync_reg_2 = 5'd0;
reg [4:0] rx_sync_reg_3 = 5'd0;
reg [4:0] rx_sync_reg_4 = 5'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
assign rx_block_lock = rx_sync_reg_3[3] ^ rx_sync_reg_4[3];
assign rx_high_ber = rx_sync_reg_3[4] ^ rx_sync_reg_4[4];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 5'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_high_ber_int, rx_block_lock_int, rx_bad_block_int, rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 5'd0;
rx_sync_reg_3 <= 5'd0;
rx_sync_reg_4 <= 5'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (TX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
if (TX_PTP_TAG_ENABLE) begin
ptp_tag_insert #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.TAG_WIDTH(PTP_TAG_WIDTH),
.TAG_OFFSET(1),
.USER_WIDTH(TX_USER_WIDTH)
)
tx_ptp_tag_insert (
.clk(logic_clk),
.rst(logic_rst),
// AXI stream input
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
// AXI stream input
.m_axis_tdata(tx_axis_tdata_int),
.m_axis_tkeep(tx_axis_tkeep_int),
.m_axis_tvalid(tx_axis_tvalid_int),
.m_axis_tready(tx_axis_tready_int),
.m_axis_tlast(tx_axis_tlast_int),
.m_axis_tuser(tx_axis_tuser_int),
// Tag input
.s_axis_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tag_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tag_ready(s_axis_tx_ptp_ts_ready)
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TAG_WIDTH+PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata({tx_axis_ptp_ts_tag, tx_axis_ptp_ts_96}),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata({m_axis_tx_ptp_ts_tag, m_axis_tx_ptp_ts_96}),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign tx_axis_tdata_int = tx_axis_tdata;
assign tx_axis_tkeep_int = tx_axis_tkeep;
assign tx_axis_tvalid_int = tx_axis_tvalid;
assign tx_axis_tready = tx_axis_tready_int;
assign tx_axis_tlast_int = tx_axis_tlast;
assign tx_axis_tuser_int = tx_axis_tuser;
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
assign s_axis_tx_ptp_ts_ready = 1'b0;
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
end
end else begin
assign s_axis_tx_ptp_ts_ready = 1'b0;
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign tx_axis_tdata_int = tx_axis_tdata;
assign tx_axis_tkeep_int = tx_axis_tkeep;
assign tx_axis_tvalid_int = tx_axis_tvalid;
assign tx_axis_tready = tx_axis_tready_int;
assign tx_axis_tlast_int = tx_axis_tlast;
assign tx_axis_tuser_int = tx_axis_tuser;
end
if (RX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
axis_fifo #(
.DEPTH(RX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_ptp_ts_fifo (
.clk(logic_clk),
.rst(logic_rst),
// AXI input
.s_axis_tdata(rx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(m_axis_rx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_rx_ptp_ts_valid),
.m_axis_tready(m_axis_rx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
ptp_ts_extract #(
.TS_WIDTH(PTP_TS_WIDTH),
.TS_OFFSET(1),
.USER_WIDTH(RX_USER_WIDTH)
)
rx_ptp_ts_extract (
.clk(logic_clk),
.rst(logic_rst),
// AXI stream input
.s_axis_tvalid(rx_axis_tvalid && rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser_int),
// Timestamp output
.m_axis_ts(rx_axis_ptp_ts_96),
.m_axis_ts_valid(rx_axis_ptp_ts_valid)
);
end else begin
assign m_axis_rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_rx_ptp_ts_valid = 1'b0;
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
assign rx_axis_tuser = rx_axis_tuser_int[0];
endgenerate
eth_mac_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.rx_bad_block(rx_bad_block_int),
.rx_block_lock(rx_block_lock_int),
.rx_high_ber(rx_high_ber_int),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata_int),
.s_axis_tkeep(tx_axis_tkeep_int),
.s_axis_tvalid(tx_axis_tvalid_int),
.s_axis_tready(tx_axis_tready_int),
.s_axis_tlast(tx_axis_tlast_int),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser_int),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser_int),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
corundum/lib/eth/rtl/eth_mac_phy_10g_rx.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g_rx #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Status
*/
output wire [1:0] rx_start_packet,
output wire [6:0] rx_error_count,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH * 32 != DATA_WIDTH) begin
$error("Error: HDR_WIDTH must be equal to DATA_WIDTH/32");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
axis_baser_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
axis_baser_rx_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.ptp_ts(ptp_ts),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block)
);
endmodule
corundum/lib/eth/rtl/eth_mac_phy_10g_tx.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g_tx #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH * 32 != DATA_WIDTH) begin
$error("Error: HDR_WIDTH must be equal to DATA_WIDTH/32");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
axis_baser_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
axis_baser_tx_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay)
);
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
corundum/lib/eth/rtl/eth_mux.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet multiplexer
*/
module eth_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame inputs
*/
input wire [S_COUNT-1:0] s_eth_hdr_valid,
output wire [S_COUNT-1:0] s_eth_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_eth_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_eth_payload_axis_tready,
input wire [S_COUNT-1:0] s_eth_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_eth_hdr_ready_reg = 0, s_eth_hdr_ready_next;
reg [S_COUNT-1:0] s_eth_payload_axis_tready_reg = 0, s_eth_payload_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_eth_payload_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_eth_payload_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_eth_payload_axis_tvalid[select_reg];
wire current_s_tready = s_eth_payload_axis_tready[select_reg];
wire current_s_tlast = s_eth_payload_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_eth_payload_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_eth_payload_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_eth_hdr_ready_next = 0;
s_eth_payload_axis_tready_next = 0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && !m_eth_hdr_valid && (s_eth_hdr_valid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
s_eth_hdr_ready_next = (1 << select);
m_eth_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[select*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[select*48 +: 48];
m_eth_type_next = s_eth_type[select*16 +: 16];
end
// generate ready signal on selected port
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_eth_payload_axis_tdata_int = current_s_tdata;
m_eth_payload_axis_tkeep_int = current_s_tkeep;
m_eth_payload_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_eth_payload_axis_tlast_int = current_s_tlast;
m_eth_payload_axis_tid_int = current_s_tid;
m_eth_payload_axis_tdest_int = current_s_tdest;
m_eth_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= 0;
s_eth_payload_axis_tready_reg <= 0;
m_eth_hdr_valid_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tid = ID_ENABLE ? m_eth_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
corundum/lib/eth/rtl/eth_phy_10g.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY
*/
module eth_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
eth_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
eth_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
corundum/lib/eth/rtl/eth_phy_10g_rx.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY RX
*/
module eth_phy_10g_rx #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
xgmii_baser_dec_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
xgmii_baser_dec_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.rx_bad_block(rx_bad_block)
);
endmodule
corundum/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY BER monitor
*/
module eth_phy_10g_rx_ber_mon #
(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
/*
* Status
*/
output wire rx_high_ber
);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
parameter COUNT_WIDTH = $clog2(COUNT_125US);
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [COUNT_WIDTH-1:0] time_count_reg = 0, time_count_next;
reg [3:0] ber_count_reg = 4'd0, ber_count_next;
reg rx_high_ber_reg = 1'b0, rx_high_ber_next;
assign rx_high_ber = rx_high_ber_reg;
always @* begin
if (time_count_reg > 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = time_count_reg;
end
ber_count_next = ber_count_reg;
rx_high_ber_next = rx_high_ber_reg;
if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
if (ber_count_reg != 4'd15) begin
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end else begin
// invalid header
if (ber_count_reg == 4'd15) begin
rx_high_ber_next = 1'b1;
end else begin
ber_count_next = ber_count_reg + 1;
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end
if (time_count_reg == 0) begin
// 125 us timer expired
ber_count_next = 4'd0;
time_count_next = COUNT_125US;
end
end
always @(posedge clk) begin
if (rst) begin
time_count_reg <= COUNT_125US;
ber_count_reg <= 4'd0;
rx_high_ber_reg <= 1'b0;
end else begin
time_count_reg <= time_count_next;
ber_count_reg <= ber_count_next;
rx_high_ber_reg <= rx_high_ber_next;
end
end
endmodule
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