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Commit 738c1fef authored by Antoine Kaufmann's avatar Antoine Kaufmann
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add corundum and verilator build files

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corundum/lib/axi/rtl/axil_cdc.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite clock domain crossing module
*/
module axil_cdc #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8)
)
(
/*
* AXI lite slave interface
*/
input wire s_clk,
input wire s_rst,
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* AXI lite master interface
*/
input wire m_clk,
input wire m_rst,
output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [DATA_WIDTH-1:0] m_axil_wdata,
output wire [STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready,
output wire [ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready
);
axil_cdc_wr #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH)
)
axil_cdc_wr_inst (
/*
* AXI lite slave interface
*/
.s_clk(s_clk),
.s_rst(s_rst),
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
.s_axil_wstrb(s_axil_wstrb),
.s_axil_wvalid(s_axil_wvalid),
.s_axil_wready(s_axil_wready),
.s_axil_bresp(s_axil_bresp),
.s_axil_bvalid(s_axil_bvalid),
.s_axil_bready(s_axil_bready),
/*
* AXI lite master interface
*/
.m_clk(m_clk),
.m_rst(m_rst),
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready)
);
axil_cdc_rd #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH)
)
axil_cdc_rd_inst (
/*
* AXI lite slave interface
*/
.s_clk(s_clk),
.s_rst(s_rst),
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready),
/*
* AXI lite master interface
*/
.m_clk(m_clk),
.m_rst(m_rst),
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready)
);
endmodule
corundum/lib/axi/rtl/axil_cdc_rd.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite clock domain crossing module (read)
*/
module axil_cdc_rd #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8)
)
(
/*
* AXI lite slave interface
*/
input wire s_clk,
input wire s_rst,
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* AXI lite master interface
*/
input wire m_clk,
input wire m_rst,
output wire [ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready
);
reg [1:0] s_state_reg = 2'd0;
reg s_flag_reg = 1'b0;
(* srl_style = "register" *)
reg s_flag_sync_reg_1 = 1'b0;
(* srl_style = "register" *)
reg s_flag_sync_reg_2 = 1'b0;
reg [1:0] m_state_reg = 2'd0;
reg m_flag_reg = 1'b0;
(* srl_style = "register" *)
reg m_flag_sync_reg_1 = 1'b0;
(* srl_style = "register" *)
reg m_flag_sync_reg_2 = 1'b0;
reg [ADDR_WIDTH-1:0] s_axil_araddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] s_axil_arprot_reg = 3'd0;
reg s_axil_arvalid_reg = 1'b0;
reg [DATA_WIDTH-1:0] s_axil_rdata_reg = {DATA_WIDTH{1'b0}};
reg [1:0] s_axil_rresp_reg = 2'b00;
reg s_axil_rvalid_reg = 1'b0;
reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] m_axil_arprot_reg = 3'd0;
reg m_axil_arvalid_reg = 1'b0;
reg [DATA_WIDTH-1:0] m_axil_rdata_reg = {DATA_WIDTH{1'b0}};
reg [1:0] m_axil_rresp_reg = 2'b00;
reg m_axil_rvalid_reg = 1'b1;
assign s_axil_arready = !s_axil_arvalid_reg && !s_axil_rvalid_reg;
assign s_axil_rdata = s_axil_rdata_reg;
assign s_axil_rresp = s_axil_rresp_reg;
assign s_axil_rvalid = s_axil_rvalid_reg;
assign m_axil_araddr = m_axil_araddr_reg;
assign m_axil_arprot = m_axil_arprot_reg;
assign m_axil_arvalid = m_axil_arvalid_reg;
assign m_axil_rready = !m_axil_rvalid_reg;
// slave side
always @(posedge s_clk) begin
s_axil_rvalid_reg <= s_axil_rvalid_reg && !s_axil_rready;
if (!s_axil_arvalid_reg && !s_axil_rvalid_reg) begin
s_axil_araddr_reg <= s_axil_araddr;
s_axil_arprot_reg <= s_axil_arprot;
s_axil_arvalid_reg <= s_axil_arvalid;
end
case (s_state_reg)
2'd0: begin
if (s_axil_arvalid_reg) begin
s_state_reg <= 2'd1;
s_flag_reg <= 1'b1;
end
end
2'd1: begin
if (m_flag_sync_reg_2) begin
s_state_reg <= 2'd2;
s_flag_reg <= 1'b0;
s_axil_rdata_reg <= m_axil_rdata_reg;
s_axil_rresp_reg <= m_axil_rresp_reg;
s_axil_rvalid_reg <= 1'b1;
end
end
2'd2: begin
if (!m_flag_sync_reg_2) begin
s_state_reg <= 2'd0;
s_axil_arvalid_reg <= 1'b0;
end
end
endcase
if (s_rst) begin
s_state_reg <= 2'd0;
s_flag_reg <= 1'b0;
s_axil_arvalid_reg <= 1'b0;
s_axil_rvalid_reg <= 1'b0;
end
end
// synchronization
always @(posedge s_clk) begin
m_flag_sync_reg_1 <= m_flag_reg;
m_flag_sync_reg_2 <= m_flag_sync_reg_1;
end
always @(posedge m_clk) begin
s_flag_sync_reg_1 <= s_flag_reg;
s_flag_sync_reg_2 <= s_flag_sync_reg_1;
end
// master side
always @(posedge m_clk) begin
m_axil_arvalid_reg <= m_axil_arvalid_reg && !m_axil_arready;
if (!m_axil_rvalid_reg) begin
m_axil_rdata_reg <= m_axil_rdata;
m_axil_rresp_reg <= m_axil_rresp;
m_axil_rvalid_reg <= m_axil_rvalid;
end
case (m_state_reg)
2'd0: begin
if (s_flag_sync_reg_2) begin
m_state_reg <= 2'd1;
m_axil_araddr_reg <= s_axil_araddr_reg;
m_axil_arprot_reg <= s_axil_arprot_reg;
m_axil_arvalid_reg <= 1'b1;
m_axil_rvalid_reg <= 1'b0;
end
end
2'd1: begin
if (m_axil_rvalid_reg) begin
m_flag_reg <= 1'b1;
m_state_reg <= 2'd2;
end
end
2'd2: begin
if (!s_flag_sync_reg_2) begin
m_state_reg <= 2'd0;
m_flag_reg <= 1'b0;
end
end
endcase
if (m_rst) begin
m_state_reg <= 2'd0;
m_flag_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rvalid_reg <= 1'b1;
end
end
endmodule
corundum/lib/axi/rtl/axil_cdc_wr.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite clock domain crossing module (write)
*/
module axil_cdc_wr #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8)
)
(
/*
* AXI lite slave interface
*/
input wire s_clk,
input wire s_rst,
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
/*
* AXI lite master interface
*/
input wire m_clk,
input wire m_rst,
output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [DATA_WIDTH-1:0] m_axil_wdata,
output wire [STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready
);
reg [1:0] s_state_reg = 2'd0;
reg s_flag_reg = 1'b0;
(* srl_style = "register" *)
reg s_flag_sync_reg_1 = 1'b0;
(* srl_style = "register" *)
reg s_flag_sync_reg_2 = 1'b0;
reg [1:0] m_state_reg = 2'd0;
reg m_flag_reg = 1'b0;
(* srl_style = "register" *)
reg m_flag_sync_reg_1 = 1'b0;
(* srl_style = "register" *)
reg m_flag_sync_reg_2 = 1'b0;
reg [ADDR_WIDTH-1:0] s_axil_awaddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] s_axil_awprot_reg = 3'd0;
reg s_axil_awvalid_reg = 1'b0;
reg [DATA_WIDTH-1:0] s_axil_wdata_reg = {DATA_WIDTH{1'b0}};
reg [STRB_WIDTH-1:0] s_axil_wstrb_reg = {STRB_WIDTH{1'b0}};
reg s_axil_wvalid_reg = 1'b0;
reg [1:0] s_axil_bresp_reg = 2'b00;
reg s_axil_bvalid_reg = 1'b0;
reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] m_axil_awprot_reg = 3'd0;
reg m_axil_awvalid_reg = 1'b0;
reg [DATA_WIDTH-1:0] m_axil_wdata_reg = {DATA_WIDTH{1'b0}};
reg [STRB_WIDTH-1:0] m_axil_wstrb_reg = {STRB_WIDTH{1'b0}};
reg m_axil_wvalid_reg = 1'b0;
reg [1:0] m_axil_bresp_reg = 2'b00;
reg m_axil_bvalid_reg = 1'b1;
assign s_axil_awready = !s_axil_awvalid_reg && !s_axil_bvalid_reg;
assign s_axil_wready = !s_axil_wvalid_reg && !s_axil_bvalid_reg;
assign s_axil_bresp = s_axil_bresp_reg;
assign s_axil_bvalid = s_axil_bvalid_reg;
assign m_axil_awaddr = m_axil_awaddr_reg;
assign m_axil_awprot = m_axil_awprot_reg;
assign m_axil_awvalid = m_axil_awvalid_reg;
assign m_axil_wdata = m_axil_wdata_reg;
assign m_axil_wstrb = m_axil_wstrb_reg;
assign m_axil_wvalid = m_axil_wvalid_reg;
assign m_axil_bready = !m_axil_bvalid_reg;
// slave side
always @(posedge s_clk) begin
s_axil_bvalid_reg <= s_axil_bvalid_reg && !s_axil_bready;
if (!s_axil_awvalid_reg && !s_axil_bvalid_reg) begin
s_axil_awaddr_reg <= s_axil_awaddr;
s_axil_awprot_reg <= s_axil_awprot;
s_axil_awvalid_reg <= s_axil_awvalid;
end
if (!s_axil_wvalid_reg && !s_axil_bvalid_reg) begin
s_axil_wdata_reg <= s_axil_wdata;
s_axil_wstrb_reg <= s_axil_wstrb;
s_axil_wvalid_reg <= s_axil_wvalid;
end
case (s_state_reg)
2'd0: begin
if (s_axil_awvalid_reg && s_axil_wvalid_reg) begin
s_state_reg <= 2'd1;
s_flag_reg <= 1'b1;
end
end
2'd1: begin
if (m_flag_sync_reg_2) begin
s_state_reg <= 2'd2;
s_flag_reg <= 1'b0;
s_axil_bresp_reg <= m_axil_bresp_reg;
s_axil_bvalid_reg <= 1'b1;
end
end
2'd2: begin
if (!m_flag_sync_reg_2) begin
s_state_reg <= 2'd0;
s_axil_awvalid_reg <= 1'b0;
s_axil_wvalid_reg <= 1'b0;
end
end
endcase
if (s_rst) begin
s_state_reg <= 2'd0;
s_flag_reg <= 1'b0;
s_axil_awvalid_reg <= 1'b0;
s_axil_wvalid_reg <= 1'b0;
s_axil_bvalid_reg <= 1'b0;
end
end
// synchronization
always @(posedge s_clk) begin
m_flag_sync_reg_1 <= m_flag_reg;
m_flag_sync_reg_2 <= m_flag_sync_reg_1;
end
always @(posedge m_clk) begin
s_flag_sync_reg_1 <= s_flag_reg;
s_flag_sync_reg_2 <= s_flag_sync_reg_1;
end
// master side
always @(posedge m_clk) begin
m_axil_awvalid_reg <= m_axil_awvalid_reg && !m_axil_awready;
m_axil_wvalid_reg <= m_axil_wvalid_reg && !m_axil_wready;
if (!m_axil_bvalid_reg) begin
m_axil_bresp_reg <= m_axil_bresp;
m_axil_bvalid_reg <= m_axil_bvalid;
end
case (m_state_reg)
2'd0: begin
if (s_flag_sync_reg_2) begin
m_state_reg <= 2'd1;
m_axil_awaddr_reg <= s_axil_awaddr_reg;
m_axil_awprot_reg <= s_axil_awprot_reg;
m_axil_awvalid_reg <= 1'b1;
m_axil_wdata_reg <= s_axil_wdata_reg;
m_axil_wstrb_reg <= s_axil_wstrb_reg;
m_axil_wvalid_reg <= 1'b1;
m_axil_bvalid_reg <= 1'b0;
end
end
2'd1: begin
if (m_axil_bvalid_reg) begin
m_flag_reg <= 1'b1;
m_state_reg <= 2'd2;
end
end
2'd2: begin
if (!s_flag_sync_reg_2) begin
m_state_reg <= 2'd0;
m_flag_reg <= 1'b0;
end
end
endcase
if (m_rst) begin
m_state_reg <= 2'd0;
m_flag_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bvalid_reg <= 1'b1;
end
end
endmodule
corundum/lib/axi/rtl/axil_dp_ram.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Lite dual port RAM
*/
module axil_dp_ram #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 16,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Extra pipeline register on output
parameter PIPELINE_OUTPUT = 0
)
(
input wire a_clk,
input wire a_rst,
input wire b_clk,
input wire b_rst,
input wire [ADDR_WIDTH-1:0] s_axil_a_awaddr,
input wire [2:0] s_axil_a_awprot,
input wire s_axil_a_awvalid,
output wire s_axil_a_awready,
input wire [DATA_WIDTH-1:0] s_axil_a_wdata,
input wire [STRB_WIDTH-1:0] s_axil_a_wstrb,
input wire s_axil_a_wvalid,
output wire s_axil_a_wready,
output wire [1:0] s_axil_a_bresp,
output wire s_axil_a_bvalid,
input wire s_axil_a_bready,
input wire [ADDR_WIDTH-1:0] s_axil_a_araddr,
input wire [2:0] s_axil_a_arprot,
input wire s_axil_a_arvalid,
output wire s_axil_a_arready,
output wire [DATA_WIDTH-1:0] s_axil_a_rdata,
output wire [1:0] s_axil_a_rresp,
output wire s_axil_a_rvalid,
input wire s_axil_a_rready,
input wire [ADDR_WIDTH-1:0] s_axil_b_awaddr,
input wire [2:0] s_axil_b_awprot,
input wire s_axil_b_awvalid,
output wire s_axil_b_awready,
input wire [DATA_WIDTH-1:0] s_axil_b_wdata,
input wire [STRB_WIDTH-1:0] s_axil_b_wstrb,
input wire s_axil_b_wvalid,
output wire s_axil_b_wready,
output wire [1:0] s_axil_b_bresp,
output wire s_axil_b_bvalid,
input wire s_axil_b_bready,
input wire [ADDR_WIDTH-1:0] s_axil_b_araddr,
input wire [2:0] s_axil_b_arprot,
input wire s_axil_b_arvalid,
output wire s_axil_b_arready,
output wire [DATA_WIDTH-1:0] s_axil_b_rdata,
output wire [1:0] s_axil_b_rresp,
output wire s_axil_b_rvalid,
input wire s_axil_b_rready
);
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
parameter WORD_WIDTH = STRB_WIDTH;
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg read_eligible_a;
reg write_eligible_a;
reg read_eligible_b;
reg write_eligible_b;
reg mem_wr_en_a;
reg mem_rd_en_a;
reg mem_wr_en_b;
reg mem_rd_en_b;
reg last_read_a_reg = 1'b0, last_read_a_next;
reg last_read_b_reg = 1'b0, last_read_b_next;
reg s_axil_a_awready_reg = 1'b0, s_axil_a_awready_next;
reg s_axil_a_wready_reg = 1'b0, s_axil_a_wready_next;
reg s_axil_a_bvalid_reg = 1'b0, s_axil_a_bvalid_next;
reg s_axil_a_arready_reg = 1'b0, s_axil_a_arready_next;
reg [DATA_WIDTH-1:0] s_axil_a_rdata_reg = {DATA_WIDTH{1'b0}}, s_axil_a_rdata_next;
reg s_axil_a_rvalid_reg = 1'b0, s_axil_a_rvalid_next;
reg [DATA_WIDTH-1:0] s_axil_a_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
reg s_axil_a_rvalid_pipe_reg = 1'b0;
reg s_axil_b_awready_reg = 1'b0, s_axil_b_awready_next;
reg s_axil_b_wready_reg = 1'b0, s_axil_b_wready_next;
reg s_axil_b_bvalid_reg = 1'b0, s_axil_b_bvalid_next;
reg s_axil_b_arready_reg = 1'b0, s_axil_b_arready_next;
reg [DATA_WIDTH-1:0] s_axil_b_rdata_reg = {DATA_WIDTH{1'b0}}, s_axil_b_rdata_next;
reg s_axil_b_rvalid_reg = 1'b0, s_axil_b_rvalid_next;
reg [DATA_WIDTH-1:0] s_axil_b_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
reg s_axil_b_rvalid_pipe_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] s_axil_a_awaddr_valid = s_axil_a_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] s_axil_a_araddr_valid = s_axil_a_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] s_axil_b_awaddr_valid = s_axil_b_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] s_axil_b_araddr_valid = s_axil_b_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign s_axil_a_awready = s_axil_a_awready_reg;
assign s_axil_a_wready = s_axil_a_wready_reg;
assign s_axil_a_bresp = 2'b00;
assign s_axil_a_bvalid = s_axil_a_bvalid_reg;
assign s_axil_a_arready = s_axil_a_arready_reg;
assign s_axil_a_rdata = PIPELINE_OUTPUT ? s_axil_a_rdata_pipe_reg : s_axil_a_rdata_reg;
assign s_axil_a_rresp = 2'b00;
assign s_axil_a_rvalid = PIPELINE_OUTPUT ? s_axil_a_rvalid_pipe_reg : s_axil_a_rvalid_reg;
assign s_axil_b_awready = s_axil_b_awready_reg;
assign s_axil_b_wready = s_axil_b_wready_reg;
assign s_axil_b_bresp = 2'b00;
assign s_axil_b_bvalid = s_axil_b_bvalid_reg;
assign s_axil_b_arready = s_axil_b_arready_reg;
assign s_axil_b_rdata = PIPELINE_OUTPUT ? s_axil_b_rdata_pipe_reg : s_axil_b_rdata_reg;
assign s_axil_b_rresp = 2'b00;
assign s_axil_b_rvalid = PIPELINE_OUTPUT ? s_axil_b_rvalid_pipe_reg : s_axil_b_rvalid_reg;
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
mem[j] = 0;
end
end
end
always @* begin
mem_wr_en_a = 1'b0;
mem_rd_en_a = 1'b0;
last_read_a_next = last_read_a_reg;
s_axil_a_awready_next = 1'b0;
s_axil_a_wready_next = 1'b0;
s_axil_a_bvalid_next = s_axil_a_bvalid_reg && !s_axil_a_bready;
s_axil_a_arready_next = 1'b0;
s_axil_a_rvalid_next = s_axil_a_rvalid_reg && !(s_axil_a_rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg));
write_eligible_a = s_axil_a_awvalid && s_axil_a_wvalid && (!s_axil_a_bvalid || s_axil_a_bready) && (!s_axil_a_awready && !s_axil_a_wready);
read_eligible_a = s_axil_a_arvalid && (!s_axil_a_rvalid || s_axil_a_rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg)) && (!s_axil_a_arready);
if (write_eligible_a && (!read_eligible_a || last_read_a_reg)) begin
last_read_a_next = 1'b0;
s_axil_a_awready_next = 1'b1;
s_axil_a_wready_next = 1'b1;
s_axil_a_bvalid_next = 1'b1;
mem_wr_en_a = 1'b1;
end else if (read_eligible_a) begin
last_read_a_next = 1'b1;
s_axil_a_arready_next = 1'b1;
s_axil_a_rvalid_next = 1'b1;
mem_rd_en_a = 1'b1;
end
end
always @(posedge a_clk) begin
if (a_rst) begin
last_read_a_reg <= 1'b0;
s_axil_a_awready_reg <= 1'b0;
s_axil_a_wready_reg <= 1'b0;
s_axil_a_bvalid_reg <= 1'b0;
s_axil_a_arready_reg <= 1'b0;
s_axil_a_rvalid_reg <= 1'b0;
s_axil_a_rvalid_pipe_reg <= 1'b0;
end else begin
last_read_a_reg <= last_read_a_next;
s_axil_a_awready_reg <= s_axil_a_awready_next;
s_axil_a_wready_reg <= s_axil_a_wready_next;
s_axil_a_bvalid_reg <= s_axil_a_bvalid_next;
s_axil_a_arready_reg <= s_axil_a_arready_next;
s_axil_a_rvalid_reg <= s_axil_a_rvalid_next;
if (!s_axil_a_rvalid_pipe_reg || s_axil_a_rready) begin
s_axil_a_rvalid_pipe_reg <= s_axil_a_rvalid_reg;
end
end
if (mem_rd_en_a) begin
s_axil_a_rdata_reg <= mem[s_axil_a_araddr_valid];
end else begin
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (mem_wr_en_a && s_axil_a_wstrb[i]) begin
mem[s_axil_a_awaddr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axil_a_wdata[WORD_SIZE*i +: WORD_SIZE];
end
end
end
if (!s_axil_a_rvalid_pipe_reg || s_axil_a_rready) begin
s_axil_a_rdata_pipe_reg <= s_axil_a_rdata_reg;
end
end
always @* begin
mem_wr_en_b = 1'b0;
mem_rd_en_b = 1'b0;
last_read_b_next = last_read_b_reg;
s_axil_b_awready_next = 1'b0;
s_axil_b_wready_next = 1'b0;
s_axil_b_bvalid_next = s_axil_b_bvalid_reg && !s_axil_b_bready;
s_axil_b_arready_next = 1'b0;
s_axil_b_rvalid_next = s_axil_b_rvalid_reg && !(s_axil_b_rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg));
write_eligible_b = s_axil_b_awvalid && s_axil_b_wvalid && (!s_axil_b_bvalid || s_axil_b_bready) && (!s_axil_b_awready && !s_axil_b_wready);
read_eligible_b = s_axil_b_arvalid && (!s_axil_b_rvalid || s_axil_b_rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg)) && (!s_axil_b_arready);
if (write_eligible_b && (!read_eligible_b || last_read_b_reg)) begin
last_read_b_next = 1'b0;
s_axil_b_awready_next = 1'b1;
s_axil_b_wready_next = 1'b1;
s_axil_b_bvalid_next = 1'b1;
mem_wr_en_b = 1'b1;
end else if (read_eligible_b) begin
last_read_b_next = 1'b1;
s_axil_b_arready_next = 1'b1;
s_axil_b_rvalid_next = 1'b1;
mem_rd_en_b = 1'b1;
end
end
always @(posedge b_clk) begin
if (b_rst) begin
last_read_b_reg <= 1'b0;
s_axil_b_awready_reg <= 1'b0;
s_axil_b_wready_reg <= 1'b0;
s_axil_b_bvalid_reg <= 1'b0;
s_axil_b_arready_reg <= 1'b0;
s_axil_b_rvalid_reg <= 1'b0;
s_axil_b_rvalid_pipe_reg <= 1'b0;
end else begin
last_read_b_reg <= last_read_b_next;
s_axil_b_awready_reg <= s_axil_b_awready_next;
s_axil_b_wready_reg <= s_axil_b_wready_next;
s_axil_b_bvalid_reg <= s_axil_b_bvalid_next;
s_axil_b_arready_reg <= s_axil_b_arready_next;
s_axil_b_rvalid_reg <= s_axil_b_rvalid_next;
if (!s_axil_b_rvalid_pipe_reg || s_axil_b_rready) begin
s_axil_b_rvalid_pipe_reg <= s_axil_b_rvalid_reg;
end
end
if (mem_rd_en_b) begin
s_axil_b_rdata_reg <= mem[s_axil_b_araddr_valid];
end else begin
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (mem_wr_en_b && s_axil_b_wstrb[i]) begin
mem[s_axil_b_awaddr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axil_b_wdata[WORD_SIZE*i +: WORD_SIZE];
end
end
end
if (!s_axil_b_rvalid_pipe_reg || s_axil_b_rready) begin
s_axil_b_rdata_pipe_reg <= s_axil_b_rdata_reg;
end
end
endmodule
corundum/lib/axi/rtl/axil_interconnect.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite interconnect
*/
module axil_interconnect #
(
// Number of AXI inputs (slave interfaces)
parameter S_COUNT = 4,
// Number of AXI outputs (master interfaces)
parameter M_COUNT = 4,
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Number of regions per master interface
parameter M_REGIONS = 1,
// Master interface base addresses
// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
// set to zero for default addressing based on M_ADDR_WIDTH
parameter M_BASE_ADDR = 0,
// Master interface address widths
// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
// Read connections between interfaces
// M_COUNT concatenated fields of S_COUNT bits
parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},
// Write connections between interfaces
// M_COUNT concatenated fields of S_COUNT bits
parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}},
// Secure master (fail operations based on awprot/arprot)
// M_COUNT bits
parameter M_SECURE = {M_COUNT{1'b0}}
)
(
input wire clk,
input wire rst,
/*
* AXI lite slave interfaces
*/
input wire [S_COUNT*ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [S_COUNT*3-1:0] s_axil_awprot,
input wire [S_COUNT-1:0] s_axil_awvalid,
output wire [S_COUNT-1:0] s_axil_awready,
input wire [S_COUNT*DATA_WIDTH-1:0] s_axil_wdata,
input wire [S_COUNT*STRB_WIDTH-1:0] s_axil_wstrb,
input wire [S_COUNT-1:0] s_axil_wvalid,
output wire [S_COUNT-1:0] s_axil_wready,
output wire [S_COUNT*2-1:0] s_axil_bresp,
output wire [S_COUNT-1:0] s_axil_bvalid,
input wire [S_COUNT-1:0] s_axil_bready,
input wire [S_COUNT*ADDR_WIDTH-1:0] s_axil_araddr,
input wire [S_COUNT*3-1:0] s_axil_arprot,
input wire [S_COUNT-1:0] s_axil_arvalid,
output wire [S_COUNT-1:0] s_axil_arready,
output wire [S_COUNT*DATA_WIDTH-1:0] s_axil_rdata,
output wire [S_COUNT*2-1:0] s_axil_rresp,
output wire [S_COUNT-1:0] s_axil_rvalid,
input wire [S_COUNT-1:0] s_axil_rready,
/*
* AXI lite master interfaces
*/
output wire [M_COUNT*ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [M_COUNT*3-1:0] m_axil_awprot,
output wire [M_COUNT-1:0] m_axil_awvalid,
input wire [M_COUNT-1:0] m_axil_awready,
output wire [M_COUNT*DATA_WIDTH-1:0] m_axil_wdata,
output wire [M_COUNT*STRB_WIDTH-1:0] m_axil_wstrb,
output wire [M_COUNT-1:0] m_axil_wvalid,
input wire [M_COUNT-1:0] m_axil_wready,
input wire [M_COUNT*2-1:0] m_axil_bresp,
input wire [M_COUNT-1:0] m_axil_bvalid,
output wire [M_COUNT-1:0] m_axil_bready,
output wire [M_COUNT*ADDR_WIDTH-1:0] m_axil_araddr,
output wire [M_COUNT*3-1:0] m_axil_arprot,
output wire [M_COUNT-1:0] m_axil_arvalid,
input wire [M_COUNT-1:0] m_axil_arready,
input wire [M_COUNT*DATA_WIDTH-1:0] m_axil_rdata,
input wire [M_COUNT*2-1:0] m_axil_rresp,
input wire [M_COUNT-1:0] m_axil_rvalid,
output wire [M_COUNT-1:0] m_axil_rready
);
parameter CL_S_COUNT = $clog2(S_COUNT);
parameter CL_M_COUNT = $clog2(M_COUNT);
// default address computation
function [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy);
integer i;
reg [ADDR_WIDTH-1:0] base;
begin
calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}};
base = 0;
for (i = 1; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32]) begin
base = base + 2**M_ADDR_WIDTH[(i-1)*32 +: 32]; // increment
base = base - (base % 2**M_ADDR_WIDTH[i*32 +: 32]); // align
calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base;
end
end
end
endfunction
parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0);
integer i, j;
// check configuration
initial begin
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 0 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
$error("Error: address width out of range (instance %m)");
$finish;
end
end
$display("Addressing configuration for axil_interconnect instance %m");
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32]) begin
$display("%2d (%2d): %x / %2d -- %x-%x", i/M_REGIONS, i%M_REGIONS, M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[i*32 +: 32], M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])));
end
end
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin
if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])))) && ((M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin
$display("Overlapping regions:");
$display("%2d (%2d): %x / %2d -- %x-%x", i/M_REGIONS, i%M_REGIONS, M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[i*32 +: 32], M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])));
$display("%2d (%2d): %x / %2d -- %x-%x", j/M_REGIONS, j%M_REGIONS, M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[j*32 +: 32], M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]), M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])));
$error("Error: address ranges overlap (instance %m)");
$finish;
end
end
end
end
end
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_DECODE = 3'd1,
STATE_WRITE = 3'd2,
STATE_WRITE_RESP = 3'd3,
STATE_WRITE_DROP = 3'd4,
STATE_READ = 3'd5,
STATE_WAIT_IDLE = 3'd6;
reg [2:0] state_reg = STATE_IDLE, state_next;
reg match;
reg [CL_M_COUNT-1:0] m_select_reg = 2'd0, m_select_next;
reg [ADDR_WIDTH-1:0] axil_addr_reg = {ADDR_WIDTH{1'b0}}, axil_addr_next;
reg axil_addr_valid_reg = 1'b0, axil_addr_valid_next;
reg [2:0] axil_prot_reg = 3'b000, axil_prot_next;
reg [DATA_WIDTH-1:0] axil_data_reg = {DATA_WIDTH{1'b0}}, axil_data_next;
reg [STRB_WIDTH-1:0] axil_wstrb_reg = {STRB_WIDTH{1'b0}}, axil_wstrb_next;
reg [1:0] axil_resp_reg = 2'b00, axil_resp_next;
reg [S_COUNT-1:0] s_axil_awready_reg = 0, s_axil_awready_next;
reg [S_COUNT-1:0] s_axil_wready_reg = 0, s_axil_wready_next;
reg [S_COUNT-1:0] s_axil_bvalid_reg = 0, s_axil_bvalid_next;
reg [S_COUNT-1:0] s_axil_arready_reg = 0, s_axil_arready_next;
reg [S_COUNT-1:0] s_axil_rvalid_reg = 0, s_axil_rvalid_next;
reg [M_COUNT-1:0] m_axil_awvalid_reg = 0, m_axil_awvalid_next;
reg [M_COUNT-1:0] m_axil_wvalid_reg = 0, m_axil_wvalid_next;
reg [M_COUNT-1:0] m_axil_bready_reg = 0, m_axil_bready_next;
reg [M_COUNT-1:0] m_axil_arvalid_reg = 0, m_axil_arvalid_next;
reg [M_COUNT-1:0] m_axil_rready_reg = 0, m_axil_rready_next;
assign s_axil_awready = s_axil_awready_reg;
assign s_axil_wready = s_axil_wready_reg;
assign s_axil_bresp = {S_COUNT{axil_resp_reg}};
assign s_axil_bvalid = s_axil_bvalid_reg;
assign s_axil_arready = s_axil_arready_reg;
assign s_axil_rdata = {S_COUNT{axil_data_reg}};
assign s_axil_rresp = {S_COUNT{axil_resp_reg}};
assign s_axil_rvalid = s_axil_rvalid_reg;
assign m_axil_awaddr = {M_COUNT{axil_addr_reg}};
assign m_axil_awprot = {M_COUNT{axil_prot_reg}};
assign m_axil_awvalid = m_axil_awvalid_reg;
assign m_axil_wdata = {M_COUNT{axil_data_reg}};
assign m_axil_wstrb = {M_COUNT{axil_wstrb_reg}};
assign m_axil_wvalid = m_axil_wvalid_reg;
assign m_axil_bready = m_axil_bready_reg;
assign m_axil_araddr = {M_COUNT{axil_addr_reg}};
assign m_axil_arprot = {M_COUNT{axil_prot_reg}};
assign m_axil_arvalid = m_axil_arvalid_reg;
assign m_axil_rready = m_axil_rready_reg;
// slave side mux
wire [(CL_S_COUNT > 0 ? CL_S_COUNT-1 : 0):0] s_select;
wire [ADDR_WIDTH-1:0] current_s_axil_awaddr = s_axil_awaddr[s_select*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_s_axil_awprot = s_axil_awprot[s_select*3 +: 3];
wire current_s_axil_awvalid = s_axil_awvalid[s_select];
wire current_s_axil_awready = s_axil_awready[s_select];
wire [DATA_WIDTH-1:0] current_s_axil_wdata = s_axil_wdata[s_select*DATA_WIDTH +: DATA_WIDTH];
wire [STRB_WIDTH-1:0] current_s_axil_wstrb = s_axil_wstrb[s_select*STRB_WIDTH +: STRB_WIDTH];
wire current_s_axil_wvalid = s_axil_wvalid[s_select];
wire current_s_axil_wready = s_axil_wready[s_select];
wire [1:0] current_s_axil_bresp = s_axil_bresp[s_select*2 +: 2];
wire current_s_axil_bvalid = s_axil_bvalid[s_select];
wire current_s_axil_bready = s_axil_bready[s_select];
wire [ADDR_WIDTH-1:0] current_s_axil_araddr = s_axil_araddr[s_select*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_s_axil_arprot = s_axil_arprot[s_select*3 +: 3];
wire current_s_axil_arvalid = s_axil_arvalid[s_select];
wire current_s_axil_arready = s_axil_arready[s_select];
wire [DATA_WIDTH-1:0] current_s_axil_rdata = s_axil_rdata[s_select*DATA_WIDTH +: DATA_WIDTH];
wire [1:0] current_s_axil_rresp = s_axil_rresp[s_select*2 +: 2];
wire current_s_axil_rvalid = s_axil_rvalid[s_select];
wire current_s_axil_rready = s_axil_rready[s_select];
// master side mux
wire [ADDR_WIDTH-1:0] current_m_axil_awaddr = m_axil_awaddr[m_select_reg*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_m_axil_awprot = m_axil_awprot[m_select_reg*3 +: 3];
wire current_m_axil_awvalid = m_axil_awvalid[m_select_reg];
wire current_m_axil_awready = m_axil_awready[m_select_reg];
wire [DATA_WIDTH-1:0] current_m_axil_wdata = m_axil_wdata[m_select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [STRB_WIDTH-1:0] current_m_axil_wstrb = m_axil_wstrb[m_select_reg*STRB_WIDTH +: STRB_WIDTH];
wire current_m_axil_wvalid = m_axil_wvalid[m_select_reg];
wire current_m_axil_wready = m_axil_wready[m_select_reg];
wire [1:0] current_m_axil_bresp = m_axil_bresp[m_select_reg*2 +: 2];
wire current_m_axil_bvalid = m_axil_bvalid[m_select_reg];
wire current_m_axil_bready = m_axil_bready[m_select_reg];
wire [ADDR_WIDTH-1:0] current_m_axil_araddr = m_axil_araddr[m_select_reg*ADDR_WIDTH +: ADDR_WIDTH];
wire [2:0] current_m_axil_arprot = m_axil_arprot[m_select_reg*3 +: 3];
wire current_m_axil_arvalid = m_axil_arvalid[m_select_reg];
wire current_m_axil_arready = m_axil_arready[m_select_reg];
wire [DATA_WIDTH-1:0] current_m_axil_rdata = m_axil_rdata[m_select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [1:0] current_m_axil_rresp = m_axil_rresp[m_select_reg*2 +: 2];
wire current_m_axil_rvalid = m_axil_rvalid[m_select_reg];
wire current_m_axil_rready = m_axil_rready[m_select_reg];
// arbiter instance
wire [S_COUNT*2-1:0] request;
wire [S_COUNT*2-1:0] acknowledge;
wire [S_COUNT*2-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT:0] grant_encoded;
wire read = grant_encoded[0];
assign s_select = grant_encoded >> 1;
arbiter #(
.PORTS(S_COUNT*2),
.TYPE("ROUND_ROBIN"),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY("HIGH")
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
genvar n;
// request generation
generate
for (n = 0; n < S_COUNT; n = n + 1) begin
assign request[2*n] = s_axil_awvalid[n];
assign request[2*n+1] = s_axil_arvalid[n];
end
endgenerate
// acknowledge generation
generate
for (n = 0; n < S_COUNT; n = n + 1) begin
assign acknowledge[2*n] = grant[2*n] && s_axil_bvalid[n] && s_axil_bready[n];
assign acknowledge[2*n+1] = grant[2*n+1] && s_axil_rvalid[n] && s_axil_rready[n];
end
endgenerate
always @* begin
state_next = STATE_IDLE;
match = 1'b0;
m_select_next = m_select_reg;
axil_addr_next = axil_addr_reg;
axil_addr_valid_next = axil_addr_valid_reg;
axil_prot_next = axil_prot_reg;
axil_data_next = axil_data_reg;
axil_wstrb_next = axil_wstrb_reg;
axil_resp_next = axil_resp_reg;
s_axil_awready_next = 0;
s_axil_wready_next = 0;
s_axil_bvalid_next = s_axil_bvalid_reg & ~s_axil_bready;
s_axil_arready_next = 0;
s_axil_rvalid_next = s_axil_rvalid_reg & ~s_axil_rready;
m_axil_awvalid_next = m_axil_awvalid_reg & ~m_axil_awready;
m_axil_wvalid_next = m_axil_wvalid_reg & ~m_axil_wready;
m_axil_bready_next = 0;
m_axil_arvalid_next = m_axil_arvalid_reg & ~m_axil_arready;
m_axil_rready_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state; wait for arbitration
if (grant_valid) begin
axil_addr_valid_next = 1'b1;
if (read) begin
// reading
axil_addr_next = current_s_axil_araddr;
axil_prot_next = current_s_axil_arprot;
s_axil_arready_next[s_select] = 1'b1;
end else begin
// writing
axil_addr_next = current_s_axil_awaddr;
axil_prot_next = current_s_axil_awprot;
s_axil_awready_next[s_select] = 1'b1;
end
state_next = STATE_DECODE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DECODE: begin
// decode state; determine master interface
match = 1'b0;
for (i = 0; i < M_COUNT; i = i + 1) begin
for (j = 0; j < M_REGIONS; j = j + 1) begin
if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !axil_prot_reg[1]) && ((read ? M_CONNECT_READ : M_CONNECT_WRITE) & (1 << (s_select+i*S_COUNT))) && (axil_addr_reg >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin
m_select_next = i;
match = 1'b1;
end
end
end
if (match) begin
if (read) begin
// reading
m_axil_rready_next[m_select_next] = 1'b1;
state_next = STATE_READ;
end else begin
// writing
s_axil_wready_next[s_select] = 1'b1;
state_next = STATE_WRITE;
end
end else begin
// no match; return decode error
axil_data_next = {DATA_WIDTH{1'b0}};
axil_resp_next = 2'b11;
if (read) begin
// reading
s_axil_rvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
// writing
s_axil_wready_next[s_select] = 1'b1;
state_next = STATE_WRITE_DROP;
end
end
end
STATE_WRITE: begin
// write state; store and forward write data
s_axil_wready_next[s_select] = 1'b1;
if (axil_addr_valid_reg) begin
m_axil_awvalid_next[m_select_reg] = 1'b1;
end
axil_addr_valid_next = 1'b0;
if (current_s_axil_wready && current_s_axil_wvalid) begin
s_axil_wready_next[s_select] = 1'b0;
axil_data_next = current_s_axil_wdata;
axil_wstrb_next = current_s_axil_wstrb;
m_axil_wvalid_next[m_select_reg] = 1'b1;
m_axil_bready_next[m_select_reg] = 1'b1;
state_next = STATE_WRITE_RESP;
end else begin
state_next = STATE_WRITE;
end
end
STATE_WRITE_RESP: begin
// write response state; store and forward write response
m_axil_bready_next[m_select_reg] = 1'b1;
if (current_m_axil_bready && current_m_axil_bvalid) begin
m_axil_bready_next[m_select_reg] = 1'b0;
axil_resp_next = current_m_axil_bresp;
s_axil_bvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
state_next = STATE_WRITE_RESP;
end
end
STATE_WRITE_DROP: begin
// write drop state; drop write data
s_axil_wready_next[s_select] = 1'b1;
axil_addr_valid_next = 1'b0;
if (current_s_axil_wready && current_s_axil_wvalid) begin
s_axil_wready_next[s_select] = 1'b0;
s_axil_bvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
state_next = STATE_WRITE_DROP;
end
end
STATE_READ: begin
// read state; store and forward read response
m_axil_rready_next[m_select_reg] = 1'b1;
if (axil_addr_valid_reg) begin
m_axil_arvalid_next[m_select_reg] = 1'b1;
end
axil_addr_valid_next = 1'b0;
if (current_m_axil_rready && current_m_axil_rvalid) begin
m_axil_rready_next[m_select_reg] = 1'b0;
axil_data_next = current_m_axil_rdata;
axil_resp_next = current_m_axil_rresp;
s_axil_rvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;
end else begin
state_next = STATE_READ;
end
end
STATE_WAIT_IDLE: begin
// wait for idle state; wait untl grant valid is deasserted
if (!grant_valid || acknowledge) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_IDLE;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axil_awready_reg <= 0;
s_axil_wready_reg <= 0;
s_axil_bvalid_reg <= 0;
s_axil_arready_reg <= 0;
s_axil_rvalid_reg <= 0;
m_axil_awvalid_reg <= 0;
m_axil_wvalid_reg <= 0;
m_axil_bready_reg <= 0;
m_axil_arvalid_reg <= 0;
m_axil_rready_reg <= 0;
end else begin
state_reg <= state_next;
s_axil_awready_reg <= s_axil_awready_next;
s_axil_wready_reg <= s_axil_wready_next;
s_axil_bvalid_reg <= s_axil_bvalid_next;
s_axil_arready_reg <= s_axil_arready_next;
s_axil_rvalid_reg <= s_axil_rvalid_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
end
m_select_reg <= m_select_next;
axil_addr_reg <= axil_addr_next;
axil_addr_valid_reg <= axil_addr_valid_next;
axil_prot_reg <= axil_prot_next;
axil_data_reg <= axil_data_next;
axil_wstrb_reg <= axil_wstrb_next;
axil_resp_reg <= axil_resp_next;
end
endmodule
corundum/lib/axi/rtl/axil_ram.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Lite RAM
*/
module axil_ram #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 16,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Extra pipeline register on output
parameter PIPELINE_OUTPUT = 0
)
(
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready
);
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
parameter WORD_WIDTH = STRB_WIDTH;
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg mem_wr_en;
reg mem_rd_en;
reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
reg [DATA_WIDTH-1:0] s_axil_rdata_reg = {DATA_WIDTH{1'b0}}, s_axil_rdata_next;
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
reg [DATA_WIDTH-1:0] s_axil_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
reg s_axil_rvalid_pipe_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] s_axil_awaddr_valid = s_axil_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] s_axil_araddr_valid = s_axil_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign s_axil_awready = s_axil_awready_reg;
assign s_axil_wready = s_axil_wready_reg;
assign s_axil_bresp = 2'b00;
assign s_axil_bvalid = s_axil_bvalid_reg;
assign s_axil_arready = s_axil_arready_reg;
assign s_axil_rdata = PIPELINE_OUTPUT ? s_axil_rdata_pipe_reg : s_axil_rdata_reg;
assign s_axil_rresp = 2'b00;
assign s_axil_rvalid = PIPELINE_OUTPUT ? s_axil_rvalid_pipe_reg : s_axil_rvalid_reg;
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
mem[j] = 0;
end
end
end
always @* begin
mem_wr_en = 1'b0;
s_axil_awready_next = 1'b0;
s_axil_wready_next = 1'b0;
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
if (s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready)) begin
s_axil_awready_next = 1'b1;
s_axil_wready_next = 1'b1;
s_axil_bvalid_next = 1'b1;
mem_wr_en = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_awready_reg <= 1'b0;
s_axil_wready_reg <= 1'b0;
s_axil_bvalid_reg <= 1'b0;
end else begin
s_axil_awready_reg <= s_axil_awready_next;
s_axil_wready_reg <= s_axil_wready_next;
s_axil_bvalid_reg <= s_axil_bvalid_next;
end
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (mem_wr_en && s_axil_wstrb[i]) begin
mem[s_axil_awaddr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axil_wdata[WORD_SIZE*i +: WORD_SIZE];
end
end
end
always @* begin
mem_rd_en = 1'b0;
s_axil_arready_next = 1'b0;
s_axil_rvalid_next = s_axil_rvalid_reg && !(s_axil_rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg));
if (s_axil_arvalid && (!s_axil_rvalid || s_axil_rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg)) && (!s_axil_arready)) begin
s_axil_arready_next = 1'b1;
s_axil_rvalid_next = 1'b1;
mem_rd_en = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_arready_reg <= 1'b0;
s_axil_rvalid_reg <= 1'b0;
s_axil_rvalid_pipe_reg <= 1'b0;
end else begin
s_axil_arready_reg <= s_axil_arready_next;
s_axil_rvalid_reg <= s_axil_rvalid_next;
if (!s_axil_rvalid_pipe_reg || s_axil_rready) begin
s_axil_rvalid_pipe_reg <= s_axil_rvalid_reg;
end
end
if (mem_rd_en) begin
s_axil_rdata_reg <= mem[s_axil_araddr_valid];
end
if (!s_axil_rvalid_pipe_reg || s_axil_rready) begin
s_axil_rdata_pipe_reg <= s_axil_rdata_reg;
end
end
endmodule
corundum/lib/axi/rtl/axil_register.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite register
*/
module axil_register #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// AW channel register type
// 0 to bypass, 1 for simple buffer
parameter AW_REG_TYPE = 1,
// W channel register type
// 0 to bypass, 1 for simple buffer
parameter W_REG_TYPE = 1,
// B channel register type
// 0 to bypass, 1 for simple buffer
parameter B_REG_TYPE = 1,
// AR channel register type
// 0 to bypass, 1 for simple buffer
parameter AR_REG_TYPE = 1,
// R channel register type
// 0 to bypass, 1 for simple buffer
parameter R_REG_TYPE = 1
)
(
input wire clk,
input wire rst,
/*
* AXI lite slave interface
*/
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* AXI lite master interface
*/
output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [DATA_WIDTH-1:0] m_axil_wdata,
output wire [STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready,
output wire [ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready
);
axil_register_wr #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.AW_REG_TYPE(AW_REG_TYPE),
.W_REG_TYPE(W_REG_TYPE),
.B_REG_TYPE(B_REG_TYPE)
)
axil_register_wr_inst (
.clk(clk),
.rst(rst),
/*
* AXI lite slave interface
*/
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
.s_axil_wstrb(s_axil_wstrb),
.s_axil_wvalid(s_axil_wvalid),
.s_axil_wready(s_axil_wready),
.s_axil_bresp(s_axil_bresp),
.s_axil_bvalid(s_axil_bvalid),
.s_axil_bready(s_axil_bready),
/*
* AXI lite master interface
*/
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready)
);
axil_register_rd #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.AR_REG_TYPE(AR_REG_TYPE),
.R_REG_TYPE(R_REG_TYPE)
)
axil_register_rd_inst (
.clk(clk),
.rst(rst),
/*
* AXI lite slave interface
*/
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready),
/*
* AXI lite master interface
*/
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready)
);
endmodule
corundum/lib/axi/rtl/axil_register_rd.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite register (read)
*/
module axil_register_rd #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// AR channel register type
// 0 to bypass, 1 for simple buffer
parameter AR_REG_TYPE = 1,
// R channel register type
// 0 to bypass, 1 for simple buffer
parameter R_REG_TYPE = 1
)
(
input wire clk,
input wire rst,
/*
* AXI lite slave interface
*/
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* AXI lite master interface
*/
output wire [ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready
);
generate
// AR channel
if (AR_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
reg s_axil_arready_reg = 1'b0;
reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] m_axil_arprot_reg = 3'd0;
reg m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
reg [ADDR_WIDTH-1:0] temp_m_axil_araddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] temp_m_axil_arprot_reg = 3'd0;
reg temp_m_axil_arvalid_reg = 1'b0, temp_m_axil_arvalid_next;
// datapath control
reg store_axil_ar_input_to_output;
reg store_axil_ar_input_to_temp;
reg store_axil_ar_temp_to_output;
assign s_axil_arready = s_axil_arready_reg;
assign m_axil_araddr = m_axil_araddr_reg;
assign m_axil_arprot = m_axil_arprot_reg;
assign m_axil_arvalid = m_axil_arvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axil_arready_early = m_axil_arready | (~temp_m_axil_arvalid_reg & (~m_axil_arvalid_reg | ~s_axil_arvalid));
always @* begin
// transfer sink ready state to source
m_axil_arvalid_next = m_axil_arvalid_reg;
temp_m_axil_arvalid_next = temp_m_axil_arvalid_reg;
store_axil_ar_input_to_output = 1'b0;
store_axil_ar_input_to_temp = 1'b0;
store_axil_ar_temp_to_output = 1'b0;
if (s_axil_arready_reg) begin
// input is ready
if (m_axil_arready | ~m_axil_arvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axil_arvalid_next = s_axil_arvalid;
store_axil_ar_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axil_arvalid_next = s_axil_arvalid;
store_axil_ar_input_to_temp = 1'b1;
end
end else if (m_axil_arready) begin
// input is not ready, but output is ready
m_axil_arvalid_next = temp_m_axil_arvalid_reg;
temp_m_axil_arvalid_next = 1'b0;
store_axil_ar_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_arready_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
temp_m_axil_arvalid_reg <= 1'b0;
end else begin
s_axil_arready_reg <= s_axil_arready_early;
m_axil_arvalid_reg <= m_axil_arvalid_next;
temp_m_axil_arvalid_reg <= temp_m_axil_arvalid_next;
end
// datapath
if (store_axil_ar_input_to_output) begin
m_axil_araddr_reg <= s_axil_araddr;
m_axil_arprot_reg <= s_axil_arprot;
end else if (store_axil_ar_temp_to_output) begin
m_axil_araddr_reg <= temp_m_axil_araddr_reg;
m_axil_arprot_reg <= temp_m_axil_arprot_reg;
end
if (store_axil_ar_input_to_temp) begin
temp_m_axil_araddr_reg <= s_axil_araddr;
temp_m_axil_arprot_reg <= s_axil_arprot;
end
end
end else if (AR_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg s_axil_arready_reg = 1'b0;
reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] m_axil_arprot_reg = 3'd0;
reg m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
// datapath control
reg store_axil_ar_input_to_output;
assign s_axil_arready = s_axil_arready_reg;
assign m_axil_araddr = m_axil_araddr_reg;
assign m_axil_arprot = m_axil_arprot_reg;
assign m_axil_arvalid = m_axil_arvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axil_arready_early = !m_axil_arvalid_next;
always @* begin
// transfer sink ready state to source
m_axil_arvalid_next = m_axil_arvalid_reg;
store_axil_ar_input_to_output = 1'b0;
if (s_axil_arready_reg) begin
m_axil_arvalid_next = s_axil_arvalid;
store_axil_ar_input_to_output = 1'b1;
end else if (m_axil_arready) begin
m_axil_arvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_arready_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
end else begin
s_axil_arready_reg <= s_axil_arready_early;
m_axil_arvalid_reg <= m_axil_arvalid_next;
end
// datapath
if (store_axil_ar_input_to_output) begin
m_axil_araddr_reg <= s_axil_araddr;
m_axil_arprot_reg <= s_axil_arprot;
end
end
end else begin
// bypass AR channel
assign m_axil_araddr = s_axil_araddr;
assign m_axil_arprot = s_axil_arprot;
assign m_axil_arvalid = s_axil_arvalid;
assign s_axil_arready = m_axil_arready;
end
// R channel
if (R_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
reg m_axil_rready_reg = 1'b0;
reg [DATA_WIDTH-1:0] s_axil_rdata_reg = {DATA_WIDTH{1'b0}};
reg [1:0] s_axil_rresp_reg = 2'b0;
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
reg [DATA_WIDTH-1:0] temp_s_axil_rdata_reg = {DATA_WIDTH{1'b0}};
reg [1:0] temp_s_axil_rresp_reg = 2'b0;
reg temp_s_axil_rvalid_reg = 1'b0, temp_s_axil_rvalid_next;
// datapath control
reg store_axil_r_input_to_output;
reg store_axil_r_input_to_temp;
reg store_axil_r_temp_to_output;
assign m_axil_rready = m_axil_rready_reg;
assign s_axil_rdata = s_axil_rdata_reg;
assign s_axil_rresp = s_axil_rresp_reg;
assign s_axil_rvalid = s_axil_rvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire m_axil_rready_early = s_axil_rready | (~temp_s_axil_rvalid_reg & (~s_axil_rvalid_reg | ~m_axil_rvalid));
always @* begin
// transfer sink ready state to source
s_axil_rvalid_next = s_axil_rvalid_reg;
temp_s_axil_rvalid_next = temp_s_axil_rvalid_reg;
store_axil_r_input_to_output = 1'b0;
store_axil_r_input_to_temp = 1'b0;
store_axil_r_temp_to_output = 1'b0;
if (m_axil_rready_reg) begin
// input is ready
if (s_axil_rready | ~s_axil_rvalid_reg) begin
// output is ready or currently not valid, transfer data to output
s_axil_rvalid_next = m_axil_rvalid;
store_axil_r_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_s_axil_rvalid_next = m_axil_rvalid;
store_axil_r_input_to_temp = 1'b1;
end
end else if (s_axil_rready) begin
// input is not ready, but output is ready
s_axil_rvalid_next = temp_s_axil_rvalid_reg;
temp_s_axil_rvalid_next = 1'b0;
store_axil_r_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axil_rready_reg <= 1'b0;
s_axil_rvalid_reg <= 1'b0;
temp_s_axil_rvalid_reg <= 1'b0;
end else begin
m_axil_rready_reg <= m_axil_rready_early;
s_axil_rvalid_reg <= s_axil_rvalid_next;
temp_s_axil_rvalid_reg <= temp_s_axil_rvalid_next;
end
// datapath
if (store_axil_r_input_to_output) begin
s_axil_rdata_reg <= m_axil_rdata;
s_axil_rresp_reg <= m_axil_rresp;
end else if (store_axil_r_temp_to_output) begin
s_axil_rdata_reg <= temp_s_axil_rdata_reg;
s_axil_rresp_reg <= temp_s_axil_rresp_reg;
end
if (store_axil_r_input_to_temp) begin
temp_s_axil_rdata_reg <= m_axil_rdata;
temp_s_axil_rresp_reg <= m_axil_rresp;
end
end
end else if (R_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg m_axil_rready_reg = 1'b0;
reg [DATA_WIDTH-1:0] s_axil_rdata_reg = {DATA_WIDTH{1'b0}};
reg [1:0] s_axil_rresp_reg = 2'b0;
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
// datapath control
reg store_axil_r_input_to_output;
assign m_axil_rready = m_axil_rready_reg;
assign s_axil_rdata = s_axil_rdata_reg;
assign s_axil_rresp = s_axil_rresp_reg;
assign s_axil_rvalid = s_axil_rvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire m_axil_rready_early = !s_axil_rvalid_next;
always @* begin
// transfer sink ready state to source
s_axil_rvalid_next = s_axil_rvalid_reg;
store_axil_r_input_to_output = 1'b0;
if (m_axil_rready_reg) begin
s_axil_rvalid_next = m_axil_rvalid;
store_axil_r_input_to_output = 1'b1;
end else if (s_axil_rready) begin
s_axil_rvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
m_axil_rready_reg <= 1'b0;
s_axil_rvalid_reg <= 1'b0;
end else begin
m_axil_rready_reg <= m_axil_rready_early;
s_axil_rvalid_reg <= s_axil_rvalid_next;
end
// datapath
if (store_axil_r_input_to_output) begin
s_axil_rdata_reg <= m_axil_rdata;
s_axil_rresp_reg <= m_axil_rresp;
end
end
end else begin
// bypass R channel
assign s_axil_rdata = m_axil_rdata;
assign s_axil_rresp = m_axil_rresp;
assign s_axil_rvalid = m_axil_rvalid;
assign m_axil_rready = s_axil_rready;
end
endgenerate
endmodule
corundum/lib/axi/rtl/axil_register_wr.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4 lite register (write)
*/
module axil_register_wr #
(
// Width of data bus in bits
parameter DATA_WIDTH = 32,
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// AW channel register type
// 0 to bypass, 1 for simple buffer
parameter AW_REG_TYPE = 1,
// W channel register type
// 0 to bypass, 1 for simple buffer
parameter W_REG_TYPE = 1,
// B channel register type
// 0 to bypass, 1 for simple buffer
parameter B_REG_TYPE = 1
)
(
input wire clk,
input wire rst,
/*
* AXI lite slave interface
*/
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
/*
* AXI lite master interface
*/
output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [DATA_WIDTH-1:0] m_axil_wdata,
output wire [STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready
);
generate
// AW channel
if (AW_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
reg s_axil_awready_reg = 1'b0;
reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] m_axil_awprot_reg = 3'd0;
reg m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
reg [ADDR_WIDTH-1:0] temp_m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] temp_m_axil_awprot_reg = 3'd0;
reg temp_m_axil_awvalid_reg = 1'b0, temp_m_axil_awvalid_next;
// datapath control
reg store_axil_aw_input_to_output;
reg store_axil_aw_input_to_temp;
reg store_axil_aw_temp_to_output;
assign s_axil_awready = s_axil_awready_reg;
assign m_axil_awaddr = m_axil_awaddr_reg;
assign m_axil_awprot = m_axil_awprot_reg;
assign m_axil_awvalid = m_axil_awvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axil_awready_early = m_axil_awready | (~temp_m_axil_awvalid_reg & (~m_axil_awvalid_reg | ~s_axil_awvalid));
always @* begin
// transfer sink ready state to source
m_axil_awvalid_next = m_axil_awvalid_reg;
temp_m_axil_awvalid_next = temp_m_axil_awvalid_reg;
store_axil_aw_input_to_output = 1'b0;
store_axil_aw_input_to_temp = 1'b0;
store_axil_aw_temp_to_output = 1'b0;
if (s_axil_awready_reg) begin
// input is ready
if (m_axil_awready | ~m_axil_awvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axil_awvalid_next = s_axil_awvalid;
store_axil_aw_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axil_awvalid_next = s_axil_awvalid;
store_axil_aw_input_to_temp = 1'b1;
end
end else if (m_axil_awready) begin
// input is not ready, but output is ready
m_axil_awvalid_next = temp_m_axil_awvalid_reg;
temp_m_axil_awvalid_next = 1'b0;
store_axil_aw_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_awready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
temp_m_axil_awvalid_reg <= 1'b0;
end else begin
s_axil_awready_reg <= s_axil_awready_early;
m_axil_awvalid_reg <= m_axil_awvalid_next;
temp_m_axil_awvalid_reg <= temp_m_axil_awvalid_next;
end
// datapath
if (store_axil_aw_input_to_output) begin
m_axil_awaddr_reg <= s_axil_awaddr;
m_axil_awprot_reg <= s_axil_awprot;
end else if (store_axil_aw_temp_to_output) begin
m_axil_awaddr_reg <= temp_m_axil_awaddr_reg;
m_axil_awprot_reg <= temp_m_axil_awprot_reg;
end
if (store_axil_aw_input_to_temp) begin
temp_m_axil_awaddr_reg <= s_axil_awaddr;
temp_m_axil_awprot_reg <= s_axil_awprot;
end
end
end else if (AW_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg s_axil_awready_reg = 1'b0;
reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}};
reg [2:0] m_axil_awprot_reg = 3'd0;
reg m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
// datapath control
reg store_axil_aw_input_to_output;
assign s_axil_awready = s_axil_awready_reg;
assign m_axil_awaddr = m_axil_awaddr_reg;
assign m_axil_awprot = m_axil_awprot_reg;
assign m_axil_awvalid = m_axil_awvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axil_awready_eawly = !m_axil_awvalid_next;
always @* begin
// transfer sink ready state to source
m_axil_awvalid_next = m_axil_awvalid_reg;
store_axil_aw_input_to_output = 1'b0;
if (s_axil_awready_reg) begin
m_axil_awvalid_next = s_axil_awvalid;
store_axil_aw_input_to_output = 1'b1;
end else if (m_axil_awready) begin
m_axil_awvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_awready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
end else begin
s_axil_awready_reg <= s_axil_awready_eawly;
m_axil_awvalid_reg <= m_axil_awvalid_next;
end
// datapath
if (store_axil_aw_input_to_output) begin
m_axil_awaddr_reg <= s_axil_awaddr;
m_axil_awprot_reg <= s_axil_awprot;
end
end
end else begin
// bypass AW channel
assign m_axil_awaddr = s_axil_awaddr;
assign m_axil_awprot = s_axil_awprot;
assign m_axil_awvalid = s_axil_awvalid;
assign s_axil_awready = m_axil_awready;
end
// W channel
if (W_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
reg s_axil_wready_reg = 1'b0;
reg [DATA_WIDTH-1:0] m_axil_wdata_reg = {DATA_WIDTH{1'b0}};
reg [STRB_WIDTH-1:0] m_axil_wstrb_reg = {STRB_WIDTH{1'b0}};
reg m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
reg [DATA_WIDTH-1:0] temp_m_axil_wdata_reg = {DATA_WIDTH{1'b0}};
reg [STRB_WIDTH-1:0] temp_m_axil_wstrb_reg = {STRB_WIDTH{1'b0}};
reg temp_m_axil_wvalid_reg = 1'b0, temp_m_axil_wvalid_next;
// datapath control
reg store_axil_w_input_to_output;
reg store_axil_w_input_to_temp;
reg store_axil_w_temp_to_output;
assign s_axil_wready = s_axil_wready_reg;
assign m_axil_wdata = m_axil_wdata_reg;
assign m_axil_wstrb = m_axil_wstrb_reg;
assign m_axil_wvalid = m_axil_wvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axil_wready_early = m_axil_wready | (~temp_m_axil_wvalid_reg & (~m_axil_wvalid_reg | ~s_axil_wvalid));
always @* begin
// transfer sink ready state to source
m_axil_wvalid_next = m_axil_wvalid_reg;
temp_m_axil_wvalid_next = temp_m_axil_wvalid_reg;
store_axil_w_input_to_output = 1'b0;
store_axil_w_input_to_temp = 1'b0;
store_axil_w_temp_to_output = 1'b0;
if (s_axil_wready_reg) begin
// input is ready
if (m_axil_wready | ~m_axil_wvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axil_wvalid_next = s_axil_wvalid;
store_axil_w_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axil_wvalid_next = s_axil_wvalid;
store_axil_w_input_to_temp = 1'b1;
end
end else if (m_axil_wready) begin
// input is not ready, but output is ready
m_axil_wvalid_next = temp_m_axil_wvalid_reg;
temp_m_axil_wvalid_next = 1'b0;
store_axil_w_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_wready_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
temp_m_axil_wvalid_reg <= 1'b0;
end else begin
s_axil_wready_reg <= s_axil_wready_early;
m_axil_wvalid_reg <= m_axil_wvalid_next;
temp_m_axil_wvalid_reg <= temp_m_axil_wvalid_next;
end
// datapath
if (store_axil_w_input_to_output) begin
m_axil_wdata_reg <= s_axil_wdata;
m_axil_wstrb_reg <= s_axil_wstrb;
end else if (store_axil_w_temp_to_output) begin
m_axil_wdata_reg <= temp_m_axil_wdata_reg;
m_axil_wstrb_reg <= temp_m_axil_wstrb_reg;
end
if (store_axil_w_input_to_temp) begin
temp_m_axil_wdata_reg <= s_axil_wdata;
temp_m_axil_wstrb_reg <= s_axil_wstrb;
end
end
end else if (W_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg s_axil_wready_reg = 1'b0;
reg [DATA_WIDTH-1:0] m_axil_wdata_reg = {DATA_WIDTH{1'b0}};
reg [STRB_WIDTH-1:0] m_axil_wstrb_reg = {STRB_WIDTH{1'b0}};
reg m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
// datapath control
reg store_axil_w_input_to_output;
assign s_axil_wready = s_axil_wready_reg;
assign m_axil_wdata = m_axil_wdata_reg;
assign m_axil_wstrb = m_axil_wstrb_reg;
assign m_axil_wvalid = m_axil_wvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axil_wready_ewly = !m_axil_wvalid_next;
always @* begin
// transfer sink ready state to source
m_axil_wvalid_next = m_axil_wvalid_reg;
store_axil_w_input_to_output = 1'b0;
if (s_axil_wready_reg) begin
m_axil_wvalid_next = s_axil_wvalid;
store_axil_w_input_to_output = 1'b1;
end else if (m_axil_wready) begin
m_axil_wvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
s_axil_wready_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
end else begin
s_axil_wready_reg <= s_axil_wready_ewly;
m_axil_wvalid_reg <= m_axil_wvalid_next;
end
// datapath
if (store_axil_w_input_to_output) begin
m_axil_wdata_reg <= s_axil_wdata;
m_axil_wstrb_reg <= s_axil_wstrb;
end
end
end else begin
// bypass W channel
assign m_axil_wdata = s_axil_wdata;
assign m_axil_wstrb = s_axil_wstrb;
assign m_axil_wvalid = s_axil_wvalid;
assign s_axil_wready = m_axil_wready;
end
// B channel
if (B_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
reg m_axil_bready_reg = 1'b0;
reg [1:0] s_axil_bresp_reg = 2'b0;
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
reg [1:0] temp_s_axil_bresp_reg = 2'b0;
reg temp_s_axil_bvalid_reg = 1'b0, temp_s_axil_bvalid_next;
// datapath control
reg store_axil_b_input_to_output;
reg store_axil_b_input_to_temp;
reg store_axil_b_temp_to_output;
assign m_axil_bready = m_axil_bready_reg;
assign s_axil_bresp = s_axil_bresp_reg;
assign s_axil_bvalid = s_axil_bvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire m_axil_bready_early = s_axil_bready | (~temp_s_axil_bvalid_reg & (~s_axil_bvalid_reg | ~m_axil_bvalid));
always @* begin
// transfer sink ready state to source
s_axil_bvalid_next = s_axil_bvalid_reg;
temp_s_axil_bvalid_next = temp_s_axil_bvalid_reg;
store_axil_b_input_to_output = 1'b0;
store_axil_b_input_to_temp = 1'b0;
store_axil_b_temp_to_output = 1'b0;
if (m_axil_bready_reg) begin
// input is ready
if (s_axil_bready | ~s_axil_bvalid_reg) begin
// output is ready or currently not valid, transfer data to output
s_axil_bvalid_next = m_axil_bvalid;
store_axil_b_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_s_axil_bvalid_next = m_axil_bvalid;
store_axil_b_input_to_temp = 1'b1;
end
end else if (s_axil_bready) begin
// input is not ready, but output is ready
s_axil_bvalid_next = temp_s_axil_bvalid_reg;
temp_s_axil_bvalid_next = 1'b0;
store_axil_b_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axil_bready_reg <= 1'b0;
s_axil_bvalid_reg <= 1'b0;
temp_s_axil_bvalid_reg <= 1'b0;
end else begin
m_axil_bready_reg <= m_axil_bready_early;
s_axil_bvalid_reg <= s_axil_bvalid_next;
temp_s_axil_bvalid_reg <= temp_s_axil_bvalid_next;
end
// datapath
if (store_axil_b_input_to_output) begin
s_axil_bresp_reg <= m_axil_bresp;
end else if (store_axil_b_temp_to_output) begin
s_axil_bresp_reg <= temp_s_axil_bresp_reg;
end
if (store_axil_b_input_to_temp) begin
temp_s_axil_bresp_reg <= m_axil_bresp;
end
end
end else if (B_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
reg m_axil_bready_reg = 1'b0;
reg [1:0] s_axil_bresp_reg = 2'b0;
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
// datapath control
reg store_axil_b_input_to_output;
assign m_axil_bready = m_axil_bready_reg;
assign s_axil_bresp = s_axil_bresp_reg;
assign s_axil_bvalid = s_axil_bvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire m_axil_bready_early = !s_axil_bvalid_next;
always @* begin
// transfer sink ready state to source
s_axil_bvalid_next = s_axil_bvalid_reg;
store_axil_b_input_to_output = 1'b0;
if (m_axil_bready_reg) begin
s_axil_bvalid_next = m_axil_bvalid;
store_axil_b_input_to_output = 1'b1;
end else if (s_axil_bready) begin
s_axil_bvalid_next = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
m_axil_bready_reg <= 1'b0;
s_axil_bvalid_reg <= 1'b0;
end else begin
m_axil_bready_reg <= m_axil_bready_early;
s_axil_bvalid_reg <= s_axil_bvalid_next;
end
// datapath
if (store_axil_b_input_to_output) begin
s_axil_bresp_reg <= m_axil_bresp;
end
end
end else begin
// bypass B channel
assign s_axil_bresp = m_axil_bresp;
assign s_axil_bvalid = m_axil_bvalid;
assign m_axil_bready = s_axil_bready;
end
endgenerate
endmodule
corundum/lib/axi/rtl/priority_encoder.v 0 → 100644
View file @ 738c1fef
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Priority encoder module
*/
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
// power-of-two width
parameter W1 = 2**$clog2(WIDTH);
parameter W2 = W1/2;
generate
if (WIDTH == 1) begin
// one input
assign output_valid = input_unencoded;
assign output_encoded = 0;
end else if (WIDTH == 2) begin
// two inputs - just an OR gate
assign output_valid = |input_unencoded;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = input_unencoded[1];
end else begin
assign output_encoded = ~input_unencoded[0];
end
end else begin
// more than two inputs - split into two parts and recurse
// also pad input to correct power-of-two width
wire [$clog2(W2)-1:0] out1, out2;
wire valid1, valid2;
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst1 (
.input_unencoded(input_unencoded[W2-1:0]),
.output_valid(valid1),
.output_encoded(out1)
);
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst2 (
.input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
.output_valid(valid2),
.output_encoded(out2)
);
// multiplexer to select part
assign output_valid = valid1 | valid2;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
end else begin
assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
end
end
endgenerate
// unencoded output
assign output_unencoded = 1 << output_encoded;
endmodule
corundum/lib/axi/syn/axil_cdc.tcl 0 → 100644
View file @ 738c1fef
# Copyright (c) 2019 Alex Forencich
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.
# AXI lite clock domain crossing module timing constraints
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == axil_cdc_rd || REF_NAME == axil_cdc_rd || ORIG_REF_NAME == axil_cdc_wr || REF_NAME == axil_cdc_wr)}] {
puts "Inserting timing constraints for axil_cdc instance $inst"
# get clock periods
set m_clk [get_clocks -of_objects [get_pins $inst/m_flag_reg_reg/C]]
set s_clk [get_clocks -of_objects [get_pins $inst/s_flag_reg_reg/C]]
set m_clk_period [get_property -min PERIOD $m_clk]
set s_clk_period [get_property -min PERIOD $s_clk]
set min_clk_period [expr $m_clk_period < $s_clk_period ? $m_clk_period : $s_clk_period]
set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/m_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]
set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/s_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells $inst/m_flag_reg_reg] -to [get_cells $inst/m_flag_sync_reg_1_reg] -datapath_only $s_clk_period
set_max_delay -from [get_cells $inst/s_flag_reg_reg] -to [get_cells $inst/s_flag_sync_reg_1_reg] -datapath_only $m_clk_period
set source [get_cells -quiet -hier -regexp ".*/s_axil_a?(r|w)(addr|prot|data|strb)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
set dest [get_cells -quiet -hier -regexp ".*/m_axil_a?(r|w)(addr|prot|data|strb)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
if {[llength $dest]} {
if {![llength $source]} {
# source cells seem to have been merged with something, so go hunt them down
set dest_pins [get_pins -of_objects $dest -filter {REF_PIN_NAME == "D"}]
set nets [get_nets -segments -of_objects $dest_pins]
set source_pins [get_pins -of_objects $nets -filter {IS_LEAF && DIRECTION == "OUT"}]
set source [get_cells -of_objects $source_pins]
}
if {[llength $source]} {
set_max_delay -from $source -to $dest -datapath_only $m_clk_period
set_bus_skew -from $source -to $dest $s_clk_period
}
}
set source [get_cells -quiet -hier -regexp ".*/m_axil_(r|b)(resp|data)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
set dest [get_cells -quiet -hier -regexp ".*/s_axil_(r|b)(resp|data)_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
if {[llength $dest]} {
if {![llength $source]} {
# source cells seem to have been merged with something, so go hunt them down
set dest_pins [get_pins -of_objects $dest -filter {REF_PIN_NAME == "D"}]
set nets [get_nets -segments -of_objects $dest_pins]
set source_pins [get_pins -of_objects $nets -filter {IS_LEAF && DIRECTION == "OUT"}]
set source [get_cells -of_objects $source_pins]
}
if {[llength $source]} {
set_max_delay -from $source -to $dest -datapath_only $s_clk_period
set_bus_skew -from $source -to $dest $m_clk_period
}
}
}
corundum/lib/axis 0 → 120000
View file @ 738c1fef
eth/lib/axis/
\ No newline at end of file
corundum/lib/eth/.gitignore 0 → 100644
View file @ 738c1fef
*~
*.lxt
*.pyc
*.vvp
*.kate-swp
corundum/lib/eth/.travis.yml 0 → 100644
View file @ 738c1fef
language: python
python:
- "3.6"
before_install:
- export d=`pwd`
- export PYTHON_EXE=`which python`
- sudo apt-get update -qq
- sudo apt-get install -y iverilog
- git clone https://github.com/jandecaluwe/myhdl.git
- cd $d/myhdl && sudo $PYTHON_EXE setup.py install
- cd $d/myhdl/cosimulation/icarus && make && sudo install -m 0755 -D ./myhdl.vpi /usr/lib/x86_64-linux-gnu/ivl/myhdl.vpi
- cd $d
script:
- cd tb && py.test
corundum/lib/eth/AUTHORS 0 → 100644
View file @ 738c1fef
Alex Forencich <alex@alexforencich.com>
corundum/lib/eth/COPYING 0 → 100644
View file @ 738c1fef
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
corundum/lib/eth/README 0 → 120000
View file @ 738c1fef
README.md
\ No newline at end of file
corundum/lib/eth/README.md 0 → 100644
View file @ 738c1fef
# Verilog Ethernet Components Readme
For more information and updates: http://alexforencich.com/wiki/en/verilog/ethernet/start
GitHub repository: https://github.com/alexforencich/verilog-ethernet
## Introduction
Collection of Ethernet-related components for gigabit, 10G, and 25G packet
processing (8 bit and 64 bit datapaths). Includes modules for handling
Ethernet frames as well as IP, UDP, and ARP and the components for
constructing a complete UDP/IP stack. Includes MAC modules for gigabit and
10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA
module. Includes various PTP related components for implementing systems that
require precise time synchronization. Also includes full MyHDL testbench with
intelligent bus cosimulation endpoints.
For IP and ARP support only, use ip_complete (1G) or ip_complete_64 (10G/25G).
For UDP, IP, and ARP support, use udp_complete (1G) or udp_complete_64
(10G/25G).
Top level gigabit and 10G/25G MAC modules are eth_mac_*, with various
interfaces and with/without FIFOs. Top level 10G/25G PCS/PMA PHY module is
eth_phy_10g. Top level 10G/25G MAC/PCS/PMA combination module is
eth_mac_phy_10g.
PTP components include a configurable PTP clock (ptp_clock), a PTP clock CDC
module (ptp_clock_cdc) for transferring PTP time across clock domains, and a
configurable PTP period output module for precisely generating arbitrary
frequencies from PTP time.
## Documentation
### arp module
ARP handling logic with parametrizable retry timeout parameters and
parametrizable datapath.
### arp_cache module
Basic hash-based cache for ARP entries. Parametrizable depth.
### arp_eth_rx module
ARP frame receiver with parametrizable datapath.
### arp_eth_tx module
ARP frame transmitter with parametrizable datapath.
### axis_eth_fcs module
Ethernet frame check sequence calculator.
### axis_eth_fcs_64 module
Ethernet frame check sequence calculator with 64 bit datapath for 10G/25G
Ethernet.
### axis_eth_fcs_check module
Ethernet frame check sequence checker.
### axis_eth_fcs_insert module
Ethernet frame check sequence inserter.
### axis_gmii_rx module
AXI stream GMII/MII frame receiver with clock enable and MII select.
### axis_gmii_tx module
AXI stream GMII/MII frame transmitter with clock enable and MII select.
### axis_xgmii_rx_32 module
AXI stream XGMII frame receiver with 32 bit datapath.
### axis_xgmii_rx_64 module
AXI stream XGMII frame receiver with 64 bit datapath.
### axis_xgmii_tx_32 module
AXI stream XGMII frame transmitter with 32 bit datapath.
### axis_xgmii_tx_64 module
AXI stream XGMII frame transmitter with 64 bit datapath.
### eth_arb_mux module
Ethernet frame arbitrated muliplexer with parametrizable data width and port
count. Supports priority and round-robin arbitration.
### eth_axis_rx module
Ethernet frame receiver with parametrizable datapath.
### eth_axis_tx module
Ethernet frame transmitter with parametrizable datapath.
### eth_demux module
Ethernet frame demuliplexer with parametrizable data width and port count.
Supports priority and round-robin arbitration.
### eth_mac_1g module
Gigabit Ethernet MAC with GMII interface.
### eth_mac_1g_fifo module
Gigabit Ethernet MAC with GMII interface and FIFOs.
### eth_mac_1g_gmii module
Tri-mode Ethernet MAC with GMII/MII interface and automatic PHY rate
adaptation logic.
### eth_mac_1g_gmii_fifo module
Tri-mode Ethernet MAC with GMII/MII interface, FIFOs, and automatic PHY rate
adaptation logic.
### eth_mac_1g_rgmii module
Tri-mode Ethernet MAC with RGMII interface and automatic PHY rate adaptation
logic.
### eth_mac_1g_rgmii_fifo module
Tri-mode Ethernet MAC with RGMII interface, FIFOs, and automatic PHY rate
adaptation logic.
### eth_mac_10g module
10G/25G Ethernet MAC with XGMII interface. Datapath selectable between 32 and
64 bits.
### eth_mac_10g_fifo module
10G/25G Ethernet MAC with XGMII interface and FIFOs. Datapath selectable
between 32 and 64 bits.
### eth_mac_mii module
Ethernet MAC with MII interface.
### eth_mac_mii_fifo module
Ethernet MAC with MII interface and FIFOs.
### eth_mac_phy_10g module
10G/25G Ethernet MAC/PHY combination module with SERDES interface.
### eth_mac_phy_10g_fifo module
10G/25G Ethernet MAC/PHY combination module with SERDES interface and FIFOs.
### eth_mac_phy_10g_rx module
10G/25G Ethernet MAC/PHY combination module with SERDES interface, RX path.
### eth_mac_phy_10g_tx module
10G/25G Ethernet MAC/PHY combination module with SERDES interface, TX path.
### eth_mux module
Ethernet frame muliplexer with parametrizable data width and port count.
Supports priority and round-robin arbitration.
### eth_phy_10g module
10G/25G Ethernet PCS/PMA PHY.
### eth_phy_10g_rx module
10G/25G Ethernet PCS/PMA PHY receive-side logic.
### eth_phy_10g_rx_ber_mon module
10G/25G Ethernet PCS/PMA PHY BER monitor.
### eth_phy_10g_rx_frame_sync module
10G/25G Ethernet PCS/PMA PHY frame synchronizer.
### eth_phy_10g_tx module
10G/25G Ethernet PCS/PMA PHY transmit-side logic.
### gmii_phy_if module
GMII/MII PHY interface and clocking logic.
### ip module
IPv4 block with 8 bit data width for gigabit Ethernet. Manages IPv4 packet
transmssion and reception. Interfaces with ARP module for MAC address lookup.
### ip_64 module
IPv4 block with 64 bit data width for 10G/25G Ethernet. Manages IPv4 packet
transmssion and reception. Interfaces with ARP module for MAC address lookup.
### ip_arb_mux module
IP frame arbitrated muliplexer with parametrizable data width and port count.
Supports priority and round-robin arbitration.
### ip_complete module
IPv4 module with ARP integration.
Top level for gigabit IP stack.
### ip_complete_64 module
IPv4 module with ARP integration and 64 bit data width for 10G/25G Ethernet.
Top level for 10G/25G IP stack.
### ip_demux module
IP frame demuliplexer with parametrizable data width and port count.
Supports priority and round-robin arbitration.
### ip_eth_rx module
IP frame receiver.
### ip_eth_rx_64 module
IP frame receiver with 64 bit datapath for 10G/25G Ethernet.
### ip_eth_tx module
IP frame transmitter.
### ip_eth_tx_64 module
IP frame transmitter with 64 bit datapath for 10G/25G Ethernet.
### ip_mux module
IP frame muliplexer with parametrizable data width and port count.
Supports priority and round-robin arbitration.
### lfsr module
Fully parametrizable combinatorial parallel LFSR/CRC module.
### mii_phy_if module
MII PHY interface and clocking logic.
### ptp_clock module
PTP clock module with PPS output. Generates both 64 bit and 96 bit timestamp
formats. Fine frequeny adjustment supported with configurable fractional
nanoseconds field.
### ptp_clock_cdc module
PTP clock CDC module with PPS output. Use this module to transfer and deskew a
free-running PTP clock across clock domains. Supports both 64 and 96 bit
timestamp formats.
### ptp_ts_extract module
PTP timestamp extract module. Use this module to extract a PTP timestamp
embedded in the tuser sideband signal of an AXI stream interface.
### ptp_perout module
PTP period output module. Generates a pulse output, configurable in absolute
start time, period, and width, based on PTP time from a PTP clock.
### rgmii_phy_if module
RGMII PHY interface and clocking logic.
### udp module
UDP block with 8 bit data width for gigabit Ethernet. Manages UDP packet
transmssion and reception.
### udp_64 module
UDP block with 64 bit data width for 10G/25G Ethernet. Manages UDP packet
transmssion and reception.
### udp_arb_mux module
UDP frame arbitrated muliplexer with parametrizable data width and port
count. Supports priority and round-robin arbitration.
### udp_checksum_gen module
UDP checksum generator module. Calculates UDP length, IP length, and
UDP checksum fields.
### udp_checksum_gen_64 module
UDP checksum generator module with 64 bit datapath. Calculates UDP
length, IP length, and UDP checksum fields.
### udp_complete module
UDP module with IPv4 and ARP integration.
Top level for gigabit UDP stack.
### udp_complete_64 module
UDP module with IPv4 and ARP integration and 64 bit data width for 10G
Ethernet.
Top level for 10G/25G UDP stack.
### udp_demux module
UDP frame demuliplexer with parametrizable data width and port count.
Supports priority and round-robin arbitration.
### udp_ip_rx module
UDP frame receiver.
### udp_ip_rx_64 module
UDP frame receiver with 64 bit datapath for 10G/25G Ethernet.
### udp_ip_tx module
UDP frame transmitter.
### udp_ip_tx_64 module
UDP frame transmitter with 64 bit datapath for 10G/25G Ethernet.
### udp_mux module
UDP frame muliplexer with parametrizable data width and port count.
Supports priority and round-robin arbitration.
### xgmii_baser_dec_64 module
XGMII 10GBASE-R decoder for 10G PCS/PMA PHY.
### xgmii_baser_enc_64 module
XGMII 10GBASE-R encoder for 10G PCS/PMA PHY.
### xgmii_deinterleave module
XGMII de-interleaver for interfacing with PHY cores that interleave the
control and data lines.
### xgmii_interleave module
XGMII interleaver for interfacing with PHY cores that interleave the control
and data lines.
### Common signals
tdata : Data (width generally DATA_WIDTH)
tkeep : Data word valid (width generally KEEP_WIDTH, present on _64 modules)
tvalid : Data valid
tready : Sink ready
tlast : End-of-frame
tuser : Bad frame (valid with tlast & tvalid)
### Source Files
rtl/arp.v : ARP handling logic
rtl/arp_cache.v : ARP LRU cache
rtl/arp_eth_rx.v : ARP frame receiver
rtl/arp_eth_tx.v : ARP frame transmitter
rtl/eth_arb_mux.py : Ethernet frame arbitrated multiplexer generator
rtl/axis_eth_fcs.v : Ethernet FCS calculator
rtl/axis_eth_fcs_64.v : Ethernet FCS calculator (64 bit)
rtl/axis_eth_fcs_insert.v : Ethernet FCS inserter
rtl/axis_eth_fcs_check.v : Ethernet FCS checker
rtl/axis_gmii_rx.v : AXI stream GMII/MII receiver
rtl/axis_gmii_tx.v : AXI stream GMII/MII transmitter
rtl/axis_xgmii_rx_32.v : AXI stream XGMII receiver (32 bit)
rtl/axis_xgmii_rx_64.v : AXI stream XGMII receiver (64 bit)
rtl/axis_xgmii_tx_32.v : AXI stream XGMII transmitter (32 bit)
rtl/axis_xgmii_tx_64.v : AXI stream XGMII transmitter (64 bit)
rtl/eth_arb_mux.v : Ethernet frame arbitrated multiplexer
rtl/eth_axis_rx.v : Ethernet frame receiver
rtl/eth_axis_tx.v : Ethernet frame transmitter
rtl/eth_demux.v : Ethernet frame demultiplexer
rtl/eth_mac_1g.v : Gigabit Ethernet GMII MAC
rtl/eth_mac_1g_fifo.v : Gigabit Ethernet GMII MAC with FIFO
rtl/eth_mac_1g_gmii.v : Tri-mode Ethernet GMII/MII MAC
rtl/eth_mac_1g_gmii_fifo.v : Tri-mode Ethernet GMII/MII MAC with FIFO
rtl/eth_mac_1g_rgmii.v : Tri-mode Ethernet RGMII MAC
rtl/eth_mac_1g_rgmii_fifo.v : Tri-mode Ethernet RGMII MAC with FIFO
rtl/eth_mac_10g.v : 10G/25G Ethernet XGMII MAC
rtl/eth_mac_10g_fifo.v : 10G/25G Ethernet XGMII MAC with FIFO
rtl/eth_mac_mii.v : Ethernet MII MAC
rtl/eth_mac_mii_fifo.v : Ethernet MII MAC with FIFO
rtl/eth_mac_phy_10g.v : 10G/25G Ethernet XGMII MAC/PHY
rtl/eth_mac_phy_10g_fifo.v : 10G/25G Ethernet XGMII MAC/PHY with FIFO
rtl/eth_mac_phy_10g_rx.v : 10G/25G Ethernet XGMII MAC/PHY RX with FIFO
rtl/eth_mac_phy_10g_tx.v : 10G/25G Ethernet XGMII MAC/PHY TX with FIFO
rtl/eth_mux.v : Ethernet frame multiplexer
rtl/gmii_phy_if.v : GMII PHY interface
rtl/iddr.v : Generic DDR input register
rtl/ip.v : IPv4 block
rtl/ip_64.v : IPv4 block (64 bit)
rtl/ip_arb_mux.v : IP frame arbitrated multiplexer
rtl/ip_complete.v : IPv4 stack (IP-ARP integration)
rtl/ip_complete_64.v : IPv4 stack (IP-ARP integration) (64 bit)
rtl/ip_demux.v : IP frame demultiplexer
rtl/ip_eth_rx.v : IPv4 frame receiver
rtl/ip_eth_rx_64.v : IPv4 frame receiver (64 bit)
rtl/ip_eth_tx.v : IPv4 frame transmitter
rtl/ip_eth_tx_64.v : IPv4 frame transmitter (64 bit)
rtl/ip_mux.v : IP frame multiplexer
rtl/lfsr.v : Generic LFSR/CRC module
rtl/mii_phy_if.v : MII PHY interface
rtl/oddr.v : Generic DDR output register
rtl/ptp_clock.v : PTP clock
rtl/ptp_clock_cdc.v : PTP clock CDC
rtl/ptp_ts_extract.v : PTP timestamp extract
rtl/ptp_perout.v : PTP period out
rtl/rgmii_phy_if.v : RGMII PHY interface
rtl/ssio_ddr_in.v : Generic source synchronous IO DDR input module
rtl/ssio_ddr_in_diff.v : Generic source synchronous IO DDR differential input module
rtl/ssio_ddr_out.v : Generic source synchronous IO DDR output module
rtl/ssio_ddr_out_diff.v : Generic source synchronous IO DDR differential output module
rtl/ssio_sdr_in.v : Generic source synchronous IO SDR input module
rtl/ssio_sdr_in_diff.v : Generic source synchronous IO SDR differential input module
rtl/ssio_sdr_out.v : Generic source synchronous IO SDR output module
rtl/ssio_sdr_out_diff.v : Generic source synchronous IO SDR differential output module
rtl/udp.v : UDP block
rtl/udp_64.v : UDP block (64 bit)
rtl/udp_arb_mux.v : UDP frame arbitrated multiplexer
rtl/udp_checksum_gen.v : UDP checksum generator
rtl/udp_checksum_gen_64.v : UDP checksum generator (64 bit)
rtl/udp_complete.v : UDP stack (IP-ARP-UDP)
rtl/udp_complete_64.v : UDP stack (IP-ARP-UDP) (64 bit)
rtl/udp_demux.v : UDP frame demultiplexer
rtl/udp_ip_rx.v : UDP frame receiver
rtl/udp_ip_rx_64.v : UDP frame receiver (64 bit)
rtl/udp_ip_tx.v : UDP frame transmitter
rtl/udp_ip_tx_64.v : UDP frame transmitter (64 bit)
rtl/udp_mux.v : UDP frame multiplexer
rtl/xgmii_baser_dec_64.v : XGMII 10GBASE-R decoder
rtl/xgmii_baser_enc_64.v : XGMII 10GBASE-R encoder
rtl/xgmii_deinterleave.v : XGMII data/control de-interleaver
rtl/xgmii_interleave.v : XGMII data/control interleaver
### AXI Stream Interface Example
transfer with header data
__ __ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__
______________ ___________
hdr_ready \_________________/
_____
hdr_valid ________/ \_____________________________
_____
hdr_data XXXXXXXXX_HDR_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
___________ _____ _____
tdata XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX
___________ _____ _____
tkeep XXXXXXXXX_K0________X_K1__X_K2__XXXXXXXXXXXX
_______________________
tvalid ________/ \___________
_________________
tready ______________/ \___________
_____
tlast __________________________/ \___________
tuser ____________________________________________
two byte transfer with sink pause after each byte
__ __ __ __ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
_____ _________________
tdata XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX
_____ _________________
tkeep XXXXXXXXX_K0__X_K1______________XXXXXXXXXXXXXXXXXXXXXXXX
_______________________
tvalid ________/ \_______________________
______________ _____ ___________
tready \___________/ \___________/
_________________
tlast ______________/ \_______________________
tuser ________________________________________________________
two back-to-back packets, no pauses
__ __ __ __ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
_____ _____ _____ _____ _____ _____
tdata XXXXXXXXX_A0__X_A1__X_A2__X_B0__X_B1__X_B2__XXXXXXXXXXXX
_____ _____ _____ _____ _____ _____
tkeep XXXXXXXXX_K0__X_K1__X_K2__X_K0__X_K1__X_K2__XXXXXXXXXXXX
___________________________________
tvalid ________/ \___________
________________________________________________________
tready
_____ _____
tlast ____________________/ \___________/ \___________
tuser ________________________________________________________
bad frame
__ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__
_____ _____ _____
tdata XXXXXXXXX_A0__X_A1__X_A2__XXXXXXXXXXXX
_____ _____ _____
tkeep XXXXXXXXX_K0__X_K1__X_K2__XXXXXXXXXXXX
_________________
tvalid ________/ \___________
______________________________________
tready
_____
tlast ____________________/ \___________
_____
tuser ____________________/ \___________
## Testing
Running the included testbenches requires MyHDL and Icarus Verilog. Make sure
that myhdl.vpi is installed properly for cosimulation to work correctly. The
testbenches can be run with a Python test runner like nose or py.test, or the
individual test scripts can be run with python directly.
### Testbench Files
tb/arp_ep.py : MyHDL ARP frame endpoints
tb/axis_ep.py : MyHDL AXI Stream endpoints
tb/baser_serdes.py : MyHDL 10GBASE-R SERDES endpoints
tb/eth_ep.py : MyHDL Ethernet frame endpoints
tb/gmii_ep.py : MyHDL GMII endpoints
tb/ip_ep.py : MyHDL IP frame endpoints
tb/mii_ep.py : MyHDL MII endpoints
tb/ptp.py : MyHDL PTP clock model
tb/rgmii_ep.py : MyHDL RGMII endpoints
tb/udp_ep.py : MyHDL UDP frame endpoints
tb/xgmii_ep.py : MyHDL XGMII endpoints
corundum/lib/eth/lib/axis/.gitignore 0 → 100644
View file @ 738c1fef
*~
*.lxt
*.pyc
*.vvp
*.kate-swp
corundum/lib/eth/lib/axis/.travis.yml 0 → 100644
View file @ 738c1fef
language: python
python:
- "3.6"
before_install:
- export d=`pwd`
- export PYTHON_EXE=`which python`
- sudo apt-get update -qq
- sudo apt-get install -y iverilog
- git clone https://github.com/jandecaluwe/myhdl.git
- cd $d/myhdl && sudo $PYTHON_EXE setup.py install
- cd $d/myhdl/cosimulation/icarus && make && sudo install -m 0755 -D ./myhdl.vpi /usr/lib/x86_64-linux-gnu/ivl/myhdl.vpi
- cd $d
script:
- cd tb && IVERILOG_DUMPER=none py.test
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