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Commit 69f0e0d1 authored by Antoine Kaufmann's avatar Antoine Kaufmann
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lib/proto/pcie: rename definitions cosim->simbricks 

Also fix identifier case
parent 86f8a9bb
Show whitespace changes
Inline Side-by-side
Showing with 253 additions and 238 deletions
lib/simbricks/nicbm/nicbm.cc
View file @ 69f0e0d1
......@@ -53,8 +53,8 @@ static void sigusr1_handler(int dummy) {
fprintf(stderr, "main_time = %lu\n", main_time);
}
volatile union cosim_pcie_proto_d2h *Runner::d2h_alloc(void) {
volatile union cosim_pcie_proto_d2h *msg;
volatile union SimbricksProtoPcieD2H *Runner::d2h_alloc(void) {
volatile union SimbricksProtoPcieD2H *msg;
while ((msg = nicsim_d2h_alloc(&nsparams, main_time)) == NULL) {
fprintf(stderr, "d2h_alloc: no entry available\n");
}
......@@ -97,7 +97,7 @@ void Runner::dma_trigger() {
}
void Runner::dma_do(DMAOp &op) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
dma_pending++;
#ifdef DEBUG_NICBM
printf("nicbm: executing dma op %p addr %lx len %zu pending %zu\n", &op,
......@@ -105,7 +105,7 @@ void Runner::dma_do(DMAOp &op) {
#endif
if (op.write) {
volatile struct cosim_pcie_proto_d2h_write *write = &msg->write;
volatile struct SimbricksProtoPcieD2HWrite *write = &msg->write;
if (dintro.d2h_elen < sizeof(*write) + op.len) {
fprintf(stderr,
"issue_dma: write too big (%zu), can only fit up "
......@@ -120,16 +120,16 @@ void Runner::dma_do(DMAOp &op) {
memcpy((void *)write->data, (void *)op.data, op.len);
// WMB();
write->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITE | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITE | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
} else {
volatile struct cosim_pcie_proto_d2h_read *read = &msg->read;
volatile struct SimbricksProtoPcieD2HRead *read = &msg->read;
if (dintro.h2d_elen <
sizeof(struct cosim_pcie_proto_h2d_readcomp) + op.len) {
sizeof(struct SimbricksProtoPcieH2DReadcomp) + op.len) {
fprintf(stderr,
"issue_dma: write too big (%zu), can only fit up "
"to (%zu)\n",
op.len,
dintro.h2d_elen - sizeof(struct cosim_pcie_proto_h2d_readcomp));
dintro.h2d_elen - sizeof(struct SimbricksProtoPcieH2DReadcomp));
abort();
}
......@@ -138,36 +138,38 @@ void Runner::dma_do(DMAOp &op) {
read->len = op.len;
// WMB();
read->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READ | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_READ | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
}
void Runner::msi_issue(uint8_t vec) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
#ifdef DEBUG_NICBM
printf("nicbm: issue MSI interrupt vec %u\n", vec);
#endif
volatile struct cosim_pcie_proto_d2h_interrupt *intr = &msg->interrupt;
volatile struct SimbricksProtoPcieD2HInterrupt *intr = &msg->interrupt;
intr->vector = vec;
intr->inttype = COSIM_PCIE_PROTO_INT_MSI;
intr->inttype = SIMBRICKS_PROTO_PCIE_INT_MSI;
// WMB();
intr->own_type =
COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_INTERRUPT |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::msix_issue(uint8_t vec) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
#ifdef DEBUG_NICBM
printf("nicbm: issue MSI-X interrupt vec %u\n", vec);
#endif
volatile struct cosim_pcie_proto_d2h_interrupt *intr = &msg->interrupt;
volatile struct SimbricksProtoPcieD2HInterrupt *intr = &msg->interrupt;
intr->vector = vec;
intr->inttype = COSIM_PCIE_PROTO_INT_MSIX;
intr->inttype = SIMBRICKS_PROTO_PCIE_INT_MSIX;
// WMB();
intr->own_type =
COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_INTERRUPT |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::event_schedule(TimedEvent &evt) {
......@@ -178,9 +180,9 @@ void Runner::event_cancel(TimedEvent &evt) {
events.erase(&evt);
}
void Runner::h2d_read(volatile struct cosim_pcie_proto_h2d_read *read) {
volatile union cosim_pcie_proto_d2h *msg;
volatile struct cosim_pcie_proto_d2h_readcomp *rc;
void Runner::h2d_read(volatile struct SimbricksProtoPcieH2DRead *read) {
volatile union SimbricksProtoPcieD2H *msg;
volatile struct SimbricksProtoPcieD2HReadcomp *rc;
msg = d2h_alloc();
rc = &msg->readcomp;
......@@ -197,12 +199,12 @@ void Runner::h2d_read(volatile struct cosim_pcie_proto_h2d_read *read) {
// WMB();
rc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READCOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_READCOMP | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::h2d_write(volatile struct cosim_pcie_proto_h2d_write *write) {
volatile union cosim_pcie_proto_d2h *msg;
volatile struct cosim_pcie_proto_d2h_writecomp *wc;
void Runner::h2d_write(volatile struct SimbricksProtoPcieH2DWrite *write) {
volatile union SimbricksProtoPcieD2H *msg;
volatile struct SimbricksProtoPcieD2HWritecomp *wc;
msg = d2h_alloc();
wc = &msg->writecomp;
......@@ -218,10 +220,11 @@ void Runner::h2d_write(volatile struct cosim_pcie_proto_h2d_write *write) {
// WMB();
wc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITECOMP |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
void Runner::h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc) {
void Runner::h2d_readcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc) {
DMAOp *op = (DMAOp *)(uintptr_t)rc->req_id;
#ifdef DEBUG_NICBM
......@@ -236,7 +239,7 @@ void Runner::h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc) {
dma_trigger();
}
void Runner::h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc) {
void Runner::h2d_writecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc) {
DMAOp *op = (DMAOp *)(uintptr_t)wc->req_id;
#ifdef DEBUG_NICBM
......@@ -250,8 +253,8 @@ void Runner::h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc) {
dma_trigger();
}
void Runner::h2d_devctrl(volatile struct cosim_pcie_proto_h2d_devctrl *dc) {
dev.devctrl_update(*(struct cosim_pcie_proto_h2d_devctrl *)dc);
void Runner::h2d_devctrl(volatile struct SimbricksProtoPcieH2DDevctrl *dc) {
dev.devctrl_update(*(struct SimbricksProtoPcieH2DDevctrl *)dc);
}
void Runner::eth_recv(volatile struct cosim_eth_proto_n2d_recv *recv) {
......@@ -276,36 +279,36 @@ void Runner::eth_send(const void *data, size_t len) {
}
void Runner::poll_h2d() {
volatile union cosim_pcie_proto_h2d *msg =
volatile union SimbricksProtoPcieH2D *msg =
nicif_h2d_poll(&nsparams, main_time);
uint8_t type;
if (msg == NULL)
return;
type = msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_MSG_MASK;
type = msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_H2D_MSG_MASK;
switch (type) {
case COSIM_PCIE_PROTO_H2D_MSG_READ:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_READ:
h2d_read(&msg->read);
break;
case COSIM_PCIE_PROTO_H2D_MSG_WRITE:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITE:
h2d_write(&msg->write);
break;
case COSIM_PCIE_PROTO_H2D_MSG_READCOMP:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_READCOMP:
h2d_readcomp(&msg->readcomp);
break;
case COSIM_PCIE_PROTO_H2D_MSG_WRITECOMP:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITECOMP:
h2d_writecomp(&msg->writecomp);
break;
case COSIM_PCIE_PROTO_H2D_MSG_DEVCTRL:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_DEVCTRL:
h2d_devctrl(&msg->devctrl);
break;
case COSIM_PCIE_PROTO_H2D_MSG_SYNC:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_SYNC:
break;
default:
......@@ -470,10 +473,10 @@ void Runner::Device::timed_event(TimedEvent &te) {
}
void Runner::Device::devctrl_update(
struct cosim_pcie_proto_h2d_devctrl &devctrl) {
int_intx_en = devctrl.flags & COSIM_PCIE_PROTO_CTRL_INTX_EN;
int_msi_en = devctrl.flags & COSIM_PCIE_PROTO_CTRL_MSI_EN;
int_msix_en = devctrl.flags & COSIM_PCIE_PROTO_CTRL_MSIX_EN;
struct SimbricksProtoPcieH2DDevctrl &devctrl) {
int_intx_en = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_INTX_EN;
int_msi_en = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_MSI_EN;
int_msix_en = devctrl.flags & SIMBRICKS_PROTO_PCIE_CTRL_MSIX_EN;
}
} // namespace nicbm
lib/simbricks/nicbm/nicbm.h
View file @ 69f0e0d1
......@@ -74,7 +74,7 @@ class Runner {
* Initialize device specific parameters (pci dev/vendor id,
* BARs etc. in intro struct.
*/
virtual void setup_intro(struct cosim_pcie_proto_dev_intro &di) = 0;
virtual void setup_intro(struct SimbricksProtoPcieDevIntro &di) = 0;
/**
* execute a register read from `bar`:`addr` of length `len`.
......@@ -109,7 +109,7 @@ class Runner {
/**
* Device control update
*/
virtual void devctrl_update(struct cosim_pcie_proto_h2d_devctrl &devctrl);
virtual void devctrl_update(struct SimbricksProtoPcieH2DDevctrl &devctrl);
};
protected:
......@@ -125,16 +125,16 @@ class Runner {
size_t dma_pending;
uint64_t mac_addr;
struct nicsim_params nsparams;
struct cosim_pcie_proto_dev_intro dintro;
struct SimbricksProtoPcieDevIntro dintro;
volatile union cosim_pcie_proto_d2h *d2h_alloc(void);
volatile union SimbricksProtoPcieD2H *d2h_alloc(void);
volatile union cosim_eth_proto_d2n *d2n_alloc(void);
void h2d_read(volatile struct cosim_pcie_proto_h2d_read *read);
void h2d_write(volatile struct cosim_pcie_proto_h2d_write *write);
void h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc);
void h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc);
void h2d_devctrl(volatile struct cosim_pcie_proto_h2d_devctrl *dc);
void h2d_read(volatile struct SimbricksProtoPcieH2DRead *read);
void h2d_write(volatile struct SimbricksProtoPcieH2DWrite *write);
void h2d_readcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc);
void h2d_writecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc);
void h2d_devctrl(volatile struct SimbricksProtoPcieH2DDevctrl *dc);
void poll_h2d();
void eth_recv(volatile struct cosim_eth_proto_n2d_recv *recv);
......
lib/simbricks/nicif/nicsim.c
View file @ 69f0e0d1
......@@ -72,7 +72,7 @@ static int shm_fd = -1;
static int pci_cfd = -1;
static int eth_cfd = -1;
static int accept_pci(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
static int accept_pci(struct SimbricksProtoPcieDevIntro *di, int pci_lfd,
int *sync_pci) {
if ((pci_cfd = accept(pci_lfd, NULL, NULL)) < 0) {
return -1;
......@@ -89,9 +89,9 @@ static int accept_pci(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
di->h2d_nentries = H2D_ENUM;
if (*sync_pci)
di->flags |= COSIM_PCIE_PROTO_FLAGS_DI_SYNC;
di->flags |= SIMBRICKS_PROTO_PCIE_FLAGS_DI_SYNC;
else
di->flags &= ~((uint64_t)COSIM_PCIE_PROTO_FLAGS_DI_SYNC);
di->flags &= ~((uint64_t)SIMBRICKS_PROTO_PCIE_FLAGS_DI_SYNC);
if (uxsocket_send(pci_cfd, di, sizeof(*di), shm_fd)) {
return -1;
......@@ -129,7 +129,7 @@ static int accept_eth(int eth_lfd, int *sync_eth) {
return 0;
}
static int accept_conns(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
static int accept_conns(struct SimbricksProtoPcieDevIntro *di, int pci_lfd,
int *sync_pci, int eth_lfd, int *sync_eth) {
struct pollfd pfds[2];
int await_pci = pci_lfd != -1;
......@@ -177,7 +177,7 @@ static int accept_conns(struct cosim_pcie_proto_dev_intro *di, int pci_lfd,
}
int nicsim_init(struct nicsim_params *params,
struct cosim_pcie_proto_dev_intro *di) {
struct SimbricksProtoPcieDevIntro *di) {
int pci_lfd = -1, eth_lfd = -1;
void *shmptr;
size_t shm_size;
......@@ -221,11 +221,11 @@ int nicsim_init(struct nicsim_params *params,
/* receive introductions from other end */
if (params->pci_socket_path != NULL) {
struct cosim_pcie_proto_host_intro hi;
struct SimbricksProtoPcieHostIntro hi;
if (recv(pci_cfd, &hi, sizeof(hi), 0) != sizeof(hi)) {
return -1;
}
if ((hi.flags & COSIM_PCIE_PROTO_FLAGS_HI_SYNC) == 0)
if ((hi.flags & SIMBRICKS_PROTO_PCIE_FLAGS_HI_SYNC) == 0)
params->sync_pci = 0;
printf("pci host info received\n");
}
......@@ -252,7 +252,7 @@ void nicsim_cleanup(void) {
int nicsim_sync(struct nicsim_params *params, uint64_t timestamp) {
int ret = 0;
volatile union cosim_pcie_proto_d2h *d2h;
volatile union SimbricksProtoPcieD2H *d2h;
volatile union cosim_eth_proto_d2n *d2n;
/* sync PCI if necessary */
......@@ -278,7 +278,8 @@ int nicsim_sync(struct nicsim_params *params, uint64_t timestamp) {
ret = -1;
} else {
d2h->sync.own_type =
COSIM_PCIE_PROTO_D2H_MSG_SYNC | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_SYNC |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
}
}
......@@ -353,14 +354,14 @@ uint64_t nicsim_next_timestamp(struct nicsim_params *params) {
/******************************************************************************/
/* PCI */
volatile union cosim_pcie_proto_h2d *nicif_h2d_poll(
volatile union SimbricksProtoPcieH2D *nicif_h2d_poll(
struct nicsim_params *params, uint64_t timestamp) {
volatile union cosim_pcie_proto_h2d *msg =
(volatile union cosim_pcie_proto_h2d *)(h2d_queue + h2d_pos * H2D_ELEN);
volatile union SimbricksProtoPcieH2D *msg =
(volatile union SimbricksProtoPcieH2D *)(h2d_queue + h2d_pos * H2D_ELEN);
/* message not ready */
if ((msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_OWN_MASK) !=
COSIM_PCIE_PROTO_H2D_OWN_DEV)
if ((msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_H2D_OWN_MASK) !=
SIMBRICKS_PROTO_PCIE_H2D_OWN_DEV)
return NULL;
/* if in sync mode, wait till message is ready */
......@@ -371,22 +372,23 @@ volatile union cosim_pcie_proto_h2d *nicif_h2d_poll(
return msg;
}
void nicif_h2d_done(volatile union cosim_pcie_proto_h2d *msg) {
msg->dummy.own_type = (msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_MSG_MASK) |
COSIM_PCIE_PROTO_H2D_OWN_HOST;
void nicif_h2d_done(volatile union SimbricksProtoPcieH2D *msg) {
msg->dummy.own_type =
(msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_H2D_MSG_MASK) |
SIMBRICKS_PROTO_PCIE_H2D_OWN_HOST;
}
void nicif_h2d_next(void) {
h2d_pos = (h2d_pos + 1) % H2D_ENUM;
}
volatile union cosim_pcie_proto_d2h *nicsim_d2h_alloc(
volatile union SimbricksProtoPcieD2H *nicsim_d2h_alloc(
struct nicsim_params *params, uint64_t timestamp) {
volatile union cosim_pcie_proto_d2h *msg =
(volatile union cosim_pcie_proto_d2h *)(d2h_queue + d2h_pos * D2H_ELEN);
volatile union SimbricksProtoPcieD2H *msg =
(volatile union SimbricksProtoPcieD2H *)(d2h_queue + d2h_pos * D2H_ELEN);
if ((msg->dummy.own_type & COSIM_PCIE_PROTO_D2H_OWN_MASK) !=
COSIM_PCIE_PROTO_D2H_OWN_DEV) {
if ((msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_D2H_OWN_MASK) !=
SIMBRICKS_PROTO_PCIE_D2H_OWN_DEV) {
return NULL;
}
......
lib/simbricks/nicif/nicsim.h
View file @ 69f0e0d1
......@@ -46,7 +46,7 @@ struct nicsim_params {
};
int nicsim_init(struct nicsim_params *params,
struct cosim_pcie_proto_dev_intro *di);
struct SimbricksProtoPcieDevIntro *di);
void nicsim_cleanup(void);
int nicsim_sync(struct nicsim_params *params, uint64_t timestamp);
......@@ -54,12 +54,12 @@ void nicsim_advance_epoch(struct nicsim_params *params, uint64_t timestamp);
uint64_t nicsim_advance_time(struct nicsim_params *params, uint64_t timestamp);
uint64_t nicsim_next_timestamp(struct nicsim_params *params);
volatile union cosim_pcie_proto_h2d *nicif_h2d_poll(
volatile union SimbricksProtoPcieH2D *nicif_h2d_poll(
struct nicsim_params *params, uint64_t timestamp);
void nicif_h2d_done(volatile union cosim_pcie_proto_h2d *msg);
void nicif_h2d_done(volatile union SimbricksProtoPcieH2D *msg);
void nicif_h2d_next(void);
volatile union cosim_pcie_proto_d2h *nicsim_d2h_alloc(
volatile union SimbricksProtoPcieD2H *nicsim_d2h_alloc(
struct nicsim_params *params, uint64_t timestamp);
volatile union cosim_eth_proto_n2d *nicif_n2d_poll(struct nicsim_params *params,
......
lib/simbricks/proto/pcie.h
View file @ 69f0e0d1
......@@ -27,35 +27,35 @@
#include <stdint.h>
// #define COSIM_PCI_MSG_SZCHECK(s) static_assert(sizeof(s) == 64)
// #define COSIM_PCI_MSG_SZCHECK(s) _Static_assert(sizeof(s) == 64)
#define COSIM_PCI_MSG_SZCHECK(s)
// #define SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(s) static_assert(sizeof(s) == 64)
// #define SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(s) _Static_assert(sizeof(s) == 64)
#define SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(s)
/******************************************************************************/
/* Initialization messages on Unix socket */
/** in dev_intro.flags to indicate that sender supports issuing syncs. */
#define COSIM_PCIE_PROTO_FLAGS_DI_SYNC (1 << 0)
#define SIMBRICKS_PROTO_PCIE_FLAGS_DI_SYNC (1 << 0)
/** Number of PCI bars */
#define COSIM_PCIE_PROTO_NBARS 6
#define SIMBRICKS_PROTO_PCIE_NBARS 6
/** in bars.flags: this is an I/O port bar. (otherwise memory) */
#define COSIM_PCIE_PROTO_BAR_IO (1 << 0)
#define SIMBRICKS_PROTO_PCIE_BAR_IO (1 << 0)
/** in bars.flags: this is a 64-bit bar. (otherwise 32-bit only) */
#define COSIM_PCIE_PROTO_BAR_64 (1 << 1)
#define SIMBRICKS_PROTO_PCIE_BAR_64 (1 << 1)
/** in bars.flags: this memory bar is prefetchable */
#define COSIM_PCIE_PROTO_BAR_PF (1 << 2)
#define SIMBRICKS_PROTO_PCIE_BAR_PF (1 << 2)
/** in bars.flags: this memory bar is a dummy bar (device doesn't get MMIO
* messages for this, but it dose get exposed to software. used for MSI-X). */
#define COSIM_PCIE_PROTO_BAR_DUMMY (1 << 3)
#define SIMBRICKS_PROTO_PCIE_BAR_DUMMY (1 << 3)
/**
* welcome message sent by device to host. This message comes with the shared
* memory file descriptor attached.
*/
struct cosim_pcie_proto_dev_intro {
/** flags: see COSIM_PCIE_PROTO_FLAGS_DI_* */
struct SimbricksProtoPcieDevIntro {
/** flags: see SIMBRICKS_PROTO_PCIE_FLAGS_DI_* */
uint64_t flags;
/** offset of the device-to-host queue in shared memory region */
......@@ -76,9 +76,9 @@ struct cosim_pcie_proto_dev_intro {
struct {
/** length of the bar in bytes (len = 0 indicates unused bar) */
uint64_t len;
/** flags (see COSIM_PCIE_PROTO_BAR_*) */
/** flags (see SIMBRICKS_PROTO_PCIE_BAR_*) */
uint64_t flags;
} __attribute__((packed)) bars[COSIM_PCIE_PROTO_NBARS];
} __attribute__((packed)) bars[SIMBRICKS_PROTO_PCIE_NBARS];
/** PCI vendor id */
uint16_t pci_vendor_id;
......@@ -108,11 +108,11 @@ struct cosim_pcie_proto_dev_intro {
uint16_t psi_msix_cap_offset;
} __attribute__((packed));
#define COSIM_PCIE_PROTO_FLAGS_HI_SYNC (1 << 0)
#define SIMBRICKS_PROTO_PCIE_FLAGS_HI_SYNC (1 << 0)
/** welcome message sent by host to device */
struct cosim_pcie_proto_host_intro {
/** flags: see COSIM_PCIE_PROTO_FLAGS_HI_* */
struct SimbricksProtoPcieHostIntro {
/** flags: see SIMBRICKS_PROTO_PCIE_FLAGS_HI_* */
uint64_t flags;
} __attribute__((packed));
......@@ -120,38 +120,38 @@ struct cosim_pcie_proto_host_intro {
/* Messages on in-memory device to host channel */
/** Mask for ownership bit in own_type field */
#define COSIM_PCIE_PROTO_D2H_OWN_MASK 0x80
#define SIMBRICKS_PROTO_PCIE_D2H_OWN_MASK 0x80
/** Message is owned by device */
#define COSIM_PCIE_PROTO_D2H_OWN_DEV 0x00
#define SIMBRICKS_PROTO_PCIE_D2H_OWN_DEV 0x00
/** Message is owned by host */
#define COSIM_PCIE_PROTO_D2H_OWN_HOST 0x80
#define SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST 0x80
/** Mask for type value in own_type field */
#define COSIM_PCIE_PROTO_D2H_MSG_MASK 0x7f
#define COSIM_PCIE_PROTO_D2H_MSG_SYNC 0x1
#define COSIM_PCIE_PROTO_D2H_MSG_READ 0x2
#define COSIM_PCIE_PROTO_D2H_MSG_WRITE 0x3
#define COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT 0x4
#define COSIM_PCIE_PROTO_D2H_MSG_READCOMP 0x5
#define COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP 0x6
struct cosim_pcie_proto_d2h_dummy {
#define SIMBRICKS_PROTO_PCIE_D2H_MSG_MASK 0x7f
#define SIMBRICKS_PROTO_PCIE_D2H_MSG_SYNC 0x1
#define SIMBRICKS_PROTO_PCIE_D2H_MSG_READ 0x2
#define SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITE 0x3
#define SIMBRICKS_PROTO_PCIE_D2H_MSG_INTERRUPT 0x4
#define SIMBRICKS_PROTO_PCIE_D2H_MSG_READCOMP 0x5
#define SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITECOMP 0x6
struct SimbricksProtoPcieD2HDummy {
uint8_t pad[48];
uint64_t timestamp;
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_d2h_dummy);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieD2HDummy);
struct cosim_pcie_proto_d2h_sync {
struct SimbricksProtoPcieD2HSync {
uint8_t pad[48];
uint64_t timestamp;
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_d2h_sync);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieD2HSync);
struct cosim_pcie_proto_d2h_read {
struct SimbricksProtoPcieD2HRead {
uint64_t req_id;
uint64_t offset;
uint16_t len;
......@@ -160,9 +160,9 @@ struct cosim_pcie_proto_d2h_read {
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_d2h_read);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieD2HRead);
struct cosim_pcie_proto_d2h_write {
struct SimbricksProtoPcieD2HWrite {
uint64_t req_id;
uint64_t offset;
uint16_t len;
......@@ -172,14 +172,14 @@ struct cosim_pcie_proto_d2h_write {
uint8_t own_type;
uint8_t data[];
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_d2h_write);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieD2HWrite);
#define COSIM_PCIE_PROTO_INT_LEGACY_HI 0
#define COSIM_PCIE_PROTO_INT_LEGACY_LO 1
#define COSIM_PCIE_PROTO_INT_MSI 2
#define COSIM_PCIE_PROTO_INT_MSIX 3
#define SIMBRICKS_PROTO_PCIE_INT_LEGACY_HI 0
#define SIMBRICKS_PROTO_PCIE_INT_LEGACY_LO 1
#define SIMBRICKS_PROTO_PCIE_INT_MSI 2
#define SIMBRICKS_PROTO_PCIE_INT_MSIX 3
struct cosim_pcie_proto_d2h_interrupt {
struct SimbricksProtoPcieD2HInterrupt {
uint16_t vector;
uint8_t inttype;
uint8_t pad[45];
......@@ -187,9 +187,9 @@ struct cosim_pcie_proto_d2h_interrupt {
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_d2h_interrupt);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieD2HInterrupt);
struct cosim_pcie_proto_d2h_readcomp {
struct SimbricksProtoPcieD2HReadcomp {
uint64_t req_id;
uint8_t pad[40];
uint64_t timestamp;
......@@ -197,62 +197,62 @@ struct cosim_pcie_proto_d2h_readcomp {
uint8_t own_type;
uint8_t data[];
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_d2h_readcomp);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieD2HReadcomp);
struct cosim_pcie_proto_d2h_writecomp {
struct SimbricksProtoPcieD2HWritecomp {
uint64_t req_id;
uint8_t pad[40];
uint64_t timestamp;
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_d2h_writecomp);
union cosim_pcie_proto_d2h {
struct cosim_pcie_proto_d2h_dummy dummy;
struct cosim_pcie_proto_d2h_sync sync;
struct cosim_pcie_proto_d2h_read read;
struct cosim_pcie_proto_d2h_write write;
struct cosim_pcie_proto_d2h_interrupt interrupt;
struct cosim_pcie_proto_d2h_readcomp readcomp;
struct cosim_pcie_proto_d2h_writecomp writecomp;
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieD2HWritecomp);
union SimbricksProtoPcieD2H {
struct SimbricksProtoPcieD2HDummy dummy;
struct SimbricksProtoPcieD2HSync sync;
struct SimbricksProtoPcieD2HRead read;
struct SimbricksProtoPcieD2HWrite write;
struct SimbricksProtoPcieD2HInterrupt interrupt;
struct SimbricksProtoPcieD2HReadcomp readcomp;
struct SimbricksProtoPcieD2HWritecomp writecomp;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(union cosim_pcie_proto_d2h);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(union SimbricksProtoPcieD2H);
/******************************************************************************/
/* Messages on in-memory host to device channel */
#define COSIM_PCIE_PROTO_H2D_OWN_MASK 0x80
#define SIMBRICKS_PROTO_PCIE_H2D_OWN_MASK 0x80
/** Message is owned by host */
#define COSIM_PCIE_PROTO_H2D_OWN_HOST 0x00
#define SIMBRICKS_PROTO_PCIE_H2D_OWN_HOST 0x00
/** Message is owned by device */
#define COSIM_PCIE_PROTO_H2D_OWN_DEV 0x80
#define SIMBRICKS_PROTO_PCIE_H2D_OWN_DEV 0x80
#define COSIM_PCIE_PROTO_H2D_MSG_MASK 0x7f
#define COSIM_PCIE_PROTO_H2D_MSG_SYNC 0x1
#define COSIM_PCIE_PROTO_H2D_MSG_READ 0x2
#define COSIM_PCIE_PROTO_H2D_MSG_WRITE 0x3
#define COSIM_PCIE_PROTO_H2D_MSG_READCOMP 0x4
#define COSIM_PCIE_PROTO_H2D_MSG_WRITECOMP 0x5
#define COSIM_PCIE_PROTO_H2D_MSG_DEVCTRL 0x7
#define SIMBRICKS_PROTO_PCIE_H2D_MSG_MASK 0x7f
#define SIMBRICKS_PROTO_PCIE_H2D_MSG_SYNC 0x1
#define SIMBRICKS_PROTO_PCIE_H2D_MSG_READ 0x2
#define SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITE 0x3
#define SIMBRICKS_PROTO_PCIE_H2D_MSG_READCOMP 0x4
#define SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITECOMP 0x5
#define SIMBRICKS_PROTO_PCIE_H2D_MSG_DEVCTRL 0x7
struct cosim_pcie_proto_h2d_dummy {
struct SimbricksProtoPcieH2DDummy {
uint8_t pad[48];
uint64_t timestamp;
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_h2d_dummy);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieH2DDummy);
struct cosim_pcie_proto_h2d_sync {
struct SimbricksProtoPcieH2DSync {
uint8_t pad[48];
uint64_t timestamp;
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_h2d_sync);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieH2DSync);
struct cosim_pcie_proto_h2d_read {
struct SimbricksProtoPcieH2DRead {
uint64_t req_id;
uint64_t offset;
uint16_t len;
......@@ -262,9 +262,9 @@ struct cosim_pcie_proto_h2d_read {
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_h2d_read);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieH2DRead);
struct cosim_pcie_proto_h2d_write {
struct SimbricksProtoPcieH2DWrite {
uint64_t req_id;
uint64_t offset;
uint16_t len;
......@@ -275,9 +275,9 @@ struct cosim_pcie_proto_h2d_write {
uint8_t own_type;
uint8_t data[];
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_h2d_write);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieH2DWrite);
struct cosim_pcie_proto_h2d_readcomp {
struct SimbricksProtoPcieH2DReadcomp {
uint64_t req_id;
uint8_t pad[40];
uint64_t timestamp;
......@@ -285,38 +285,38 @@ struct cosim_pcie_proto_h2d_readcomp {
uint8_t own_type;
uint8_t data[];
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_h2d_readcomp);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieH2DReadcomp);
struct cosim_pcie_proto_h2d_writecomp {
struct SimbricksProtoPcieH2DWritecomp {
uint64_t req_id;
uint8_t pad[40];
uint64_t timestamp;
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_h2d_writecomp);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieH2DWritecomp);
#define COSIM_PCIE_PROTO_CTRL_INTX_EN (1 << 0)
#define COSIM_PCIE_PROTO_CTRL_MSI_EN (1 << 1)
#define COSIM_PCIE_PROTO_CTRL_MSIX_EN (1 << 2)
struct cosim_pcie_proto_h2d_devctrl {
#define SIMBRICKS_PROTO_PCIE_CTRL_INTX_EN (1 << 0)
#define SIMBRICKS_PROTO_PCIE_CTRL_MSI_EN (1 << 1)
#define SIMBRICKS_PROTO_PCIE_CTRL_MSIX_EN (1 << 2)
struct SimbricksProtoPcieH2DDevctrl {
uint64_t flags;
uint8_t pad[40];
uint64_t timestamp;
uint8_t pad_[7];
uint8_t own_type;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(struct cosim_pcie_proto_h2d_devctrl);
union cosim_pcie_proto_h2d {
struct cosim_pcie_proto_h2d_dummy dummy;
struct cosim_pcie_proto_h2d_sync sync;
struct cosim_pcie_proto_h2d_read read;
struct cosim_pcie_proto_h2d_write write;
struct cosim_pcie_proto_h2d_readcomp readcomp;
struct cosim_pcie_proto_h2d_writecomp writecomp;
struct cosim_pcie_proto_h2d_devctrl devctrl;
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(struct SimbricksProtoPcieH2DDevctrl);
union SimbricksProtoPcieH2D {
struct SimbricksProtoPcieH2DDummy dummy;
struct SimbricksProtoPcieH2DSync sync;
struct SimbricksProtoPcieH2DRead read;
struct SimbricksProtoPcieH2DWrite write;
struct SimbricksProtoPcieH2DReadcomp readcomp;
struct SimbricksProtoPcieH2DWritecomp writecomp;
struct SimbricksProtoPcieH2DDevctrl devctrl;
} __attribute__((packed));
COSIM_PCI_MSG_SZCHECK(union cosim_pcie_proto_h2d);
SIMBRICKS_PROTO_PCIE_MSG_SZCHECK(union SimbricksProtoPcieH2D);
#endif // SIMBRICKS_PROTO_PCIE_H_
gem5 @ 3424c70b
Compare 773339d9...3424c70b
Subproject commit 773339d99147a26004c6b68ba482247fdce53176
Subproject commit 3424c70bf8309fab93e8e4a76225452c9c967f58
qemu @ a25e4b55
Compare 807475cb...a25e4b55
Subproject commit 807475cbd35377a9d6ac81570518a841dcff8338
Subproject commit a25e4b55426c5120acd204e4f293b1de7d7fe82b
sims/nic/corundum/corundum_verilator.cc
View file @ 69f0e0d1
......@@ -34,6 +34,7 @@
extern "C" {
#include <simbricks/nicif/nicsim.h>
#include <simbricks/proto/pcie.h>
}
#include "sims/nic/corundum/coord.h"
......@@ -57,7 +58,7 @@ static struct nicsim_params nsparams;
static VerilatedVcdC *trace;
#endif
static volatile union cosim_pcie_proto_d2h *d2h_alloc(void);
static volatile union SimbricksProtoPcieD2H *d2h_alloc(void);
static void sigint_handler(int dummy) {
exiting = 1;
......@@ -356,9 +357,9 @@ class MMIOInterface {
};
void pci_rwcomp_issue(MMIOOp *op) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile struct cosim_pcie_proto_d2h_readcomp *rc;
volatile struct cosim_pcie_proto_d2h_writecomp *wc;
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
volatile struct SimbricksProtoPcieD2HReadcomp *rc;
volatile struct SimbricksProtoPcieD2HWritecomp *wc;
if (!msg)
throw "completion alloc failed";
......@@ -369,7 +370,8 @@ void pci_rwcomp_issue(MMIOOp *op) {
// WMB();
wc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITECOMP |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
} else {
rc = &msg->readcomp;
memcpy((void *)rc->data, &op->value, op->len);
......@@ -377,7 +379,8 @@ void pci_rwcomp_issue(MMIOOp *op) {
// WMB();
rc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READCOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_READCOMP |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
delete op;
......@@ -386,14 +389,14 @@ void pci_rwcomp_issue(MMIOOp *op) {
std::set<DMAOp *> pci_dma_pending;
void pci_dma_issue(DMAOp *op) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
uint8_t ty;
if (!msg)
throw "completion alloc failed";
if (op->write) {
volatile struct cosim_pcie_proto_d2h_write *write = &msg->write;
volatile struct SimbricksProtoPcieD2HWrite *write = &msg->write;
write->req_id = (uintptr_t)op;
write->offset = op->dma_addr;
write->len = op->len;
......@@ -403,22 +406,22 @@ void pci_dma_issue(DMAOp *op) {
// WMB();
write->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITE | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITE | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
} else {
volatile struct cosim_pcie_proto_d2h_read *read = &msg->read;
volatile struct SimbricksProtoPcieD2HRead *read = &msg->read;
read->req_id = (uintptr_t)op;
read->offset = op->dma_addr;
read->len = op->len;
// WMB();
read->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READ | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_READ | SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
pci_dma_pending.insert(op);
}
static void h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc) {
static void h2d_readcomp(volatile struct SimbricksProtoPcieH2DReadcomp *rc) {
DMAOp *op = (DMAOp *)(uintptr_t)rc->req_id;
if (pci_dma_pending.find(op) == pci_dma_pending.end())
throw "unexpected completion";
......@@ -436,7 +439,7 @@ static void h2d_readcomp(volatile struct cosim_pcie_proto_h2d_readcomp *rc) {
op->engine->pci_op_complete(op);
}
static void h2d_writecomp(volatile struct cosim_pcie_proto_h2d_writecomp *wc) {
static void h2d_writecomp(volatile struct SimbricksProtoPcieH2DWritecomp *wc) {
DMAOp *op = (DMAOp *)(uintptr_t)wc->req_id;
if (pci_dma_pending.find(op) == pci_dma_pending.end())
throw "unexpected completion";
......@@ -479,11 +482,11 @@ static void csr_write(uint64_t off, uint64_t val) {
}
static void h2d_read(MMIOInterface &mmio,
volatile struct cosim_pcie_proto_h2d_read *read) {
volatile struct SimbricksProtoPcieH2DRead *read) {
// std::cout << "got read " << read->offset << std::endl;
if (read->offset < 0x80000) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile struct cosim_pcie_proto_d2h_readcomp *rc;
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
volatile struct SimbricksProtoPcieD2HReadcomp *rc;
if (!msg)
throw "completion alloc failed";
......@@ -496,7 +499,8 @@ static void h2d_read(MMIOInterface &mmio,
// WMB();
rc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_READCOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_READCOMP |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
} else {
/*printf("read(bar=%u, off=%lu, len=%u) = %lu\n", read->bar, read->offset,
read->len, val);*/
......@@ -505,7 +509,7 @@ static void h2d_read(MMIOInterface &mmio,
}
static void h2d_write(MMIOInterface &mmio,
volatile struct cosim_pcie_proto_h2d_write *write) {
volatile struct SimbricksProtoPcieH2DWrite *write) {
uint64_t val = 0;
memcpy(&val, (void *)write->data, write->len);
......@@ -513,8 +517,8 @@ static void h2d_write(MMIOInterface &mmio,
// std::cout << "got write " << write->offset << " = " << val << std::endl;
if (write->offset < 0x80000) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile struct cosim_pcie_proto_d2h_writecomp *wc;
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
volatile struct SimbricksProtoPcieD2HWritecomp *wc;
if (!msg)
throw "completion alloc failed";
......@@ -526,44 +530,45 @@ static void h2d_write(MMIOInterface &mmio,
// WMB();
wc->own_type =
COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_WRITECOMP |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
} else {
mmio.issueWrite(write->req_id, write->offset, write->len, val);
}
}
static void poll_h2d(MMIOInterface &mmio) {
volatile union cosim_pcie_proto_h2d *msg =
volatile union SimbricksProtoPcieH2D *msg =
nicif_h2d_poll(&nsparams, main_time);
uint8_t t;
if (msg == NULL)
return;
t = msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_MSG_MASK;
t = msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_H2D_MSG_MASK;
// std::cerr << "poll_h2d: polled type=" << (int) t << std::endl;
switch (t) {
case COSIM_PCIE_PROTO_H2D_MSG_READ:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_READ:
h2d_read(mmio, &msg->read);
break;
case COSIM_PCIE_PROTO_H2D_MSG_WRITE:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITE:
h2d_write(mmio, &msg->write);
break;
case COSIM_PCIE_PROTO_H2D_MSG_READCOMP:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_READCOMP:
h2d_readcomp(&msg->readcomp);
break;
case COSIM_PCIE_PROTO_H2D_MSG_WRITECOMP:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_WRITECOMP:
h2d_writecomp(&msg->writecomp);
break;
case COSIM_PCIE_PROTO_H2D_MSG_DEVCTRL:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_DEVCTRL:
break;
case COSIM_PCIE_PROTO_H2D_MSG_SYNC:
case SIMBRICKS_PROTO_PCIE_H2D_MSG_SYNC:
break;
default:
......@@ -574,7 +579,7 @@ static void poll_h2d(MMIOInterface &mmio) {
nicif_h2d_next();
}
static volatile union cosim_pcie_proto_d2h *d2h_alloc(void) {
static volatile union SimbricksProtoPcieD2H *d2h_alloc(void) {
return nicsim_d2h_alloc(&nsparams, main_time);
}
......@@ -752,8 +757,8 @@ static void poll_n2d(EthernetRx &rx) {
}
void pci_msi_issue(uint8_t vec) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile struct cosim_pcie_proto_d2h_interrupt *intr;
volatile union SimbricksProtoPcieD2H *msg = d2h_alloc();
volatile struct SimbricksProtoPcieD2HInterrupt *intr;
#ifdef MSI_DEBUG
std::cerr << main_time << " MSI interrupt vec=" << (int)vec << std::endl;
......@@ -761,11 +766,12 @@ void pci_msi_issue(uint8_t vec) {
intr = &msg->interrupt;
intr->vector = vec;
intr->inttype = COSIM_PCIE_PROTO_INT_MSI;
intr->inttype = SIMBRICKS_PROTO_PCIE_INT_MSI;
// WMB();
intr->own_type =
COSIM_PCIE_PROTO_D2H_MSG_INTERRUPT | COSIM_PCIE_PROTO_D2H_OWN_HOST;
SIMBRICKS_PROTO_PCIE_D2H_MSG_INTERRUPT |
SIMBRICKS_PROTO_PCIE_D2H_OWN_HOST;
}
static void msi_step(Vinterface &top, PCICoordinator &coord) {
......@@ -812,11 +818,11 @@ int main(int argc, char *argv[]) {
if (argc >= 10)
clock_period = 1000000ULL / strtoull(argv[9], NULL, 0);
struct cosim_pcie_proto_dev_intro di;
struct SimbricksProtoPcieDevIntro di;
memset(&di, 0, sizeof(di));
di.bars[0].len = 1 << 24;
di.bars[0].flags = COSIM_PCIE_PROTO_BAR_64;
di.bars[0].flags = SIMBRICKS_PROTO_PCIE_BAR_64;
di.pci_vendor_id = 0x5543;
di.pci_device_id = 0x1001;
......
sims/nic/corundum_bm/corundum_bm.cc
View file @ 69f0e0d1
......@@ -686,9 +686,9 @@ void Corundum::reg_write(uint8_t bar, uint64_t addr, reg_t val) {
}
}
void Corundum::setup_intro(struct cosim_pcie_proto_dev_intro &di) {
void Corundum::setup_intro(struct SimbricksProtoPcieDevIntro &di) {
di.bars[0].len = 1 << 24;
di.bars[0].flags = COSIM_PCIE_PROTO_BAR_64;
di.bars[0].flags = SIMBRICKS_PROTO_PCIE_BAR_64;
di.pci_vendor_id = 0x5543;
di.pci_device_id = 0x1001;
di.pci_class = 0x02;
......
sims/nic/corundum_bm/corundum_bm.h
View file @ 69f0e0d1
......@@ -323,7 +323,7 @@ class Corundum : public nicbm::SimpleDevice<reg_t> {
Corundum();
~Corundum();
virtual void setup_intro(struct cosim_pcie_proto_dev_intro &di);
virtual void setup_intro(struct SimbricksProtoPcieDevIntro &di);
virtual reg_t reg_read(uint8_t bar, addr_t addr);
virtual void reg_write(uint8_t bar, addr_t addr, reg_t val);
virtual void dma_complete(nicbm::DMAOp &op);
......
sims/nic/corundum_bm/tester.c
View file @ 69f0e0d1
......@@ -23,9 +23,7 @@
*/
#include <assert.h>
#include <cosim_pcie_proto.h>
#include <fcntl.h>
#include <nicsim.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
......@@ -35,6 +33,9 @@
#include <sys/un.h>
#include <unistd.h>
#include <simbricks/nicif/nicsim.h>
#include <simbricks/proto/pcie.h>
static uint8_t *d2h_queue;
static size_t d2h_pos;
static size_t d2h_elen;
......@@ -69,7 +70,7 @@ static int uxsocket_init() {
return cfd;
}
static int queue_create(const struct cosim_pcie_proto_dev_intro di) {
static int queue_create(const struct SimbricksProtoPcieDevIntro di) {
int fd = -1;
if ((fd = open("/dev/shm/dummy_nic_shm", O_RDWR)) == -1) {
perror("Failed to open shm file");
......@@ -102,12 +103,12 @@ error:
return -1;
}
volatile union cosim_pcie_proto_h2d *h2d_alloc() {
volatile union cosim_pcie_proto_h2d *msg =
(volatile union cosim_pcie_proto_h2d *)(h2d_queue + h2d_pos * h2d_elen);
volatile union SimbricksProtoPcieH2D *h2d_alloc() {
volatile union SimbricksProtoPcieH2D *msg =
(volatile union SimbricksProtoPcieH2D *)(h2d_queue + h2d_pos * h2d_elen);
if ((msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_OWN_MASK) !=
COSIM_PCIE_PROTO_H2D_OWN_HOST) {
if ((msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_H2D_OWN_MASK) !=
SIMBRICKS_PROTO_PCIE_H2D_OWN_HOST) {
fprintf(stderr, "cosim: failed to allocate h2d message\n");
exit(1);
}
......@@ -116,37 +117,40 @@ volatile union cosim_pcie_proto_h2d *h2d_alloc() {
return msg;
}
volatile union cosim_pcie_proto_d2h *d2h_poll() {
volatile union cosim_pcie_proto_d2h *msg;
volatile union SimbricksProtoPcieD2H *d2h_poll() {
volatile union SimbricksProtoPcieD2H *msg;
msg = (volatile union cosim_pcie_proto_d2h *)(d2h_queue + d2h_pos * d2h_elen);
if ((msg->dummy.own_type & COSIM_PCIE_PROTO_D2H_OWN_MASK) ==
COSIM_PCIE_PROTO_D2H_OWN_DEV) {
msg = (volatile union SimbricksProtoPcieD2H *)
(d2h_queue + d2h_pos * d2h_elen);
if ((msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_D2H_OWN_MASK) ==
SIMBRICKS_PROTO_PCIE_D2H_OWN_DEV) {
return NULL;
}
return msg;
}
void d2h_done(volatile union cosim_pcie_proto_d2h *msg) {
msg->dummy.own_type = (msg->dummy.own_type & COSIM_PCIE_PROTO_D2H_MSG_MASK) |
COSIM_PCIE_PROTO_D2H_OWN_DEV;
void d2h_done(volatile union SimbricksProtoPcieD2H *msg) {
msg->dummy.own_type =
(msg->dummy.own_type & SIMBRICKS_PROTO_PCIE_D2H_MSG_MASK) |
SIMBRICKS_PROTO_PCIE_D2H_OWN_DEV;
d2h_pos = (d2h_pos + 1) % d2h_enum;
}
static void dev_read(uint64_t offset, uint16_t len) {
volatile union cosim_pcie_proto_h2d *h2d_msg = h2d_alloc();
volatile struct cosim_pcie_proto_h2d_read *read = &h2d_msg->read;
volatile union SimbricksProtoPcieH2D *h2d_msg = h2d_alloc();
volatile struct SimbricksProtoPcieH2DRead *read = &h2d_msg->read;
read->req_id = 0xF;
read->offset = offset;
read->len = len;
read->bar = 0;
read->own_type = COSIM_PCIE_PROTO_H2D_MSG_READ | COSIM_PCIE_PROTO_H2D_OWN_DEV;
read->own_type = SIMBRICKS_PROTO_PCIE_H2D_MSG_READ |
SIMBRICKS_PROTO_PCIE_H2D_OWN_DEV;
volatile union cosim_pcie_proto_d2h *d2h_msg = NULL;
volatile union SimbricksProtoPcieD2H *d2h_msg = NULL;
while (d2h_msg == NULL) {
d2h_msg = d2h_poll();
}
volatile struct cosim_pcie_proto_d2h_readcomp *rc;
volatile struct SimbricksProtoPcieD2HReadcomp *rc;
rc = &d2h_msg->readcomp;
assert(rc->req_id == 0xF);
printf("received readcomp with data ");
......@@ -167,7 +171,7 @@ int main(int argc, char *argv[]) {
return -1;
}
struct cosim_pcie_proto_dev_intro di;
struct SimbricksProtoPcieDevIntro di;
if (recv(cfd, &di, sizeof(di), 0) != sizeof(di)) {
perror("Failed to receive dev_intro");
close(cfd);
......@@ -180,8 +184,8 @@ int main(int argc, char *argv[]) {
return -1;
}
struct cosim_pcie_proto_host_intro hi;
hi.flags = COSIM_PCIE_PROTO_FLAGS_HI_SYNC;
struct SimbricksProtoPcieHostIntro hi;
hi.flags = SIMBRICKS_PROTO_PCIE_FLAGS_HI_SYNC;
if (send(cfd, &hi, sizeof(hi), 0) != sizeof(hi)) {
perror("Failed to send host_intro");
close(cfd);
......
sims/nic/i40e_bm/i40e_bm.cc
View file @ 69f0e0d1
......@@ -48,14 +48,14 @@ i40e_bm::i40e_bm()
i40e_bm::~i40e_bm() {
}
void i40e_bm::setup_intro(struct cosim_pcie_proto_dev_intro &di) {
void i40e_bm::setup_intro(struct SimbricksProtoPcieDevIntro &di) {
di.bars[BAR_REGS].len = 4 * 1024 * 1024;
di.bars[BAR_REGS].flags = COSIM_PCIE_PROTO_BAR_64;
di.bars[BAR_REGS].flags = SIMBRICKS_PROTO_PCIE_BAR_64;
di.bars[BAR_IO].len = 32;
di.bars[BAR_IO].flags = COSIM_PCIE_PROTO_BAR_IO;
di.bars[BAR_IO].flags = SIMBRICKS_PROTO_PCIE_BAR_IO;
di.bars[BAR_MSIX].len = 32 * 1024;
di.bars[BAR_MSIX].flags =
COSIM_PCIE_PROTO_BAR_64 | COSIM_PCIE_PROTO_BAR_DUMMY;
SIMBRICKS_PROTO_PCIE_BAR_64 | SIMBRICKS_PROTO_PCIE_BAR_DUMMY;
di.pci_vendor_id = I40E_INTEL_VENDOR_ID;
di.pci_device_id = I40E_DEV_ID_QSFP_A;
......
sims/nic/i40e_bm/i40e_bm.h
View file @ 69f0e0d1
......@@ -583,7 +583,7 @@ class i40e_bm : public nicbm::Runner::Device {
i40e_bm();
~i40e_bm();
virtual void setup_intro(struct cosim_pcie_proto_dev_intro &di);
virtual void setup_intro(struct SimbricksProtoPcieDevIntro &di);
virtual void reg_read(uint8_t bar, uint64_t addr, void *dest, size_t len);
virtual uint32_t reg_read32(uint8_t bar, uint64_t addr);
virtual void reg_write(uint8_t bar, uint64_t addr, const void *src,
......
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