Skip to content
GitLab
Menu
Projects
Groups
Snippets
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Menu
Open sidebar
ycai
simbricks
Commits
6584973e
Unverified
Commit
6584973e
authored
Sep 12, 2024
by
Jakob Görgen
Browse files
addded first example helper methods
parent
696861c6
Changes
9
Show whitespace changes
Inline
Side-by-side
Showing
9 changed files
with
184 additions
and
63 deletions
+184
-63
experiments/pyexps/netperf_sysconf_jakob.py
experiments/pyexps/netperf_sysconf_jakob.py
+59
-49
experiments/simbricks/orchestration/helpers/__init__.py
experiments/simbricks/orchestration/helpers/__init__.py
+21
-0
experiments/simbricks/orchestration/helpers/system.py
experiments/simbricks/orchestration/helpers/system.py
+54
-0
experiments/simbricks/orchestration/system/base.py
experiments/simbricks/orchestration/system/base.py
+7
-0
experiments/simbricks/orchestration/system/eth.py
experiments/simbricks/orchestration/system/eth.py
+13
-6
experiments/simbricks/orchestration/system/host/base.py
experiments/simbricks/orchestration/system/host/base.py
+1
-1
experiments/simbricks/orchestration/system/mem.py
experiments/simbricks/orchestration/system/mem.py
+8
-2
experiments/simbricks/orchestration/system/nic.py
experiments/simbricks/orchestration/system/nic.py
+11
-0
experiments/simbricks/orchestration/system/pcie.py
experiments/simbricks/orchestration/system/pcie.py
+10
-5
No files found.
experiments/pyexps/netperf_sysconf_jakob.py
View file @
6584973e
from
simbricks.orchestration.system
import
base
as
sys_base
from
simbricks.orchestration.system
import
pcie
as
sys_pcie
from
simbricks.orchestration.system
import
eth
as
sys_eth
from
simbricks.orchestration.system
import
nic
as
sys_nic
from
simbricks.orchestration.system.host
import
base
as
sys_host_base
from
simbricks.orchestration.system.host
import
app
as
sys_app_base
from
simbricks.orchestration.helpers
import
system
as
helpers_sys
from
simbricks.orchestration
import
system
"""
SYSTEM CONFIGURATION
"""
def
boilerplate
():
system
=
system
.
System
()
"""
SYSTEM CONFIGURATION
"""
system
=
sys_base
.
System
()
# create client host
host0
=
sys
tem
.
CorundumLinuxHost
()
host0_app
=
sys
tem
.
PingClient
(
host0
)
host0
=
sys
_host_base
.
CorundumLinuxHost
()
host0_app
=
sys
_app_base
.
PingClient
(
host0
)
host0
.
add_app
(
host0_app
)
# create client nic
nic0
=
sys
tem
.
CorundumNIC
()
nic0
.
set_ipv4
(
'
10.0.0.1
'
)
nic0
=
sys
_nic
.
CorundumNIC
()
nic0
.
set_ipv4
(
"
10.0.0.1
"
)
# connect client host and nic
host_pci0
=
sys
tem
.
PCIeHostInterface
(
host0
)
host_pci0
=
sys
_pcie
.
PCIeHostInterface
(
host0
)
host0
.
add_if
(
host_pci0
)
nic_pci0
=
sys
tem
.
PCIeDeviceInterface
(
nic0
)
nic_pci0
=
sys
_pcie
.
PCIeDeviceInterface
(
nic0
)
nic0
.
set_pcie_if
(
nic_pci0
)
host0_nic0_chan
=
sys
tem
.
PCIeChannel
(
host_pci0
,
nic_pci0
)
host0_nic0_chan
=
sys
_pcie
.
PCIeChannel
(
host_pci0
,
nic_pci0
)
# create host server
host1
=
sys
tem
.
I40ELinuxHost
()
host1_app
=
sys
tem
.
Sleep
(
host1
)
host1
=
sys
_host_base
.
I40ELinuxHost
()
host1_app
=
sys
_app_base
.
Sleep
(
host1
)
host1
.
add_app
(
host1_app
)
# create host nic
nic1
=
sys
tem
.
I40eNIC
()
nic1
.
set_ipv4
(
'
10.0.0.2
'
)
nic1
=
sys
_nic
.
Intel
I40eNIC
()
nic1
.
set_ipv4
(
"
10.0.0.2
"
)
# connect host server to host client
host_pci1
=
sys
tem
.
PCIeHostInterface
(
host0
)
host_pci1
=
sys
_pcie
.
PCIeHostInterface
(
host0
)
host1
.
add_if
(
host_pci1
)
nic_pci1
=
sys
tem
.
PCIeDeviceInterface
(
nic1
)
nic_pci1
=
sys
_pcie
.
PCIeDeviceInterface
(
nic1
)
nic1
.
set_pcie_if
(
nic_pci1
)
host1_nic1_chan
=
sys
tem
.
PCIeChannel
(
host_pci1
,
nic_pci1
)
host1_nic1_chan
=
sys
_pcie
.
PCIeChannel
(
host_pci1
,
nic_pci1
)
# create first switch
switch0
=
sys
tem
.
EthSwitch
(
system
)
switch0
=
sys
_eth
.
EthSwitch
(
system
)
# create second switch
switch1
=
sys
tem
.
EthSwitch
(
system
)
switch1
=
sys
_eth
.
EthSwitch
(
system
)
# connect first switch to client nic
nic_eth0
=
sys
tem
.
EthInterface
(
nic0
)
nic_eth0
=
sys
_eth
.
EthInterface
(
nic0
)
nic0
.
set_eth_if
(
nic_eth0
)
switch0_for_nic
=
sys
tem
.
EthInterface
(
switch0
)
switch0_for_nic
=
sys
_eth
.
EthInterface
(
switch0
)
switch0
.
if_add
(
switch0_for_nic
)
nic0_switch0_chan
=
sys
tem
.
EthChannel
(
nic_eth0
,
switch0_for_nic
)
nic0_switch0_chan
=
sys
_eth
.
EthChannel
(
nic_eth0
,
switch0_for_nic
)
# connect second switch to server nic
nic_eth1
=
sys
tem
.
EthInterface
(
nic1
)
nic_eth1
=
sys
_eth
.
EthInterface
(
nic1
)
nic1
.
set_eth_if
(
nic_eth1
)
switch1_for_nic
=
sys
tem
.
EthInterface
(
switch1
)
switch1_for_nic
=
sys
_eth
.
EthInterface
(
switch1
)
switch1
.
if_add
(
switch1_for_nic
)
nic1_switch1_chan
=
sys
tem
.
EthChannel
(
nic_eth1
,
switch1_for_nic
)
nic1_switch1_chan
=
sys
_eth
.
EthChannel
(
nic_eth1
,
switch1_for_nic
)
# connect first switch to second switch
switch0_for_net
=
sys
tem
.
EthInterface
(
switch0
)
switch0_for_net
=
sys
_eth
.
EthInterface
(
switch0
)
switch0
.
if_add
(
switch0_for_net
)
switch1_for_net
=
sys
tem
.
EthInterface
(
switch1
)
switch1_for_net
=
sys
_eth
.
EthInterface
(
switch1
)
switch1
.
if_add
(
switch1_for_net
)
switch0_switch1_chan
=
system
.
EthChannel
(
switch0_for_net
,
switch1_for_net
)
switch0_switch1_chan
=
sys_eth
.
EthChannel
(
switch0_for_net
,
switch1_for_net
)
"""
SIMULATION CONFIGURATION
"""
"""
SYSTEM CONFIGURATION SYNTACTIC SUGAR
"""
def
syntactic_sugar
():
"""
SYSTEM CONFIGURATION SYNTACTIC SUGAR
"""
system
=
system
.
System
()
# create client host
host0
=
sys
tem
.
CorundumLinuxHost
()
install_application
(
host0
,
sys
tem
.
PingClient
(
host0
))
host0
=
sys
_host_base
.
CorundumLinuxHost
()
install_application
(
host0
,
sys
_app_base
.
PingClient
(
host0
))
# create client nic
nic0
=
sys
tem
.
CorundumNIC
()
nic0
.
set
_ipv4
(
'
10.0.0.1
'
)
nic0
=
sys
_nic
.
CorundumNIC
()
nic0
.
add
_ipv4
(
"
10.0.0.1
"
)
# connect client host and nic
connect_host_and_device
(
host
0
,
nic0
)
helpers_sys
.
connect_host_and_device
(
host
=
host0
,
device
=
nic0
)
# create host server
host1
=
sys
tem
.
I40ELinuxHost
()
host1
=
sys
_host_base
.
I40ELinuxHost
()
install_application
(
host1
,
system
.
Sleep
(
host1
))
# create host nic
nic1
=
sys
tem
.
I40eNIC
()
nic1
.
set_ipv4
(
'
10.0.0.2
'
)
nic1
=
sys
_nic
.
Intel
I40eNIC
()
nic1
.
set_ipv4
(
"
10.0.0.2
"
)
# connect host server to host client
connect_host_and_device
(
host
1
,
nic1
)
helpers_sys
.
connect_host_and_device
(
host
=
host1
,
device
=
nic1
)
# create first switch
switch0
=
sys
tem
.
EthSwitch
(
system
)
switch0
=
sys
_eth
.
EthSwitch
(
system
)
# create second switch
switch1
=
sys
tem
.
EthSwitch
(
system
)
switch1
=
sys
_eth
.
EthSwitch
(
system
)
# connect first switch to client nic
connect_
n
et_devices
(
nic0
,
switch0
)
helpers_sys
.
connect_et
h
_devices
(
device_a
=
nic0
,
device_b
=
switch0
)
# connect second switch to server nic
connect_
n
et_devices
(
nic1
,
switch1
)
helpers_sys
.
connect_et
h
_devices
(
device_a
=
nic1
,
device_b
=
switch1
)
# connect first switch to second switch
connect_net_devices
(
switch0
,
switch1
)
\ No newline at end of file
helpers_sys
.
connect_eth_devices
(
device_a
=
switch0
,
device_b
=
switch1
)
experiments/simbricks/orchestration/helpers/__init__.py
0 → 100644
View file @
6584973e
# Copyright 2024 Max Planck Institute for Software Systems, and
# National University of Singapore
#
# Permission is hereby granted, free of charge, to any person obtaining
# a copy of this software and associated documentation files (the
# "Software"), to deal in the Software without restriction, including
# without limitation the rights to use, copy, modify, merge, publish,
# distribute, sublicense, and/or sell copies of the Software, and to
# permit persons to whom the Software is furnished to do so, subject to
# the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\ No newline at end of file
experiments/simbricks/orchestration/helpers/system.py
0 → 100644
View file @
6584973e
# Copyright 2024 Max Planck Institute for Software Systems, and
# National University of Singapore
#
# Permission is hereby granted, free of charge, to any person obtaining
# a copy of this software and associated documentation files (the
# "Software"), to deal in the Software without restriction, including
# without limitation the rights to use, copy, modify, merge, publish,
# distribute, sublicense, and/or sell copies of the Software, and to
# permit persons to whom the Software is furnished to do so, subject to
# the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
from
simbricks.orchestration
import
system
from
simbricks.orchestration.utils
import
base
as
utils_base
def
connect_host_and_device
(
host
:
system
.
host
.
base
.
Host
,
device
:
system
.
base
.
Component
)
->
system
.
pcie
.
PCIeChannel
:
utils_base
.
has_expected_type
(
obj
=
host
,
expected_type
=
system
.
host
.
base
.
Host
)
utils_base
.
has_expected_type
(
obj
=
device
,
expected_type
=
system
.
base
.
Component
)
host_interface
=
system
.
pcie
.
PCIeHostInterface
(
c
=
host
)
host
.
add_if
(
interface
=
host_interface
)
device_interface
=
system
.
pcie
.
PCIeDeviceInterface
(
c
=
device
)
device
.
add_if
(
interface
=
device_interface
)
pcie_channel
=
system
.
pcie
.
PCIeChannel
(
host
=
host_interface
,
dev
=
device_interface
)
return
pcie_channel
def
connect_eth_devices
(
device_a
:
system
.
base
.
Component
,
device_b
:
system
.
base
.
Component
)
->
system
.
eth
.
EthChannel
:
utils_base
.
has_expected_type
(
obj
=
device_a
,
expected_type
=
system
.
base
.
Component
)
utils_base
.
has_expected_type
(
obj
=
device_b
,
expected_type
=
system
.
base
.
Component
)
eth_inter_a
=
system
.
eth
.
EthInterface
(
c
=
device_a
)
device_a
.
add_if
(
interface
=
eth_inter_a
)
eth_inter_b
=
system
.
eth
.
EthInterface
(
c
=
device_b
)
device_b
.
add_if
(
interface
=
eth_inter_b
)
eth_channel
=
system
.
eth
.
EthChannel
(
a
=
eth_inter_a
,
b
=
eth_inter_b
)
return
eth_channel
experiments/simbricks/orchestration/system/base.py
View file @
6584973e
...
...
@@ -22,6 +22,7 @@
from
__future__
import
annotations
import
abc
import
typing
as
tp
from
simbricks.orchestration.utils
import
base
as
util_base
...
...
@@ -49,6 +50,10 @@ class Component(util_base.IdObj):
def
interfaces
(
self
)
->
list
[
Interface
]:
return
[]
@
abc
.
abstractmethod
def
add_if
(
self
,
interface
:
tp
.
Any
)
->
None
:
raise
Exception
(
"must be overwritten by subclass"
)
def
channels
(
self
)
->
list
[
Channel
]:
return
[
i
.
channel
for
i
in
self
.
interfaces
()
if
i
.
is_connected
()]
...
...
@@ -75,7 +80,9 @@ class Channel(util_base.IdObj):
super
().
__init__
()
self
.
latency
=
500
self
.
a
:
Interface
=
a
self
.
a
.
connect
(
self
)
self
.
b
:
Interface
=
b
self
.
b
.
connect
(
self
)
def
interfaces
(
self
)
->
list
[
Interface
]:
return
[
self
.
a
,
self
.
b
]
...
...
experiments/simbricks/orchestration/system/eth.py
View file @
6584973e
...
...
@@ -21,6 +21,8 @@
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
from
simbricks.orchestration.system
import
base
from
simbricks.orchestration.system
import
pcie
from
simbricks.orchestration.utils
import
base
as
utils_base
class
EthInterface
(
base
.
Interface
):
...
...
@@ -29,8 +31,7 @@ class EthInterface(base.Interface):
def
connect
(
self
,
c
:
base
.
Channel
)
->
None
:
# Note AK: a bit ugly, but I think we can't get around a rt check here
if
not
c
is
isinstance
(
c
,
EthChannel
):
raise
TypeError
(
"EthInterface only connects to EthChannel"
)
utils_base
.
has_expected_type
(
c
,
EthChannel
)
super
().
connect
(
c
)
...
...
@@ -42,18 +43,24 @@ class EthChannel(base.Channel):
class
EthSimpleNIC
(
base
.
Component
):
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
super
().
__init__
(
s
)
self
.
ip
=
None
self
.
eth_if
=
EthInterface
(
self
)
self
.
_
ip
=
None
self
.
_
eth_if
:
EthInterface
|
None
=
None
def
add_ipv4
(
self
,
ip
:
str
)
->
None
:
assert
self
.
_ip
is
None
self
.
ip
=
ip
def
add_if
(
self
,
interface
:
EthInterface
)
->
None
:
utils_base
.
has_expected_type
(
obj
=
interface
,
expected_type
=
EthInterface
)
assert
self
.
_eth_if
is
not
None
self
.
_eth_if
=
interface
class
BaseEthNetComponent
(
base
.
Component
):
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
super
().
__init__
(
s
)
self
.
eth_ifs
:
EthInterface
=
[]
def
if_
add
(
self
,
i
:
EthInterface
)
->
None
:
def
add
_if
(
self
,
i
:
EthInterface
)
->
None
:
self
.
eth_ifs
.
append
(
i
)
def
interfaces
(
self
)
->
list
[
EthInterface
]:
...
...
@@ -64,7 +71,7 @@ class EthWire(BaseEthNetComponent):
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
super
().
__init__
(
s
)
def
if_
add
(
self
,
i
:
EthInterface
)
->
None
:
def
add
_if
(
self
,
i
:
EthInterface
)
->
None
:
if
len
(
self
.
eth_ifs
)
>
2
:
raise
Exception
(
"one can only add 2 interfaces to a EthWire"
)
self
.
eth_ifs
.
append
(
i
)
...
...
experiments/simbricks/orchestration/system/host/base.py
View file @
6584973e
...
...
@@ -40,7 +40,7 @@ class Host(base.Component):
def
interfaces
(
self
)
->
list
[
base
.
Interface
]:
return
self
.
pcie_ifs
+
self
.
eth_ifs
+
self
.
mem_ifs
def
add_if
(
self
,
i
:
base
.
Interface
)
->
None
:
def
add_if
(
self
,
i
nterface
:
base
.
Interface
)
->
None
:
self
.
ifs
.
append
(
i
)
def
add_app
(
self
,
a
:
'Application'
)
->
None
:
...
...
experiments/simbricks/orchestration/system/mem.py
View file @
6584973e
...
...
@@ -21,6 +21,7 @@
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
from
simbricks.orchestration.system
import
base
from
simbricks.orchestration.utils
import
base
as
utils_base
class
MemHostInterface
(
base
.
Interface
):
...
...
@@ -55,7 +56,12 @@ class MemChannel(base.Channel):
class
MemSimpleDevice
(
base
.
Component
):
def
__init__
(
self
,
s
:
base
.
System
):
super
().
__init__
(
s
)
self
.
mem_if
=
MemDeviceInterface
()
self
.
_
mem_if
:
MemDeviceInterface
|
None
=
None
def
interfaces
(
self
)
->
list
[
base
.
Interface
]:
return
[
self
.
mem_if
]
def
add_if
(
interface
:
MemDeviceInterface
)
->
None
:
utils_base
.
has_expected_type
(
obj
=
interface
,
expected_type
=
MemDeviceInterface
)
assert
self
.
_mem_if
is
None
self
.
_mem_if
=
interface
\ No newline at end of file
experiments/simbricks/orchestration/system/nic.py
View file @
6584973e
...
...
@@ -32,6 +32,17 @@ class SimplePCIeNIC(pcie.PCIeSimpleDevice, eth.EthSimpleNIC):
def
interfaces
(
self
)
->
list
[
base
.
Interface
]:
return
[
self
.
pci_if
,
self
.
eth_if
]
def
add_if
(
self
,
interface
:
eth
.
EthInterface
|
pcie
.
PCIeDeviceInterface
)
->
None
:
match
interface
:
case
eth
.
EthInterface
():
eth
.
EthSimpleNIC
.
add_if
(
self
,
interface
=
interface
)
case
pcie
.
PCIeDeviceInterface
():
pcie
.
PCIeSimpleDevice
.
add_if
(
self
,
interface
=
interface
)
case
_
:
raise
Exception
(
f
"interface must have type EthInterface or PCIeDeviceInterface but has type
{
type
(
interface
)
}
"
)
class
IntelI40eNIC
(
SimplePCIeNIC
):
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
...
...
experiments/simbricks/orchestration/system/pcie.py
View file @
6584973e
...
...
@@ -21,6 +21,7 @@
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
from
simbricks.orchestration.system
import
base
from
simbricks.orchestration.utils
import
base
as
utils_base
class
PCIeHostInterface
(
base
.
Interface
):
...
...
@@ -36,8 +37,7 @@ class PCIeDeviceInterface(base.Interface):
def
connect
(
self
,
c
:
base
.
Channel
)
->
None
:
# Note AK: a bit ugly, but I think we can't get around a rt check here
if
not
c
is
isinstance
(
c
,
PCIeChannel
):
raise
TypeError
(
'PCIeDeviceInterface only connects to PCIeChannel'
)
utils_base
.
has_expected_type
(
c
,
PCIeChannel
)
super
().
connect
(
c
)
...
...
@@ -56,7 +56,12 @@ class PCIeChannel(base.Channel):
class
PCIeSimpleDevice
(
base
.
Component
):
def
__init__
(
self
,
s
:
base
.
System
):
super
().
__init__
(
s
)
self
.
pci_if
=
PCIeDeviceInterface
(
self
)
self
.
_
pci_if
=
PCIeDeviceInterface
(
self
)
def
interfaces
(
self
)
->
list
[
base
.
Interface
]:
return
[
self
.
pci_if
]
def
add_if
(
interface
:
PCIeDeviceInterface
)
->
None
:
utils_base
.
has_expected_type
(
obj
=
interface
,
expected_type
=
PCIeDeviceInterface
)
assert
self
.
_pci_if
is
None
self
.
_pci_if
=
interface
\ No newline at end of file
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment