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Commit 1173e8fa authored by Jialin Li's avatar Jialin Li
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checkpoint

parent 29ddeda4
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Showing with 214 additions and 31 deletions
corundum_bm/corundum_bm.cc
View file @ 1173e8fa
......@@ -5,7 +5,7 @@
#include <unistd.h>
#include <signal.h>
#include <corundum_bm.h>
#include "corundum_bm.h"
extern "C" {
#include <nicsim.h>
......@@ -19,14 +19,142 @@ Corundum::~Corundum()
{
}
reg_t
Corundum::readReg(addr_t addr)
{
switch (addr) {
case REG_FW_ID:
return 32;
case REG_FW_VER:
return 1;
case REG_BOARD_ID:
return 0x43215678;
case REG_BOARD_VER:
return 1;
case REG_PHC_COUNT:
return 1;
case REG_PHC_OFFSET:
return 0x200;
case REG_PHC_STRIDE:
return 0x80;
case REG_IF_COUNT:
return 1;
case REG_IF_STRIDE:
return 0x80000;
case REG_IF_CSR_OFFSET:
return 0x80000;
case PHC_REG_FEATURES:
return 0x1;
case IF_REG_IF_ID:
return 0;
case IF_REG_IF_FEATURES:
return 0x711;
case IF_REG_EVENT_QUEUE_COUNT:
return 1;
case IF_REG_EVENT_QUEUE_OFFSET:
return 0x100000;
case IF_REG_TX_QUEUE_COUNT:
return 1;
case IF_REG_TX_QUEUE_OFFSET:
return 0x200000;
case IF_REG_TX_CPL_QUEUE_COUNT:
return 1;
case IF_REG_TX_CPL_QUEUE_OFFSET:
return 0x400000;
case IF_REG_RX_QUEUE_COUNT:
return 1;
case IF_REG_RX_QUEUE_OFFSET:
return 0x600000;
case IF_REG_RX_CPL_QUEUE_COUNT:
return 1;
case IF_REG_RX_CPL_QUEUE_OFFSET:
return 0x700000;
case IF_REG_PORT_COUNT:
return 1;
case IF_REG_PORT_OFFSET:
return 0x800000;
case IF_REG_PORT_STRIDE:
return 0x200000;
case TX_QUEUE_ACTIVE_LOG_SIZE_REG:
return this->txRing.sizeLog();
default:
fprintf(stderr, "Unknown register read %lx\n", addr);
abort();
}
}
void
Corundum::writeReg(addr_t addr, reg_t val)
{
switch (addr) {
case REG_FW_ID:
case REG_FW_VER:
case REG_BOARD_ID:
case REG_BOARD_VER:
case REG_PHC_COUNT:
case REG_PHC_OFFSET:
case REG_PHC_STRIDE:
case REG_IF_COUNT:
case REG_IF_STRIDE:
case REG_IF_CSR_OFFSET:
case PHC_REG_FEATURES:
case PHC_REG_PTP_SET_FNS:
case PHC_REG_PTP_SET_NS:
case PHC_REG_PTP_SET_SEC_L:
case PHC_REG_PTP_SET_SEC_H:
break;
case EVENT_QUEUE_BASE_ADDR_REG:
this->eqRing.setDMALower(val);
break;
case EVENT_QUEUE_BASE_ADDR_REG + 4:
this->eqRing.setDMAUpper(val);
break;
case EVENT_QUEUE_ACTIVE_LOG_SIZE_REG:
this->eqRing.setSizeLog(val & 0xFF);
break;
case EVENT_QUEUE_INTERRUPT_INDEX_REG:
this->eqRing.setIndex(val);
break;
case EVENT_QUEUE_HEAD_PTR_REG:
this->eqRing.setHeadPtr(val);
break;
case EVENT_QUEUE_TAIL_PTR_REG:
this->eqRing.setTailPtr(val);
break;
case TX_QUEUE_BASE_ADDR_REG:
this->txRing.setDMALower(val);
break;
case TX_QUEUE_BASE_ADDR_REG + 4:
this->txRing.setDMAUpper(val);
break;
case TX_QUEUE_ACTIVE_LOG_SIZE_REG:
this->txRing.setSizeLog(val & 0xFF);
break;
case TX_QUEUE_INTERRUPT_INDEX_REG:
this->txRing.setIndex(val);
break;
case TX_QUEUE_HEAD_PTR_REG:
this->txRing.setHeadPtr(val);
break;
case TX_QUEUE_TAIL_PTR_REG:
this->txRing.setTailPtr(val);
break;
default:
fprintf(stderr, "Unknown register write %lx\n", addr);
abort();
}
}
static volatile int exiting = 0;
static void sigint_handler(int dummy)
static void
sigint_handler(int dummy)
{
exiting = 1;
}
static volatile union cosim_pcie_proto_d2h *d2h_alloc(void)
static volatile union cosim_pcie_proto_d2h *
d2h_alloc(void)
{
volatile union cosim_pcie_proto_d2h *msg = nicsim_d2h_alloc();
if (msg == NULL) {
......@@ -36,31 +164,8 @@ static volatile union cosim_pcie_proto_d2h *d2h_alloc(void)
return msg;
}
static uint64_t csr_read(uint64_t off)
{
switch (off) {
case 0x00: return 32; /* firmware id */
case 0x04: return 1; /* firmware version */
case 0x08: return 0x43215678; /* board id */
case 0x0c: return 0x1; /* board version */
case 0x10: return 1; /* phc count */
case 0x14: return 0x200; /* phc offset */
case 0x18: return 0x80; /* phc stride */
case 0x20: return 1; /* if_count */
case 0x24: return 0x80000; /* if stride */
case 0x2c: return 0x80000; /* if csr offset */
case 0x200: return 0x1; /* phc features */
default:
fprintf(stderr, "csr_read(%lu) unimplemented\n", off);
return 0;
}
}
static void csr_write(uint64_t off, uint64_t val)
{
}
static void read_complete(uint64_t req_id, void *val, uint16_t len)
static void
read_complete(uint64_t req_id, void *val, uint16_t len)
{
volatile union cosim_pcie_proto_d2h *msg;
volatile struct cosim_pcie_proto_d2h_readcomp *rc;
......@@ -76,7 +181,8 @@ static void read_complete(uint64_t req_id, void *val, uint16_t len)
COSIM_PCIE_PROTO_D2H_OWN_HOST;
}
static void h2d_read(volatile struct cosim_pcie_proto_h2d_read *read)
static void
h2d_read(volatile struct cosim_pcie_proto_h2d_read *read)
{
printf("read(bar=0x%x, off=0x%lx, len=%u)\n", read->bar, read->offset, read->len);
if (read->offset < 0x80000) {
......@@ -86,7 +192,8 @@ static void h2d_read(volatile struct cosim_pcie_proto_h2d_read *read)
}
}
static void h2d_write(volatile struct cosim_pcie_proto_h2d_write *write)
static void
h2d_write(volatile struct cosim_pcie_proto_h2d_write *write)
{
uint64_t val = 0;
memcpy(&val, (void *)write->data, write->len);
......
corundum_bm/corundum_bm.h
View file @ 1173e8fa
......@@ -5,6 +5,78 @@
typedef uint32_t reg_t;
typedef uint64_t addr_t;
#define REG_FW_ID 0x0000
#define REG_FW_VER 0x0004
#define REG_BOARD_ID 0x0008
#define REG_BOARD_VER 0x000C
#define REG_PHC_COUNT 0x0010
#define REG_PHC_OFFSET 0x0014
#define REG_PHC_STRIDE 0x0018
#define REG_IF_COUNT 0x0020
#define REG_IF_STRIDE 0x0024
#define REG_IF_CSR_OFFSET 0x002C
#define PHC_REG_FEATURES 0x0200
#define PHC_REG_PTP_SET_FNS 0x0230
#define PHC_REG_PTP_SET_NS 0x0234
#define PHC_REG_PTP_SET_SEC_L 0x0238
#define PHC_REG_PTP_SET_SEC_H 0x023C
#define IF_REG_IF_ID 0x80000
#define IF_REG_IF_FEATURES 0x80004
#define IF_REG_EVENT_QUEUE_COUNT 0x80010
#define IF_REG_EVENT_QUEUE_OFFSET 0x80014
#define IF_REG_TX_QUEUE_COUNT 0x80020
#define IF_REG_TX_QUEUE_OFFSET 0x80024
#define IF_REG_TX_CPL_QUEUE_COUNT 0x80028
#define IF_REG_TX_CPL_QUEUE_OFFSET 0x8002C
#define IF_REG_RX_QUEUE_COUNT 0x80030
#define IF_REG_RX_QUEUE_OFFSET 0x80034
#define IF_REG_RX_CPL_QUEUE_COUNT 0x80038
#define IF_REG_RX_CPL_QUEUE_OFFSET 0x8003C
#define IF_REG_PORT_COUNT 0x80040
#define IF_REG_PORT_OFFSET 0x80044
#define IF_REG_PORT_STRIDE 0x80048
#define EVENT_QUEUE_BASE_ADDR_REG 0x100000
#define EVENT_QUEUE_ACTIVE_LOG_SIZE_REG 0x100008
#define EVENT_QUEUE_INTERRUPT_INDEX_REG 0x10000C
#define EVENT_QUEUE_HEAD_PTR_REG 0x100010
#define EVENT_QUEUE_TAIL_PTR_REG 0x100018
#define TX_QUEUE_BASE_ADDR_REG 0x200000
#define TX_QUEUE_ACTIVE_LOG_SIZE_REG 0x200008
#define TX_QUEUE_CPL_QUEUE_INDEX_REG 0x20000C
#define TX_QUEUE_HEAD_PTR_REG 0x200010
#define TX_QUEUE_TAIL_PTR_REG 0x200018
class DescRing {
public:
DescRing();
~DescRing();
addr_t dmaAddr();
size_t sizeLog();
unsigned index();
unsigned headPtr();
unsigned tailPtr();
void setDMALower(uint32_t addr);
void setDMAUpper(uint32_t addr);
void setSizeLog(size_t size_log);
void setIndex(unsigned index);
void setHeadPtr(unsigned ptr);
void setTailPtr(unsigned ptr);
private:
addr_t _dmaAddr;
size_t _sizeLog;
size_t _size;
unsigned _index;
unsigned _headPtr;
unsigned _tailPtr;
};
class Corundum {
public:
Corundum();
......@@ -14,5 +86,9 @@ public:
void writeReg(addr_t addr, reg_t val);
private:
DescRing eqRing;
DescRing txRing;
DescRing txCqRing;
DescRing rxRing;
DescRing rxCqRing;
};
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