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Unverified Commit 0d56918d authored by Jakob Görgen's avatar Jakob Görgen
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fixed host pci connect bug using wrong interfaces

parent 4c2bb680
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Showing with 104 additions and 83 deletions
experiments/pyexps/netperf_sysconf.py
View file @ 0d56918d
from simbricks.orchestration import system
from simbricks.orchestration import simulation as sim
from simbricks.orchestration import instantiation as inst
from simbricks.orchestration.helpers import simulation as sim_helpers
"""
Netperf Example:
......@@ -11,9 +11,9 @@ HOST0 -- NIC0 ------ SWITCH ------ NIC1 -- HOST1
This scripts generates the experiments with all the combinations of different execution modes
"""
host_types = ['gem5']
nic_types = ['i40e']
net_types = ['switch']
host_types = ["gem5"]
nic_types = ["i40e"]
net_types = ["switch"]
experiments = []
sys = system.System()
......@@ -26,7 +26,7 @@ host0.add_disk(cfg_disk0)
host0.add_if(pcie0)
nic0 = system.IntelI40eNIC(sys)
nic0.add_ipv4('10.0.0.1')
nic0.add_ipv4("10.0.0.1")
pcichannel0 = system.PCIeChannel(pcie0, nic0._pci_if)
# create a host instance and a NIC instance then install the NIC on the host
......@@ -35,9 +35,9 @@ pcie1 = system.PCIeHostInterface(host1)
cfg_disk1 = system.DistroDiskImage(h=host1, name="base")
host1.add_disk(cfg_disk1)
host1.add_if(pcie0)
host1.add_if(pcie1)
nic1 = system.IntelI40eNIC(sys)
nic1.add_ipv4('10.0.0.2')
nic1.add_ipv4("10.0.0.2")
pcichannel1 = system.PCIeChannel(pcie1, nic1._pci_if)
# create switch and its ports
......@@ -62,57 +62,62 @@ Execution Config
for host_type in host_types:
for nic_type in nic_types:
for net_type in net_types:
e = sim.Simulation(
'n-' + host_type + '-' + nic_type + '-' + net_type
simulation = sim.Simulation(
"n-" + host_type + "-" + nic_type + "-" + net_type
)
# Host
if host_type == 'gem5':
if host_type == "gem5":
host_sim = sim.Gem5Sim
elif host_type == 'qemu':
elif host_type == "qemu":
def qemu_sim(e):
h = sim.QemuSim(e)
h.sync = False
return h
host_sim = qemu_sim
elif host_type == 'qt':
elif host_type == "qt":
host_sim = sim.QemuSim
else:
raise NameError(host_type)
# NIC
if nic_type == 'i40e':
if nic_type == "i40e":
nic_sim = sim.I40eNicSim
elif nic_type == 'vr':
elif nic_type == "vr":
nic_sim = sim.CorundumVerilatorNICSim
else:
raise NameError(nic_type)
# Net
if net_type == 'switch':
if net_type == "switch":
net_sim = sim.SwitchNet
else:
raise NameError(net_type)
host_inst0 = host_sim(e)
host_inst0 = host_sim(simulation)
host_inst0.add(host0)
host_inst1 = host_sim(e)
host_inst1 = host_sim(simulation)
host_inst1.add(host1)
nic_inst0 = nic_sim(e)
nic_inst0 = nic_sim(simulation)
nic_inst0.add(nic0)
nic_inst1 = nic_sim(e)
nic_inst1 = nic_sim(simulation)
nic_inst1.add(nic1)
net_inst = net_sim(e)
net_inst = net_sim(simulation)
net_inst.add(switch)
print(e.name + " all simulators:")
sims = e.all_simulators()
sim_helpers.enable_sync_simulation(
simulation=simulation, amount=500, ratio=sim.Time.Nanoseconds
)
print(simulation.name + " all simulators:")
sims = simulation.all_simulators()
for s in sims:
print(s)
experiments.append(e)
experiments.append(simulation)
experiments/simbricks/orchestration/helpers/simulation.py
View file @ 0d56918d
......@@ -21,25 +21,26 @@
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
from simbricks.orchestration import system
from simbricks.orchestration import simulation
from simbricks.orchestration.simulation import base as sim_base
from simbricks.orchestration.simulation import channel as sim_chan
from simbricks.orchestration.utils import base as utils_base
def add_specs(simulator: simulation.Simulator, *specifications) -> None:
utils_base.has_expected_type(obj=simulator, expected_type=simulation.Simulator)
def add_specs(simulator: sim_base.Simulator, *specifications) -> None:
utils_base.has_expected_type(obj=simulator, expected_type=sim_base.Simulator)
for spec in specifications:
utils_base.has_expected_type(obj=spec, expected_type=system.Component)
simulator.add(comp=spec)
def enable_sync_simulation(
simulation: simulation.Simulation, amount: int = None, ratio: simulation.Time = None
simulation: sim_base.Simulation, amount: int = None, ratio: sim_chan.Time = None
) -> None:
utils_base.has_expected_type(obj=simulation, expected_type=simulation.Simulation)
utils_base.has_expected_type(obj=simulation, expected_type=sim_base.Simulation)
set_period: bool = amount is not None and ratio is not None
if set_period:
utils_base.has_expected_type(obj=amount, expected_type=int)
utils_base.has_expected_type(obj=ratio, expected_type=simulation.Time)
utils_base.has_expected_type(obj=ratio, expected_type=sim_chan.Time)
for chan in simulation.get_all_channels():
chan._synchronized = True
......@@ -47,8 +48,8 @@ def enable_sync_simulation(
chan.set_sync_period(amount=amount, ratio=ratio)
def disalbe_sync_simulation(simulation: simulation.Simulation) -> None:
utils_base.has_expected_type(obj=simulation, expected_type=simulation.Simulation)
def disalbe_sync_simulation(simulation: sim_base.Simulation) -> None:
utils_base.has_expected_type(obj=simulation, expected_type=sim_base.Simulation)
for chan in simulation.get_all_channels(lazy=False):
chan._synchronized = False
experiments/simbricks/orchestration/simulation/channel.py
View file @ 0d56918d
......@@ -37,8 +37,8 @@ class Time(enum.IntEnum):
class Channel:
def __init__(self, chan: system_base.Channel):
self._synchronized: bool = True
self.sync_period: int = 500 # nano second
self._synchronized: bool = False
self.sync_period: int = 500 # nano seconds
self.sys_channel: system_base.Channel = chan
def full_name(self) -> str:
......
experiments/simbricks/orchestration/simulation/host.py
View file @ 0d56918d
......@@ -33,8 +33,6 @@ from simbricks.orchestration.system import host as sys_host
from simbricks.orchestration.system import pcie as sys_pcie
from simbricks.orchestration.system import mem as sys_mem
# if tp.TYPE_CHECKING:
class HostSim(sim_base.Simulator):
......@@ -60,14 +58,16 @@ class HostSim(sim_base.Simulator):
class Gem5Sim(HostSim):
def __init__(self, simulation: sim_base.Simulation):
super().__init__(simulation=simulation, executable="sims/external/gem5/build/X86/gem5")
self.name=f"Gem5Sim-{self._id}"
super().__init__(
simulation=simulation, executable="sims/external/gem5/build/X86/gem5"
)
self.name = f"Gem5Sim-{self._id}"
self.cpu_type_cp = "X86KvmCPU"
self.cpu_type = "TimingSimpleCPU"
self.extra_main_args: list[str] = [] # TODO
self.extra_config_args: list[str] = [] # TODO
self._variant: str = "fast"
self._sys_clock: str = '1GHz' # TODO: move to system module
self._sys_clock: str = "1GHz" # TODO: move to system module
def resreq_cores(self) -> int:
return 1
......@@ -123,45 +123,53 @@ class Gem5Sim(HostSim):
# cmd += f'--command-line-append="{self.node_config.kcmd_append}" '
if inst.create_cp():
cmd += '--max-checkpoints=1 '
cmd += "--max-checkpoints=1 "
if inst.restore_cp():
cmd += '-r 1 '
latency, sync_period, run_sync = sim_base.Simulator.get_unique_latency_period_sync(channels=self.get_channels())
cmd += "-r 1 "
pci_devices = self.filter_components_by_type(ty=sys_pcie.PCIeSimpleDevice)
for dev in pci_devices:
for inf in dev.interfaces():
socket = self._get_socket(inst=inst, interface=inf)
if socket is None:
continue
assert socket._type == inst_base.SockType.CONNECT
cmd += (
f'--simbricks-pci=connect:{socket._path}'
f':latency={latency}ns'
f':sync_interval={sync_period}ns'
latency, sync_period, run_sync = (
sim_base.Simulator.get_unique_latency_period_sync(
channels=self.get_channels()
)
if run_sync:
cmd += ':sync'
cmd += ' '
)
fsh_interfaces = full_sys_hosts[0].interfaces()
mem_devices = self.filter_components_by_type(ty=sys_mem.MemSimpleDevice)
for dev in mem_devices:
for inf in dev.interfaces():
pci_interfaces = system.Interface.filter_by_type(
interfaces=fsh_interfaces, ty=sys_pcie.PCIeHostInterface
)
for inf in pci_interfaces:
socket = self._get_socket(inst=inst, interface=inf)
if socket is None:
continue
assert socket._type == inst_base.SockType.CONNECT
cmd += (
f'--simbricks-mem={dev._size}@{dev._addr}@{dev._as_id}@' # TODO: FIXME
f'connect:{socket._path}'
f':latency={latency}ns'
f':sync_interval={sync_period}ns'
f"--simbricks-pci=connect:{socket._path}"
f":latency={latency}ns"
f":sync_interval={sync_period}ns"
)
if run_sync:
cmd += ':sync'
cmd += ' '
cmd += ":sync"
cmd += " "
# mem_interfaces = system.Interface.filter_by_type(
# interfaces=fsh_interfaces, ty=sys_mem.MemHostInterface
# )
# for inf in mem_interfaces:
# socket = self._get_socket(inst=inst, interface=inf)
# if socket is None:
# continue
# assert socket._type == inst_base.SockType.CONNECT
# cmd += (
# f"--simbricks-mem={dev._size}@{dev._addr}@{dev._as_id}@" # TODO: FIXME
# f"connect:{socket._path}"
# f":latency={latency}ns"
# f":sync_interval={sync_period}ns"
# )
# if run_sync:
# cmd += ":sync"
# cmd += " "
# TODO: FIXME
# for net in self.net_directs:
......@@ -176,7 +184,9 @@ class Gem5Sim(HostSim):
# cmd += ':sync'
# cmd += ' '
cmd += ' '.join(self.extra_config_args)
cmd += " ".join(self.extra_config_args)
print(f"GEM5 COMMAND!!! ===== {cmd}")
return cmd
......
experiments/simbricks/orchestration/simulation/pcidev.py
View file @ 0d56918d
......@@ -80,7 +80,7 @@ class NICSim(PCIDevSim):
cmd += f"{socket._path} "
cmd += (
f" {inst.get_simulator_shm_pool_path(sim=self)} {run_sync} {self._start_tick}"
f" {inst.get_simulator_shm_pool_path(sim=self)} {int(run_sync)} {self._start_tick}"
f" {sync_period} {latency} {latency}"
)
......
experiments/simbricks/orchestration/system/base.py
View file @ 0d56918d
......@@ -89,6 +89,11 @@ class Interface(util_base.IdObj):
peer_if = self.channel.a
return peer_if
T = tp.TypeVar("T")
@staticmethod
def filter_by_type(interfaces: list[Interface], ty: type[T]) -> list[T]:
return list(filter(lambda inf: isinstance(inf, ty), interfaces))
class Channel(util_base.IdObj):
......
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