Commit 01c6f4cb authored by Jialin Li's avatar Jialin Li
Browse files

working iperf

parent 5201df73
...@@ -22,7 +22,7 @@ namespace corundum { ...@@ -22,7 +22,7 @@ namespace corundum {
DescRing::DescRing() DescRing::DescRing()
: _dmaAddr(0), _sizeLog(0), _size(0), _sizeMask(0), : _dmaAddr(0), _sizeLog(0), _size(0), _sizeMask(0),
_index(0), _headPtr(0), _tailPtr(0), _index(0), _headPtr(0), _tailPtr(0),
_currHead(0), _currTail(0), active(false) _currHead(0), _currTail(0), active(false), armed(false)
{ {
} }
...@@ -93,6 +93,9 @@ void ...@@ -93,6 +93,9 @@ void
DescRing::setIndex(unsigned index) DescRing::setIndex(unsigned index)
{ {
assert(!(index & QUEUE_CONT_MASK)); assert(!(index & QUEUE_CONT_MASK));
if (index & QUEUE_ARM_MASK) {
this->armed = true;
}
this->_index = index & 0xFF; this->_index = index & 0xFF;
} }
...@@ -150,9 +153,10 @@ void ...@@ -150,9 +153,10 @@ void
EventRing::issueEvent(unsigned type, unsigned source) EventRing::issueEvent(unsigned type, unsigned source)
{ {
assert(type == EVENT_TYPE_TX_CPL || type == EVENT_TYPE_RX_CPL); assert(type == EVENT_TYPE_TX_CPL || type == EVENT_TYPE_RX_CPL);
if (this->armed) {
if (full()) { if (full()) {
fprintf(stderr, "Event ring is rull\n"); fprintf(stderr, "Event ring is rull\n");
abort(); return;
} }
addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) * EVENT_SIZE; addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) * EVENT_SIZE;
/* Issue DMA write */ /* Issue DMA write */
...@@ -169,6 +173,8 @@ EventRing::issueEvent(unsigned type, unsigned source) ...@@ -169,6 +173,8 @@ EventRing::issueEvent(unsigned type, unsigned source)
event->source = source; event->source = source;
issue_dma_op(op); issue_dma_op(op);
this->_currHead++; this->_currHead++;
this->armed = false;
}
} }
CplRing::CplRing(EventRing *eventRing) CplRing::CplRing(EventRing *eventRing)
...@@ -205,14 +211,17 @@ CplRing::dmaDone(DMAOp *op) ...@@ -205,14 +211,17 @@ CplRing::dmaDone(DMAOp *op)
void void
CplRing::complete(unsigned index, size_t len, bool tx) CplRing::complete(unsigned index, size_t len, bool tx)
{ {
if (full()) { CplData data;
fprintf(stderr, "Completion ring is full\n"); data.index = index;
abort(); data.len = len;
} data.tx = tx;
this->pending.push_back(data);
while (!full() && !this->pending.empty()) {
CplData &data = this->pending.front();
addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) * CPL_SIZE; addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) * CPL_SIZE;
/* Issue DMA write */ /* Issue DMA write */
DMAOp *op = new DMAOp; DMAOp *op = new DMAOp;
op->type = tx ? DMA_TYPE_TX_CPL : DMA_TYPE_RX_CPL; op->type = data.tx ? DMA_TYPE_TX_CPL : DMA_TYPE_RX_CPL;
op->dma_addr = dma_addr; op->dma_addr = dma_addr;
op->len = CPL_SIZE; op->len = CPL_SIZE;
op->ring = this; op->ring = this;
...@@ -220,10 +229,12 @@ CplRing::complete(unsigned index, size_t len, bool tx) ...@@ -220,10 +229,12 @@ CplRing::complete(unsigned index, size_t len, bool tx)
op->write = true; op->write = true;
Cpl *cpl = (Cpl *)op->data; Cpl *cpl = (Cpl *)op->data;
memset(cpl, 0, sizeof(Cpl)); memset(cpl, 0, sizeof(Cpl));
cpl->index = index; cpl->index = data.index;
cpl->len = len; cpl->len = data.len;
this->pending.pop_front();
issue_dma_op(op); issue_dma_op(op);
this->_currHead++; this->_currHead++;
}
} }
TxRing::TxRing(CplRing *cplRing) TxRing::TxRing(CplRing *cplRing)
...@@ -483,10 +494,10 @@ Port::queueDisable() ...@@ -483,10 +494,10 @@ Port::queueDisable()
Corundum::Corundum() Corundum::Corundum()
: txCplRing(&this->eventRing), rxCplRing(&this->eventRing), : txCplRing(&this->eventRing), rxCplRing(&this->eventRing),
txRing(&this->txCplRing), rxRing(&this->rxCplRing) txRing(&this->txCplRing), rxRing(&this->rxCplRing), features(0)
{ {
this->port.setId(0); this->port.setId(0);
this->port.setFeatures(0x711); this->port.setFeatures(this->features);
this->port.setMtu(2048); this->port.setMtu(2048);
this->port.setSchedCount(1); this->port.setSchedCount(1);
this->port.setSchedOffset(0x100000); this->port.setSchedOffset(0x100000);
...@@ -533,7 +544,7 @@ Corundum::readReg(addr_t addr) ...@@ -533,7 +544,7 @@ Corundum::readReg(addr_t addr)
case IF_REG_IF_ID: case IF_REG_IF_ID:
return 0; return 0;
case IF_REG_IF_FEATURES: case IF_REG_IF_FEATURES:
return 0x711; return this->features;
case IF_REG_EVENT_QUEUE_COUNT: case IF_REG_EVENT_QUEUE_COUNT:
return 1; return 1;
case IF_REG_EVENT_QUEUE_OFFSET: case IF_REG_EVENT_QUEUE_OFFSET:
......
#pragma once #pragma once
#include <list>
#include <stdint.h> #include <stdint.h>
typedef uint32_t reg_t; typedef uint32_t reg_t;
...@@ -190,6 +191,7 @@ protected: ...@@ -190,6 +191,7 @@ protected:
ptr_t _currHead; ptr_t _currHead;
ptr_t _currTail; ptr_t _currTail;
bool active; bool active;
bool armed;
}; };
class EventRing : public DescRing { class EventRing : public DescRing {
...@@ -210,7 +212,13 @@ public: ...@@ -210,7 +212,13 @@ public:
void complete(unsigned index, size_t len, bool tx); void complete(unsigned index, size_t len, bool tx);
private: private:
struct CplData {
unsigned index;
size_t len;
bool tx;
};
EventRing *eventRing; EventRing *eventRing;
std::list<CplData> pending;
}; };
class TxRing : public DescRing { class TxRing : public DescRing {
...@@ -293,6 +301,7 @@ private: ...@@ -293,6 +301,7 @@ private:
RxRing rxRing; RxRing rxRing;
CplRing rxCplRing; CplRing rxCplRing;
Port port; Port port;
uint32_t features;
}; };
} // namespace corundum } // namespace corundum
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment