# Copyright 2024 Max Planck Institute for Software Systems, and
# National University of Singapore
#
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#
# The above copyright notice and this permission notice shall be
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from simbricks.orchestration.system import base
from simbricks.orchestration.system import pcie
from simbricks.orchestration.utils import base as utils_base


class EthInterface(base.Interface):
    def __init__(self, c: base.Component) -> None:
        super().__init__(c)

    def connect(self, c: base.Channel) -> None:
        # Note AK: a bit ugly, but I think we can't get around a rt check here
        utils_base.has_expected_type(c, EthChannel)
        super().connect(c)


class EthChannel(base.Channel):
    def __init__(self, a: EthInterface, b: EthInterface) -> None:
        super().__init__(a, b)


class EthSimpleNIC(base.Component):
    def __init__(self, s: base.System) -> None:
        super().__init__(s)
        self._ip = None
        self._eth_if: EthInterface | None = None

    def add_ipv4(self, ip: str) -> None:
        assert self._ip is None
        self.ip = ip

    def add_if(self, interface: EthInterface) -> None:
        utils_base.has_expected_type(obj=interface, expected_type=EthInterface)
        assert self._eth_if is not None
        self._eth_if = interface

class BaseEthNetComponent(base.Component):
    def __init__(self, s: base.System) -> None:
        super().__init__(s)
        self.eth_ifs: EthInterface = []

    def add_if(self, i: EthInterface) -> None:
        self.eth_ifs.append(i)

    def interfaces(self) -> list[EthInterface]:
        return self.eth_ifs


class EthWire(BaseEthNetComponent):
    def __init__(self, s: base.System) -> None:
        super().__init__(s)

    def add_if(self, i: EthInterface) -> None:
        if len(self.eth_ifs) > 2:
            raise Exception("one can only add 2 interfaces to a EthWire")
        self.eth_ifs.append(i)


class EthSwitch(BaseEthNetComponent):
    def __init__(self, s: base.System) -> None:
        super().__init__(s)
