# Copyright 2024 Max Planck Institute for Software Systems, and
# National University of Singapore
#
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# permit persons to whom the Software is furnished to do so, subject to
# the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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from simbricks.orchestration.system import base


class MemHostInterface(base.Interface):
    # Note AK: Component here is on purpose. Other simulators than host
    # simulators can also have MemHost interfaces (e.g. a Mem switch)
    def __init__(self, c: base.Component) -> None:
        super().__init__(c)


class MemDeviceInterface(base.Interface):
    def __init__(self, c: base.Component) -> None:
        super().__init__(c)

    def connect(self, c: base.Channel) -> None:
        # Note AK: a bit ugly, but I think we can't get around a rt check here
        if not c is isinstance(c, MemChannel):
            raise TypeError('MemDeviceInterface only connects to MemChannel')
        super().connect(c)


class MemChannel(base.Channel):
    def __init__(self, host: MemHostInterface, dev: MemDeviceInterface) -> None:
        super().__init__(host, dev)

    def host_if(self) -> MemHostInterface:
        return self.a
    
    def dev_if(self) -> MemDeviceInterface:
        return self.b


class MemSimpleDevice(base.Component):
    def __init__(self, s: base.System):
        super().__init__(s)
        self.mem_if = MemDeviceInterface()

    def interfaces(self) -> list[base.Interface]:
        return [self.mem_if]