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chenpangpang
transformers
Commits
d324b70f
Unverified
Commit
d324b70f
authored
Mar 27, 2023
by
Younes Belkada
Committed by
GitHub
Mar 27, 2023
Browse files
[`bnb`] Force `requires_grad` to be `False` (#22396)
for rg to be `False`
parent
7dcd8703
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src/transformers/utils/bitsandbytes.py
src/transformers/utils/bitsandbytes.py
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src/transformers/utils/bitsandbytes.py
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d324b70f
...
...
@@ -133,6 +133,8 @@ def replace_8bit_linear(model, threshold=6.0, modules_to_not_convert=None, curre
has_fp16_weights
=
False
,
threshold
=
threshold
,
)
# Force requires grad to False to avoid unexpected errors
model
.
_modules
[
name
].
requires_grad_
(
False
)
# Remove the last key for recursion
current_key_name
.
pop
(
-
1
)
return
model
...
...
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