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Unverified Commit 9a220ce3 authored by Bram Vanroy's avatar Bram Vanroy Committed by GitHub
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Clarify 4/8 bit loading log message (#25134) 

* clarify 4/8 bit loading log message

* make style
parent 9429642e
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Showing with 4 additions and 2 deletions
src/transformers/modeling_utils.py
View file @ 9a220ce3
...@@ -2734,8 +2734,10 @@ class PreTrainedModel(nn.Module, ModuleUtilsMixin, GenerationMixin, PushToHubMix ...@@ -2734,8 +2734,10 @@ class PreTrainedModel(nn.Module, ModuleUtilsMixin, GenerationMixin, PushToHubMix
llm_int8_skip_modules = quantization_config.llm_int8_skip_modules llm_int8_skip_modules = quantization_config.llm_int8_skip_modules
load_in_8bit_fp32_cpu_offload = quantization_config.llm_int8_enable_fp32_cpu_offload load_in_8bit_fp32_cpu_offload = quantization_config.llm_int8_enable_fp32_cpu_offload
if load_in_8bit:
logger.info("Detected 8-bit loading: activating 8-bit loading for this model") logger.info("Detected 8-bit loading: activating 8-bit loading for this model")
else:
logger.info("Detected 4-bit loading: activating 4-bit loading for this model")
# We keep some modules such as the lm_head in their original dtype for numerical stability reasons # We keep some modules such as the lm_head in their original dtype for numerical stability reasons
if llm_int8_skip_modules is None: if llm_int8_skip_modules is None:
......
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