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Commit 44cc93c7 authored by qisan's avatar qisan
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Feats: add register pipeline

parent eff4082d
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Inline Side-by-side
Showing with 1398 additions and 319 deletions
examples/gemm/example_gemm.py
View file @ 44cc93c7
import tilelang
import tilelang.language as T
tilelang.disable_cache()
@tilelang.jit(out_idx=[-1])
def matmul(M, N, K, block_M, block_N, block_K, dtype=T.float16, accum_dtype=T.float32):
......@@ -16,7 +17,7 @@ def matmul(M, N, K, block_M, block_N, block_K, dtype=T.float16, accum_dtype=T.fl
C_local = T.alloc_fragment((block_M, block_N), accum_dtype)
T.clear(C_local)
for k in T.Pipelined(T.ceildiv(K, block_K), num_stages=0):
for k in T.Pipelined(T.ceildiv(K, block_K), num_stages=4):
T.copy(A[by * block_M, k * block_K], A_shared)
T.copy(B[k * block_K, bx * block_N], B_shared)
T.gemm(A_shared, B_shared, C_local)
......@@ -27,12 +28,12 @@ def matmul(M, N, K, block_M, block_N, block_K, dtype=T.float16, accum_dtype=T.fl
def main():
kernel = matmul(1024, 1024, 1024, 256, 256, 16)
kernel = matmul(14336, 5120, 5120, 256, 256, 16)
import torch
a = torch.randn(1024, 1024).cuda().half()
b = torch.randn(1024, 1024).cuda().half()
a = torch.randn(14336, 5120).cuda().half()
b = torch.randn(5120, 5120).cuda().half()
c = kernel(a, b)
......@@ -42,13 +43,13 @@ def main():
print(c)
print("ref_c:")
print(ref_c)
torch.testing.assert_close(c, ref_c, rtol=1e-2, atol=1e-2)
print("CUDA Source:")
print(kernel.get_kernel_source())
# torch.testing.assert_close(c, ref_c, rtol=1e-2, atol=1e-2)
print("All check passed.")
# Get CUDA Source
print("CUDA Source:")
print(kernel.get_kernel_source())
# benchmark
profiler = kernel.get_profiler()
......
src/op/builtin.cc
View file @ 44cc93c7
......@@ -397,6 +397,14 @@ TIR_DEFINE_TL_BUILTIN(make_dcu_resource)
.set_num_inputs(2)
.set_attr<TCallEffectKind>("TCallEffectKind",
Integer(CallEffectKind::kOpaque));
TIR_DEFINE_TL_BUILTIN(async_gld_fence)
.set_num_inputs(1)
.set_attr<TCallEffectKind>("TCallEffectKind",
Integer(CallEffectKind::kOpaque));
TIR_DEFINE_TL_BUILTIN(wave_barrier)
.set_num_inputs(0)
.set_attr<TCallEffectKind>("TCallEffectKind",
Integer(CallEffectKind::kOpaque));
} // namespace tl
} // namespace tvm
src/target/codegen_hip.cc
View file @ 44cc93c7
......@@ -574,8 +574,8 @@ void CodeGenTileLangHIP::PrintStorageSync(const CallNode *op) {
if (sync == "warp") {
// DO nothing.
} else if (sync == "shared" || sync == "shared.dyn") {
this->PrintIndent();
this->stream << "__syncthreads();\n";
// this->PrintIndent();
// this->stream << "tl::wave_barrier();\n";
}
}
......@@ -761,7 +761,6 @@ std::string CodeGenTileLangHIP::GetBufferRef(DataType t,
void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
auto print_extern_call_stmt = [&](std::string name, size_t offset = 0) {
printf("[DEBUG VisitExpr_] Branch: print_extern_call_stmt -> %s\n", name.c_str());
this->PrintIndent();
this->stream << name << "(";
for (size_t i = offset; i < op->args.size(); i++) {
......@@ -773,7 +772,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
};
if (op->op.same_as(builtin::ptx_cp_async())) {
printf("[DEBUG VisitExpr_] Branch: ptx_cp_async\n");
std::string dst = this->PrintExpr(op->args[0]);
std::string dst_offset = this->PrintExpr(op->args[1]);
std::string src = this->PrintExpr(op->args[2]);
......@@ -796,42 +794,32 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
;
// print_extern_call_stmt("tl::cp_async_commit");
} else if (op->op.same_as(builtin::ptx_wait_group())) {
printf("[DEBUG VisitExpr_] Branch: ptx_wait_group\n");
int n = Downcast<IntImm>(op->args[0])->value;
std::string func_name = "tl::cp_async_wait<" + std::to_string(n) + ">";
print_extern_call_stmt(func_name, 1);
} else if (op->op.same_as(builtin::create_barriers())) {
printf("[DEBUG VisitExpr_] Branch: create_barriers\n");
this->PrintIndent();
int barrier_count = Downcast<IntImm>(op->args[0])->value;
std::string barrier_name = "_mbarrier";
this->stream << "__shared__ uint64_t " << barrier_name << "["
<< barrier_count << "];\n";
} else if (op->op.same_as(tl::get_mbarrier())) {
printf("[DEBUG VisitExpr_] Branch: get_mbarrier\n");
std::string barrier_name = "_mbarrier";
std::string barrier_id = this->PrintExpr(op->args[0]);
os << barrier_name + "[" + barrier_id + "]";
} else if (op->op.same_as(builtin::ptx_arrive_barrier())) {
printf("[DEBUG VisitExpr_] Branch: ptx_arrive_barrier\n");
print_extern_call_stmt("tl::mbarrier_arrive");
} else if (op->op.same_as(builtin::ptx_init_barrier_thread_count())) {
printf("[DEBUG VisitExpr_] Branch: ptx_init_barrier_thread_count\n");
print_extern_call_stmt("tl::mbarrier_init");
} else if (op->op.same_as(builtin::ptx_arrive_barrier_expect_tx())) {
printf("[DEBUG VisitExpr_] Branch: ptx_arrive_barrier_expect_tx\n");
print_extern_call_stmt("tl::mbarrier_arrive_expect_tx");
} else if (op->op.same_as(builtin::ptx_cp_async_barrier())) {
printf("[DEBUG VisitExpr_] Branch: ptx_cp_async_barrier\n");
print_extern_call_stmt("tl::mbarrier_cp_async_arrive");
} else if (op->op.same_as(tl::mbarrier_expect_tx())) {
printf("[DEBUG VisitExpr_] Branch: mbarrier_expect_tx\n");
print_extern_call_stmt("tl::mbarrier_expect_tx");
} else if (op->op.same_as(tl::mbarrier_wait_parity())) {
printf("[DEBUG VisitExpr_] Branch: mbarrier_wait_parity\n");
print_extern_call_stmt("tl::mbarrier_wait");
} else if (op->op.same_as(tl::ptx_stmatrix())) {
printf("[DEBUG VisitExpr_] Branch: ptx_stmatrix\n");
int trans = Downcast<IntImm>(op->args[0])->value;
int num = Downcast<IntImm>(op->args[1])->value;
std::string func_name = "tl::ptx_stmatrix_x" + std::to_string(num);
......@@ -839,8 +827,8 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
func_name += "_trans";
print_extern_call_stmt(func_name, 2);
}else if(op->op.same_as(tl::ds_read_vector())){
// ds_read_m32x16_b16 %0, %1 offset:0
printf("[DEBUG VisitExpr_] Branch: ds_read_vector\n");
//ds_read_b64 %1, %2 offset:%3
// ds_read_m32x16_b16 %0, %1 offset:%2
std::string dst = this->PrintExpr(op->args[0]);
std::string local_offset = this->PrintExpr(op->args[1]);
std::string lds_offset = this->PrintExpr(op->args[2]);
......@@ -850,16 +838,13 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
<< lds_offset
<< ")";
}else if (op->op.same_as(tl::wait_wgmma())) {
printf("[DEBUG VisitExpr_] Branch: wait_wgmma\n");
this->PrintIndent();
int num_mma = Downcast<IntImm>(op->args[0])->value;
this->stream << "tl::wait_wgmma<" << std::to_string(num_mma) << ">();\n";
} else if (op->op.same_as(tl::pack_b16())) {
printf("[DEBUG VisitExpr_] Branch: pack_b16\n");
os << "__pack_half2(" << this->PrintExpr(op->args[0]) << ", "
<< this->PrintExpr(op->args[1]) << ")";
} else if (op->op.same_as(tl::__ldg())) {
printf("[DEBUG VisitExpr_] Branch: __ldg\n");
// HIP fallback: regular load
const BufferLoadNode *bl = op->args[0].as<BufferLoadNode>();
ICHECK(bl) << "T.__ldg expects a BufferLoad as the first argument.";
......@@ -870,7 +855,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
auto buffer_ref = this->GetBufferRef(op->dtype, buffer, base);
os << buffer_ref;
} else if (op->op.same_as(builtin::tvm_fill_fragment())) {
printf("[DEBUG VisitExpr_] Branch: tvm_fill_fragment\n");
need_mma_h_ = true;
ICHECK_EQ(op->args.size(), 6U);
os << "nvcuda::wmma::fill_fragment(";
......@@ -881,7 +865,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
this->PrintExpr(op->args[5], os);
os << ")";
} else if (op->op.same_as(builtin::tvm_load_matrix_sync())) {
printf("[DEBUG VisitExpr_] Branch: tvm_load_matrix_sync\n");
need_mma_h_ = true;
ICHECK_EQ(op->args.size(), 8U);
os << "nvcuda::wmma::load_matrix_sync(";
......@@ -894,7 +877,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
this->PrintExpr(op->args[6], os);
os << ")";
} else if (op->op.same_as(builtin::tvm_store_matrix_sync())) {
printf("[DEBUG VisitExpr_] Branch: tvm_store_matrix_sync\n");
need_mma_h_ = true;
ICHECK_EQ(op->args.size(), 8U);
os << "nvcuda::wmma::store_matrix_sync(";
......@@ -912,7 +894,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
}
os << ")";
} else if (op->op.same_as(builtin::tvm_mma_sync())) {
printf("[DEBUG VisitExpr_] Branch: tvm_mma_sync\n");
need_mma_h_ = true;
ICHECK_EQ(op->args.size(), 8U);
os << "nvcuda::wmma::mma_sync(";
......@@ -923,7 +904,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
os << "]" << ((i < 3) ? ", " : ")");
}
} else if (op->op.same_as(builtin::tvm_bmma_sync())) {
printf("[DEBUG VisitExpr_] Branch: tvm_bmma_sync\n");
need_mma_h_ = true;
ICHECK_EQ(op->args.size(), 8U);
os << "nvcuda::wmma::bmma_sync(";
......@@ -934,7 +914,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
os << "]" << ((i < 3) ? ", " : ")");
}
} else if (op->op.same_as(tl::tvm_mfma())) {
printf("[DEBUG VisitExpr_] Branch: tvm_mfma\n");
// arg 0: prefix: {otype}_{intrM}x{intrN}x{intrK}_{itype}
// arg 1: A layout: row/col
// arg 2: B layout: row/col
......@@ -1000,7 +979,6 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
replacer.register_rule("{c_bias}", c_bias);
os << replacer.rewrite(call_mfma_code);
} else if (op->op.same_as(tl::tvm_mmac())) {
printf("[DEBUG VisitExpr_] Branch: tvm_mmac\n");
// arg 0: prefix: {otype}_{intrM}x{intrN}x{intrK}_{itype}
// arg 1: A layout: row/col
// arg 2: B layout: row/col
......@@ -1066,10 +1044,8 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
replacer.register_rule("{c_bias}", c_bias);
os << replacer.rewrite(call_mmac_code);
} else if (op->op.same_as(builtin::thread_return())) {
printf("[DEBUG VisitExpr_] Branch: thread_return\n");
os << "return";
} else if (op->op.same_as(tl::tl_gemm())) {
printf("[DEBUG VisitExpr_] Branch: tl_gemm\n");
ICHECK(op->args.size() == 4) << "tl_gemm expects 4 arguments <op_instance, "
"A_ptr, B_ptr, C_ptr>, but got "
<< op->args.size();
......@@ -1077,14 +1053,11 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
this->PrintCallExtern(GetType(tvm::ffi::GetRef<PrimExpr>(op)),
op_instance->value, op->args, true, os);
} else if (op->op.same_as(tl::tl_gemm_sp())) {
printf("[DEBUG VisitExpr_] Branch: tl_gemm_sp\n");
LOG(FATAL) << "tl_gemm_sp is not supported on HIP";
} else if (op->op.same_as(tl::loop_break())) {
printf("[DEBUG VisitExpr_] Branch: loop_break\n");
this->PrintIndent();
this->stream << "break;\n";
} else if (op->op.same_as(tl::no_set_max_nreg())) {
printf("[DEBUG VisitExpr_] Branch: no_set_max_nreg\n");
// HIP doesn't need explicit register management like CUDA
// This is a no-op for HIP
return;
......@@ -1102,54 +1075,37 @@ void CodeGenTileLangHIP::VisitExpr_(const CallNode *op, std::ostream &os) {
}
else if (op->op.same_as(Op::Get("tl.dcu_async_copy"))) {
auto get_base_expr = [this](const PrimExpr& e) -> std::string {
if (const auto* ramp = e.as<tvm::tir::RampNode>()) {
// 如果是 Ramp，只打印它的起始位置 (base)
return this->PrintExpr(ramp->base);
}
// 否则正常打印
return this->PrintExpr(e);
};
// 辅助函数：尝试获取整数常量
if (const auto* ramp = e.as<tvm::tir::RampNode>()) {
return this->PrintExpr(ramp->base);
}
return this->PrintExpr(e);
};
auto get_int_const = [](const PrimExpr& e) -> int {
if (const auto* val = e.as<IntImmNode>()) return static_cast<int>(val->value);
return 0;
};
// 1. 静态模板参数 (按要求仅保留 N 和 smem_offset)
int N = 16;
// 2. 解析 IR 参数
// args[0]: dst_ptr (buf_dyn_shmem)
// args[1]: dst_ramp (T.Ramp...)
// args[2]: src_res (A_dcu_res)
// args[3]: src_ramp (T.Ramp...)
// args[4]: load_count (1)
std::string dst_ptr = this->PrintExpr(op->args[0]);
// 使用新定义的 get_base_expr 避开 lanes > 4 的检查
std::string dst_off = get_base_expr(op->args[1]);
std::string src_res = this->PrintExpr(op->args[2]);
std::string src_off = get_base_expr(op->args[3]);
// 3. 生成输出流
int N = 16;
std::string dst_ptr = this->PrintExpr(op->args[0]);
std::string dst_off = get_base_expr(op->args[1]);
std::string src_res = this->PrintExpr(op->args[2]);
std::string src_off = get_base_expr(op->args[3]);
this->PrintIndent();
// 模板参数仅保留 N, smem_offset 和动态提取的 load_count
this->stream << "tl::cp_async_gs<"
<< N << ">(";
// 打印函数参数
// 处理目标地址: ((char*)ptr + offset)
this->stream << "((char*)" << dst_ptr << " + " << dst_off << "), ";
// 打印源资源指针
this->stream << "((half_t*)" << dst_ptr << " + " << dst_off << "), ";
this->stream << src_res << ", ";
// 打印源偏移
this->stream << src_off << ");\n";
}
this->stream << src_off << " * sizeof(half_t));\n";
}
else if (op->op.same_as(Op::Get("tl.async_gld_fence"))) {
int fence_num = Downcast<IntImm>(op->args[0])->value;
this->PrintIndent();
this->stream << "tl::async_gld_fence(" << fence_num << ");\n";
} else if (op->op.same_as(Op::Get("tl.wave_barrier"))) {
this->PrintIndent();
this->stream << "tl::wave_barrier();\n";
}
else {
printf("[DEBUG VisitExpr_] Branch: CodeGenC::VisitExpr_ (fallback)\n");
CodeGenC::VisitExpr_(op, os);
}
}
......
src/tl_templates/dcu_hip/copy.h
View file @ 44cc93c7
......@@ -18,6 +18,7 @@ struct __attribute__((packed)) buffer_resource {
uint32_t range;
uint32_t config;
};
# define CK_TILE_BUFFER_RESOURCE_3RD_DWORD 0x00020000
CK_TILE_DEVICE int32x4_t make_wave_buffer_resource(const void *ptr,
uint32_t size = 0xffffffff) {
......@@ -86,83 +87,39 @@ CK_TILE_DEVICE void async_buffer_load_dword_v(void *smem, int32x4_t rsrc,
: "memory");
}
template <int N, int smem_offset, int load_count, int i_sstride, int i_gstride, int k_gstride>
template <int smem_offset =0, bool pre_nop = false>
CK_TILE_DEVICE void async_buffer_load_dwordx4_v(void *smem, int32x4_t rsrc,
index_t voffset) {
auto const lds_ptr_sgpr =
__builtin_amdgcn_readfirstlane((reinterpret_cast<uintptr_t>(smem)));
asm volatile("s_add_u32 m0, %0, %3 \n\t"
"buffer_load_dwordx4 %1, %2, 0, offen offset:0, lds\n\t" ::"s"(lds_ptr_sgpr),
"v"(voffset), "s"(rsrc), "n"(smem_offset)
: "memory");
}
template <int N>
TL_DEVICE void cp_async_gs(void *lds_base_ptr, int32x4_t res, int offset) {
if constexpr (N == 16) {
if constexpr (load_count == 1){
async_buffer_load_dwordx4_v<smem_offset>(
lds_base_ptr,
res,
offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, k_gstride);
}
else if constexpr (load_count == 2){
async_buffer_load_dwordx4_v<smem_offset>(
lds_base_ptr,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, i_gstride);
async_buffer_load_dwordx4_v<smem_offset + i_sstride>(
lds_base_ptr,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, k_gstride - i_gstride);
}
else if constexpr (load_count == 4){
async_buffer_load_dwordx4_v<smem_offset>(
lds_base_ptr,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, i_gstride);
async_buffer_load_dwordx4_v<smem_offset + i_sstride>(
lds_base_ptr,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, i_gstride);
async_buffer_load_dwordx4_v<smem_offset + 2 * i_sstride>(
lds_base_ptr,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, i_gstride);
async_buffer_load_dwordx4_v<smem_offset + 3 * i_sstride>(
lds_base_ptr,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, k_gstride - 3 * i_gstride);
}
else {
#pragma unroll
for (int i = 0; i < load_count - 1; ++i) {
async_buffer_load_dwordx4_v<smem_offset>(
lds_base_ptr + i * i_sstride,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, i_gstride);
}
async_buffer_load_dwordx4_v<smem_offset>(
lds_base_ptr + (load_count - 1) * i_sstride,
res,
current_offset
);
UPDATE_WAVE_BUFFER_RESOURCE(res, k_gstride - (load_count - 1) * i_gstride);
}
}
else {
not implemented;
async_buffer_load_dwordx4_v(
lds_base_ptr,
res,
offset
);
}
}
TL_DEVICE int32x4_t make_wave_buffer_resource(const void *ptr,
uint32_t size = 0xffffffff) {
buffer_resource res{ptr, size, CK_TILE_BUFFER_RESOURCE_3RD_DWORD};
int32x4_t r = __builtin_bit_cast(int32x4_t, res);
r.x = __builtin_amdgcn_readfirstlane(r.x);
r.y = __builtin_amdgcn_readfirstlane(r.y);
r.z = __builtin_amdgcn_readfirstlane(r.z);
r.w = __builtin_amdgcn_readfirstlane(r.w);
return r;
}
template <int N>
// TL_DEVICE void cp_async_gs(void *lds_base_ptr, void *global_base_ptr) {
// if constexpr (N == 16) {
// *(uint4 *)lds_base_ptr = *(uint4 *)global_base_ptr;
......
src/transform/dcu_async_copy_pipeline.cc
View file @ 44cc93c7
#include <tvm/tir/stmt_functor.h>
#include <tvm/tir/transform.h>
#include <tvm/arith/analyzer.h>
#include <tvm/tir/op.h>
#include <tvm/tir/builtin.h>
#include <tvm/tir/analysis.h>
using namespace tvm::tir;
#include <tvm/tir/stmt.h>
#include <algorithm>
using namespace tvm::tir;
using tvm::ffi::GetRef;
using tvm::ffi::make_object;
namespace tvm {
namespace tl {
using namespace tir;
using ffi::Array;
using ffi::String;
class ROCmWaitCountRewriter : public StmtMutator {
public:
static Stmt Substitute(Stmt stmt) {
return ROCmWaitCountRewriter()(stmt);
}
private:
// 辅助函数：统计一个代码块内 async 指令的总数
int CountAsyncOps(const Stmt& stmt) {
int total_count = 0;
/**
* @brief 分析器：计算 Stmt 内部的 async 指令贡献
* 注意：这里计算的是“静态进入一次该 Stmt 后产生的指令总数”
*/
class AsyncCountAnalyzer : public StmtExprVisitor {
public:
static int64_t Analyze(const Stmt& stmt) {
AsyncCountAnalyzer analyzer;
analyzer.VisitStmt(stmt);
return analyzer.count_;
}
struct Visitor : public StmtExprVisitor {
int count = 0;
void VisitStmt_(const ForNode* op) override {
// 如果内部还有循环（比如 T.unroll），需要乘上循环次数
int current_count = count;
count = 0;
StmtExprVisitor::VisitStmt_(op);
private:
void VisitStmt_(const ForNode* op) override {
// 如果遇到了嵌套循环，需要计算：子循环内部单次产生的量 * 子循环次数
int64_t sub_loop_body_count = Analyze(op->body);
int loop_count = 0;
if (const auto* extent = op->extent.as<IntImmNode>()) {
loop_count = static_cast<int>(extent->value);
} else {
// 如果是非固定长度循环，这在流水线中很少见，默认按1处理或报警
loop_count = 1;
int64_t extent = 1;
if (auto e = op->extent.as<IntImmNode>()) {
extent = e->value;
}
int body_count = count;
count = current_count + (body_count * loop_count);
}
count_ += sub_loop_body_count * extent;
// 停止递归，因为 Analyze(op->body) 已经处理完了
}
void VisitExpr_(const CallNode* op) override {
// 识别 ptx_cp_async 或对应的异步访存 Op
if (op->op.same_as(builtin::ptx_cp_async()) ||
op->op.same_as(Op::Get("tl.dcu_async_copy"))) {
LOG(INFO) << "Found async copy: " << GetRef<Call>(op);
count++;
void VisitExpr_(const CallNode* op) override {
bool is_async = op->op.same_as(Op::Get("tl.dcu_async_copy")) ||
op->op.same_as(builtin::ptx_cp_async());
if (is_async) {
count_++;
}
StmtExprVisitor::VisitExpr_(op);
}
// 兼容某些实现中把 cp_async 放在 Evaluate 里的情况
void VisitStmt_(const EvaluateNode* op) override {
StmtExprVisitor::VisitStmt_(op);
}
} visitor;
visitor(stmt);
return visitor.count;
}
Stmt VisitStmt_(const ForNode* op) override {
// 1. 我们假设流水线的主循环是核心作用域
// 先扫描该循环体内部每一轮会发出多少个 async 操作
int ops_per_iter = CountAsyncOps(op->body);
}
// 如果没有异步操作，直接跳过
if (ops_per_iter == 0) return StmtMutator::VisitStmt_(op);
int64_t count_ = 0;
};
// 2. 进入循环内部进行修改，记录当前的倍数
int old_multiplier = multiplier_;
multiplier_ = ops_per_iter;
Stmt new_body = this->VisitStmt(op->body);
multiplier_ = old_multiplier;
/**
* @brief 寻找循环体内部倍率的最大值
*/
class GlobalMaxAsyncFinder : public StmtVisitor {
public:
static int64_t FindMax(const Stmt& stmt) {
GlobalMaxAsyncFinder finder;
finder.VisitStmt(stmt);
return std::max(static_cast<int64_t>(1), finder.max_multiplier_);
}
if (new_body.same_as(op->body)) return GetRef<Stmt>(op);
auto n = CopyOnWrite(op);
n->body = std::move(new_body);
return Stmt(n);
}
private:
void VisitStmt_(const ForNode* op) override {
// 【关键修正】：我们只分析循环的 Body 产生的 async 数量
// 这样对于最外层的 for k，得到的结果就是它 body 里的 2 个 async
int64_t inner_count = AsyncCountAnalyzer::Analyze(op->body);
if (inner_count > max_multiplier_) {
max_multiplier_ = inner_count;
}
// 继续向下递归，检查是否有更深层的循环内部产生了更多指令
StmtVisitor::VisitStmt_(op);
}
Stmt VisitStmt_(const AttrStmtNode* op) override {
if (op->attr_key == "async_wait_inflight_count" && multiplier_ > 0) {
// 获取原有的 wait 组数 (比如 1)
if (auto int_imm = op->value.as<IntImmNode>()) {
// 计算 ROCm 的指令数: N_groups * Ops_per_group
int64_t new_cont = int_imm->value * multiplier_;
int64_t max_multiplier_ = 0;
};
LOG(INFO) << "Original wait count: " << new_cont << ", async ops per iter: " << multiplier_;
// 返回修改后的节点
return AttrStmt(op->node, op->attr_key, make_const(DataType::Int(32), new_cont), op->body);
}
class ROCmWaitCountRewriter : public StmtMutator {
public:
static Stmt Substitute(const Stmt& stmt) {
int64_t max_mult = GlobalMaxAsyncFinder::FindMax(stmt);
ROCmWaitCountRewriter rewriter(max_mult);
return rewriter(stmt);
}
return StmtMutator::VisitStmt_(op);
}
int multiplier_ = 0; // 当前作用域下的指令倍率
private:
explicit ROCmWaitCountRewriter(int64_t mult) : global_max_mult_(mult) {}
Stmt VisitStmt_(const AttrStmtNode* op) override {
if (op->attr_key == tir::attr::async_wait_inflight_count ||
op->attr_key == "async_wait_inflight_count") {
if (auto int_imm = op->value.as<IntImmNode>()) {
int64_t new_val = int_imm->value * global_max_mult_;
return AttrStmt(op->node, op->attr_key, make_const(DataType::Int(32), new_val),
this->VisitStmt(op->body));
}
}
return StmtMutator::VisitStmt_(op);
}
int64_t global_max_mult_;
};
// 包装成标准的 TVM Pass
// Pass 包装省略 (同前)
namespace transform {
using namespace tir::transform;
tvm::transform::Pass FixDCUWaitCount() {
auto pass_func = [=](PrimFunc f, IRModule m, PassContext ctx) {
auto* n = f.CopyOnWrite();
......@@ -119,9 +114,9 @@ tvm::transform::Pass FixDCUWaitCount() {
return CreatePrimFuncPass(pass_func, 0, "FixDCUWaitCount", {});
}
TVM_FFI_STATIC_INIT_BLOCK() {
tvm::ffi::reflection::GlobalDef().def("tl.transform.FixDCUWaitCount", FixDCUWaitCount);
tvm::ffi::reflection::GlobalDef().def("tl.transform.FixDCUWaitCount", FixDCUWaitCount);
}
}
} // namespace transform
} // namespace tl
} // namespace tvm
\ No newline at end of file
src/transform/inject_mmac_fence.cc 0 → 100644
View file @ 44cc93c7
#include <tvm/tir/stmt_functor.h>
#include <tvm/tir/transform.h>
#include <tvm/tir/op.h>
#include <tvm/tir/builtin.h>
#include <tvm/tir/expr_functor.h>
#include <tvm/arith/analyzer.h>
#include <string>
#include <vector>
namespace tvm {
namespace tl {
using ffi::Array;
using namespace tir;
// 1. 辅助类：统计 Shared -> Register 的加载量
class LoadCounter : public StmtExprVisitor {
public:
int total_loads = 0;
int current_multiplier = 1;
void VisitStmt_(const ForNode* op) override {
int64_t extent = 1;
if (auto imm = op->extent.as<IntImmNode>()) {
extent = imm->value;
}
int prev_multiplier = current_multiplier;
current_multiplier *= static_cast<int>(extent);
StmtVisitor::VisitStmt_(op);
current_multiplier = prev_multiplier;
}
void VisitExpr_(const BufferLoadNode* op) override {
std::string scope = op->buffer.scope();
std::string name = op->buffer->name;
if (scope == "shared" || name.find("shared") != std::string::npos ||
name.find("shmem") != std::string::npos) {
total_loads += current_multiplier;
}
ExprVisitor::VisitExpr_(op);
}
};
// 2. 核心 Mutator
class MMABarrierMutator : public StmtExprMutator {
public:
bool ContainsMMA(const Stmt& stmt) {
bool found = false;
PostOrderVisit(stmt, [&found](const ObjectRef& node) {
if (const CallNode* call = node.as<CallNode>()) {
std::string op_name = "";
if (const OpNode* op = call->op.as<OpNode>()) {
op_name = op->name;
} else if (const GlobalVarNode* gv = call->op.as<GlobalVarNode>()) {
op_name = gv->name_hint;
}
if (op_name.find("mmac") != std::string::npos ||
op_name.find("mma") != std::string::npos) {
found = true;
}
}
});
return found;
}
Stmt VisitStmt_(const SeqStmtNode* op) override {
// --- 步骤 1: 预扫描，确定最后一个需要插入 Fence 的位置 ---
int last_fence_idx = -1;
int temp_pending_count = 0;
for (size_t i = 0; i < op->seq.size(); ++i) {
if (ContainsMMA(op->seq[i])) {
if (temp_pending_count > 0) {
last_fence_idx = static_cast<int>(i);
temp_pending_count = 0; // 模拟重置
}
} else {
LoadCounter counter;
counter(op->seq[i]);
temp_pending_count += counter.total_loads;
}
}
// --- 步骤 2: 实际构造新的 Sequence ---
Array<Stmt> new_seq;
int pending_load_count = 0;
for (size_t i = 0; i < op->seq.size(); ++i) {
const auto& stmt = op->seq[i];
if (ContainsMMA(stmt)) {
if (pending_load_count > 0) {
// 判断是否是该序列中最后一个 Fence
int fence_val = (static_cast<int>(i) == last_fence_idx) ? 0 : pending_load_count;
Array<PrimExpr> args = {Integer(fence_val)};
// 构造 Fence
auto fence_call = Call(DataType::Void(), Op::Get("tl.async_gld_fence"), args);
new_seq.push_back(Evaluate(fence_call));
// 构造 Barrier
auto barrier_call = Call(DataType::Void(), Op::Get("tl.wave_barrier"), {});
new_seq.push_back(Evaluate(barrier_call));
pending_load_count = 0;
}
new_seq.push_back(this->VisitStmt(stmt));
} else {
LoadCounter counter;
counter(stmt);
pending_load_count += counter.total_loads;
new_seq.push_back(this->VisitStmt(stmt));
}
}
return SeqStmt(new_seq);
}
};
// 3. Pass 包装
namespace transform {
using namespace tir::transform;
Pass InsertAsyncMMAFence() {
auto pass_func = [](PrimFunc f, IRModule m, PassContext ctx) {
auto* n = f.CopyOnWrite();
MMABarrierMutator mutator;
n->body = mutator(n->body);
return f;
};
return CreatePrimFuncPass(pass_func, 0, "tl.InsertAsyncMMAFence", {});
}
TVM_FFI_STATIC_INIT_BLOCK() {
namespace refl = tvm::ffi::reflection;
refl::GlobalDef().def("tl.transform.InsertAsyncMMAFence", InsertAsyncMMAFence);
}
} // namespace transform
} // namespace tl
} // namespace tvm
\ No newline at end of file
src/transform/inject_pipeline.cc
View file @ 44cc93c7
......@@ -3,14 +3,23 @@
* \brief Transform annotated loops into pipelined one that parallelize
* producers and consumers
*/
#include <tvm/ir/type.h>
#include <tvm/target/target.h>
#include <tvm/tir/builtin.h>
#include <tvm/tir/buffer.h>
#include <tvm/tir/op.h>
#include <tvm/tir/transform.h>
#include <tvm/node/structural_equal.h>
#include <algorithm>
#include <functional>
#include <optional>
#include <string>
#include <unordered_set>
#include <utility>
#include "../op/builtin.h"
#include "support/utils.h"
#include "tir/schedule/utils.h"
#include "tir/transforms/ir_utils.h"
......@@ -21,6 +30,108 @@ using namespace tir;
using namespace ffi;
namespace software_pipeline {
/*! \brief Same notion of "local" register memory as register_pipeline_planning. */
inline bool IsRegisterPipelineLocalScope(const ffi::String &scope) {
static constexpr const char *kLocal = "local";
constexpr size_t kLocalLen = 5;
std::string s = scope;
return s == kLocal || (s.size() > kLocalLen && s.compare(0, kLocalLen, kLocal) == 0 &&
s[kLocalLen] == '.');
}
inline bool IsRegisterPipelineLocalBuffer(const Buffer &buffer) {
return IsRegisterPipelineLocalScope(buffer.scope());
}
/*! \brief Shared-memory tensors versioned by software_pipeline_stage skew. */
inline bool IsSharedPipelineBufferScope(const ffi::String &scope) {
static constexpr const char *kShared = "shared";
constexpr size_t kSharedLen = 6;
std::string s = scope;
return s == kShared || (s.size() > kSharedLen && s.compare(0, kSharedLen, kShared) == 0 &&
s[kSharedLen] == '.');
}
inline bool IsSharedPipelineBuffer(const Buffer &buffer) {
return IsSharedPipelineBufferScope(buffer.scope());
}
inline ffi::String GetAllocateStorageScope(const AllocateNode *op) {
if (auto *ptr_type = op->buffer_var->type_annotation.as<PointerTypeNode>()) {
if (!ptr_type->storage_scope.empty()) {
return ptr_type->storage_scope;
}
}
return ffi::String("global");
}
/*!
* \brief Collect local buffers declared inside the pipeline body (Allocate /
* DeclBuffer / inner Block alloc_buffers). Outer BlockRealize lists are
* merged separately — nested locals are often missing there, which used
* to leave register pipelines with a single physical buffer.
*/
class RegisterPipelineBufferCollector : public StmtExprVisitor {
public:
explicit RegisterPipelineBufferCollector(Array<Buffer> *pipeline_allocs,
Map<Var, Buffer> *buffer_map)
: pipeline_allocs_(pipeline_allocs), buffer_map_(buffer_map) {
ICHECK(pipeline_allocs_ != nullptr);
ICHECK(buffer_map_ != nullptr);
for (const Buffer &b : *pipeline_allocs_) {
seen_data_.insert(b->data);
}
}
private:
void TryAdd(const Buffer &buf) {
if (!IsRegisterPipelineLocalBuffer(buf)) {
return;
}
if (seen_data_.count(buf->data)) {
return;
}
seen_data_.insert(buf->data);
pipeline_allocs_->push_back(buf);
buffer_map_->Set(buf->data, buf);
}
void VisitStmt_(const AllocateNode *op) final {
if (!IsRegisterPipelineLocalScope(GetAllocateStorageScope(op))) {
StmtExprVisitor::VisitStmt_(op);
return;
}
std::optional<Buffer> existing = buffer_map_->Get(op->buffer_var);
if (existing.has_value()) {
TryAdd(existing.value());
} else {
Buffer reconstructed(
op->buffer_var, op->dtype, op->extents, ffi::Array<PrimExpr>(),
PrimExpr(), op->buffer_var->name_hint, 0, 0, BufferType::kDefault,
ffi::Array<IntImm>(), Span());
TryAdd(reconstructed);
}
StmtExprVisitor::VisitStmt_(op);
}
void VisitStmt_(const DeclBufferNode *op) final {
TryAdd(op->buffer);
StmtExprVisitor::VisitStmt_(op);
}
void VisitStmt_(const BlockNode *op) final {
for (const Buffer &b : op->alloc_buffers) {
TryAdd(b);
}
StmtExprVisitor::VisitStmt_(op);
}
Array<Buffer> *pipeline_allocs_{nullptr};
Map<Var, Buffer> *buffer_map_{nullptr};
/*! ObjectPtrHash/Equal apply to ObjectRef keys (Var), not raw VarNode*. */
std::unordered_set<Var, ObjectPtrHash, ObjectPtrEqual> seen_data_;
};
struct LetWrapper {
Var var;
PrimExpr value;
......@@ -98,12 +209,25 @@ public:
access_all_versions_(access_all_versions) {}
private:
/*! Same allocation may appear as different Buffer handles; remap key is by Var. */
std::optional<Buffer> LookupVersionedBuffer(const Buffer &buf) const {
if (auto got = buffer_remap_.Get(buf)) {
return *got;
}
for (const auto &kv : buffer_remap_) {
if (kv.first->data.same_as(buf->data)) {
return kv.second;
}
}
return std::nullopt;
}
BufferRegion
RewritePipelineBufferRegion(const BufferRegion &buffer_region) const {
auto it = buffer_remap_.find(buffer_region->buffer);
if (it != buffer_remap_.end()) {
auto ob = LookupVersionedBuffer(buffer_region->buffer);
if (ob.has_value()) {
Region new_region = buffer_region->region;
const Buffer &new_buffer = (*it).second;
const Buffer &new_buffer = ob.value();
// For pipeline buffers, relax the access region of the first dimension to
// full extent if access_all_versions == true
Range accessed_version =
......@@ -132,9 +256,9 @@ private:
for (int i : arg_indices) {
const Buffer &buffer =
buffer_data_to_buffer_.at(Downcast<Var>(call->args[i]));
auto it = buffer_remap_.find(buffer);
if (it != buffer_remap_.end()) {
const Buffer &new_buffer = (*it).second;
auto ob = LookupVersionedBuffer(buffer);
if (ob.has_value()) {
const Buffer &new_buffer = ob.value();
const PrimExpr &old_index = call->args[i + 1];
PrimExpr offset;
if (new_buffer->strides.empty()) {
......@@ -148,7 +272,6 @@ private:
new_args.Set(i + 1, new_index);
}
}
LOG(INFO) << "Rewriting buffer access " << call << " to " << Call(call->dtype, call->op, new_args, call->span);
return Call(call->dtype, call->op, new_args, call->span);
}
......@@ -167,17 +290,16 @@ private:
for (const Buffer &alloc_buffer : op->alloc_buffers) {
buffer_data_to_buffer_.erase(alloc_buffer->data);
}
LOG(INFO) << "Rewriting block " << GetRef<Block>(op) << " to " << GetRef<Block>(n);
return block;
}
Stmt VisitStmt_(const BufferStoreNode *op) final {
BufferStore store = Downcast<BufferStore>(StmtExprMutator::VisitStmt_(op));
auto it = buffer_remap_.find(store->buffer);
if (it == buffer_remap_.end()) {
auto ob = LookupVersionedBuffer(store->buffer);
if (!ob.has_value()) {
return store;
}
const Buffer &new_buffer = (*it).second;
const Buffer &new_buffer = ob.value();
auto *n = store.CopyOnWrite();
n->buffer = new_buffer;
PrimExpr version = floormod(
......@@ -188,11 +310,11 @@ private:
PrimExpr VisitExpr_(const BufferLoadNode *op) final {
BufferLoad load = Downcast<BufferLoad>(StmtExprMutator::VisitExpr_(op));
auto it = buffer_remap_.find(load->buffer);
if (it == buffer_remap_.end()) {
auto ob = LookupVersionedBuffer(load->buffer);
if (!ob.has_value()) {
return load;
}
const Buffer &new_buffer = (*it).second;
const Buffer &new_buffer = ob.value();
auto *n = load.CopyOnWrite();
n->buffer = new_buffer;
PrimExpr version = floormod(
......@@ -206,6 +328,16 @@ private:
if (call->op.same_as(builtin::tvm_access_ptr())) {
return RewriteBufferAccess(call, {1});
}
// tl.tvm_mmac / tvm_mfma / tvm_rdna_wmma: same layout as codegen — args
// 6,8,10 are A/B/C buffer handles, 7,9,11 are element offsets (see
// codegen_hip.cc). Pipeline versioning must apply here too, otherwise MMA
// keeps unversioned .data + bias while BufferLoad/Store use ping-pong.
if (call->op.same_as(tvm_mmac()) || call->op.same_as(tvm_mfma()) ||
call->op.same_as(tvm_rdna_wmma())) {
ICHECK_EQ(call->args.size(), 12U)
<< "tl MMA builtins expect 12 arguments for pipeline rewrite";
return RewriteBufferAccess(call, {6, 8, 10});
}
return call;
}
......@@ -221,24 +353,146 @@ private:
*/
class PipelineRewriter : public StmtExprMutator {
public:
/*!
* \param register_pipeline_min_versions For tl_register_pipeline_stage only:
* minimum physical banks per local buffer (from loop annotation
* `num_register_stages`, default 2). Same role as multi-buffering
* shared tensors — ping-pong groups selected via floormod(k, N).
* \param shared_buffer_version_pipeline When non-null (register pipeline
* injection only): use these software_pipeline_stage values — expanded
* to the same fine blocks as tl_register_* — to compute shared-memory
* multi-buffer counts. Emit skew still uses \a pipeline_info (register
* stages).
*/
PipelineRewriter(Map<Var, Buffer> buffer_data_to_buffer,
const Array<Buffer> &pipeline_allocs,
const For &pipeline_loop, const PipelineInfo &pipeline_info,
const std::vector<LetWrapper> &loop_var_let_wrappers)
const std::vector<LetWrapper> &loop_var_let_wrappers,
String stage_attr_key, String order_attr_key,
String async_attr_key,
int register_pipeline_min_versions = 0,
const PipelineInfo *shared_buffer_version_pipeline = nullptr)
: buffer_data_to_buffer_(std::move(buffer_data_to_buffer)),
pipeline_allocs_(pipeline_allocs), pipeline_loop_(pipeline_loop),
pipeline_info_(pipeline_info),
loop_var_let_wrappers_(loop_var_let_wrappers) {}
loop_var_let_wrappers_(loop_var_let_wrappers),
stage_attr_key_(std::move(stage_attr_key)),
order_attr_key_(std::move(order_attr_key)),
async_attr_key_(std::move(async_attr_key)),
register_pipeline_min_versions_(register_pipeline_min_versions),
shared_buffer_version_pipeline_(shared_buffer_version_pipeline) {}
Stmt BuildPipeline() {
// Step 1: Analyze accesses to the buffers in the pipeline and compute the
// number of versions need to maintain for each buffer.
std::unordered_map<Buffer, BufferAccessInfo, ObjectPtrHash, ObjectPtrEqual>
infos = GetBufferAccessInfo();
infos_reg = GetBufferAccessInfo(pipeline_info_, /*update_max_stage=*/true);
std::unordered_map<Buffer, BufferAccessInfo, ObjectPtrHash, ObjectPtrEqual>
infos_sw;
if (shared_buffer_version_pipeline_ != nullptr) {
infos_sw = GetBufferAccessInfo(*shared_buffer_version_pipeline_,
/*update_max_stage=*/false);
}
auto try_lookup =
[&](const Buffer &buffer,
const std::unordered_map<Buffer, BufferAccessInfo, ObjectPtrHash,
ObjectPtrEqual> &from,
Buffer *out_canonical, const BufferAccessInfo **out_acc) -> bool {
auto it = from.find(buffer);
if (it != from.end()) {
*out_canonical = it->first;
*out_acc = &it->second;
return true;
}
for (const auto &kv : from) {
if (kv.first->data.same_as(buffer->data)) {
*out_canonical = kv.first;
*out_acc = &kv.second;
return true;
}
}
return false;
};
// pipeline_allocs_ may list a different Buffer handle than the one used in
// block read/write regions (same underlying Var / Allocate). Never use
// infos.at(buffer) — missing keys caused _Map_base::at at runtime.
for (const Buffer &buffer : pipeline_allocs_) {
int num_versions = ComputeBufferVersions(buffer, infos.at(buffer));
Buffer canonical;
const BufferAccessInfo *acc = nullptr;
bool found = false;
if (IsSharedPipelineBuffer(buffer) && !infos_sw.empty()) {
found = try_lookup(buffer, infos_sw, &canonical, &acc) ||
try_lookup(buffer, infos_reg, &canonical, &acc);
} else {
found = try_lookup(buffer, infos_reg, &canonical, &acc) ||
(!infos_sw.empty() && try_lookup(buffer, infos_sw, &canonical, &acc));
}
int num_versions = 1;
if (acc != nullptr) {
const PipelineInfo &version_info =
(IsSharedPipelineBuffer(canonical) &&
shared_buffer_version_pipeline_ != nullptr)
? *shared_buffer_version_pipeline_
: pipeline_info_;
num_versions = ComputeBufferVersions(canonical, *acc, version_info);
} else if (stage_attr_key_ == "tl_register_pipeline_stage" &&
IsRegisterPipelineLocalBuffer(buffer) &&
register_pipeline_min_versions_ >= 2) {
// Collectors found a local alloc without block read/write coverage;
// still ping-pong registers like shared-memory multi-buffering.
canonical = buffer;
num_versions = register_pipeline_min_versions_;
} else {
continue;
}
// Register pipeline: allocate at least `num_register_stages` (default 2)
// physical register groups so copy (e.g. iter k+1) and compute (iter k)
// can overlap; version index uses the same k / floormod as shared smem.
if (register_pipeline_min_versions_ >= 2 &&
stage_attr_key_ == "tl_register_pipeline_stage" &&
IsRegisterPipelineLocalBuffer(canonical)) {
num_versions =
std::max(num_versions, register_pipeline_min_versions_);
}
if (num_versions > 1) {
buffer_remap_.Set(buffer, RewriteAllocBuffer(buffer, num_versions));
Buffer remapped = RewriteAllocBuffer(canonical, num_versions);
buffer_remap_.Set(canonical, remapped);
if (!buffer.same_as(canonical)) {
buffer_remap_.Set(buffer, remapped);
}
}
}
// BufferStore/Load may use a different Buffer node than the canonical key
// above (same underlying data Var). Alias every handle seen in the pipeline
// so PipelineBodyRewriter always finds the versioned Buffer.
Map<Var, Buffer> data_var_to_versioned;
for (const auto &kv : buffer_remap_) {
data_var_to_versioned.Set(kv.first->data, kv.second);
}
auto alias_pipeline_buffer = [&](const Buffer &b) {
if (auto vb = data_var_to_versioned.Get(b->data)) {
buffer_remap_.Set(b, *vb);
}
};
for (const Buffer &b : pipeline_allocs_) {
alias_pipeline_buffer(b);
}
for (const auto &kv : infos_reg) {
alias_pipeline_buffer(kv.first);
}
for (const auto &kv : infos_sw) {
alias_pipeline_buffer(kv.first);
}
for (const auto &pair : pipeline_info_) {
const Block &blk = pair.first;
for (const BufferRegion &r : blk->reads) {
alias_pipeline_buffer(r->buffer);
}
for (const BufferRegion &w : blk->writes) {
alias_pipeline_buffer(w->buffer);
}
}
ordered_stmts_.resize(pipeline_info_.size());
......@@ -311,7 +565,6 @@ public:
}
Block block = MakeBlock(stmt, buffer_data_to_buffer_);
block.CopyOnWrite()->alloc_buffers = std::move(alloc_buffers);
LOG(INFO) << "Final rewritten pipeline block: " << block;
return BlockRealize({}, Bool(true), block);
}
......@@ -324,13 +577,15 @@ private:
* needed to maintain after rewriting.
*/
std::unordered_map<Buffer, BufferAccessInfo, ObjectPtrHash, ObjectPtrEqual>
GetBufferAccessInfo() {
GetBufferAccessInfo(const PipelineInfo &pinfo, bool update_max_stage) {
std::unordered_map<Buffer, BufferAccessInfo, ObjectPtrHash, ObjectPtrEqual>
infos;
for (const auto &pair : pipeline_info_) {
for (const auto &pair : pinfo) {
const Block &block = pair.first;
int stage = pair.second.stage;
max_stage_ = std::max(max_stage_, stage);
if (update_max_stage) {
max_stage_ = std::max(max_stage_, stage);
}
for (const BufferRegion &write : block->writes) {
if (!infos.count(write->buffer)) {
......@@ -391,7 +646,8 @@ private:
* \return The number of versions required for the target buffer.
*/
int ComputeBufferVersions(const Buffer &buffer,
const BufferAccessInfo &buffer_info) {
const BufferAccessInfo &buffer_info,
const PipelineInfo &version_pipeline_info) {
if (buffer_info.def == -1) {
// Keep the original number of versions as buffers defined outside the
// software pipeline should not be mutated.
......@@ -408,7 +664,7 @@ private:
// block_j such that order(block_i) < order(block_j) and stage(block_i) <
// stage(block_j) and the access regions of block_i and block_j overlap.
bool need_multi_version = false;
for (const auto &pair1 : pipeline_info_) {
for (const auto &pair1 : version_pipeline_info) {
const Block &writer_block = pair1.first;
const auto &writer_info = pair1.second;
......@@ -421,7 +677,7 @@ private:
continue;
}
for (const auto &pair2 : pipeline_info_) {
for (const auto &pair2 : version_pipeline_info) {
const Block &reader_block = pair2.first;
const auto &reader_info = pair2.second;
auto it2 = std::find_if(
......@@ -440,7 +696,11 @@ private:
}
}
}
if (!need_multi_version) {
// Do not collapse register-file double buffering using the shared-memory
// heuristic; locals need explicit ping-pong when stages differ.
if (!need_multi_version &&
!(stage_attr_key_ == "tl_register_pipeline_stage" &&
IsRegisterPipelineLocalBuffer(buffer))) {
num_versions--;
}
}
......@@ -618,6 +878,33 @@ private:
wait_expr = analyzer_.Simplify(wait_expr);
dep_local_state.pending_waits.push_back({static_cast<int>(i), wait_expr});
}
// Register pipeline splits shared→local into multiple consecutive blocks; each
// registers the same async wait. CUDA codegen treats each AttrStmt as a full
// sync — merge waits with structurally equal inflight counts and attach once
// before the earliest dependent block.
tvm::StructuralEqual expr_equal;
for (auto &kv : *async_states_local) {
auto &pws = kv.second.pending_waits;
if (pws.size() <= 1) {
continue;
}
std::vector<AsyncStateLocal::PendingWait> merged;
merged.reserve(pws.size());
for (const auto &pw : pws) {
bool joined = false;
for (auto &ex : merged) {
if (expr_equal(ex.wait_count, pw.wait_count)) {
ex.insert_before = std::min(ex.insert_before, pw.insert_before);
joined = true;
break;
}
}
if (!joined) {
merged.push_back(pw);
}
}
pws = std::move(merged);
}
}
// Given pipelined blocks and async-related information, generate final loop
......@@ -634,9 +921,6 @@ private:
n->body = AttrStmt(zero, tir::attr::async_wait_queue_scope, stage_id,
AttrStmt(zero, tir::attr::async_wait_inflight_count,
pw.wait_count, n->body));
LOG(INFO) << "Inserting async_wait with count " << pw.wait_count
<< " before block with order " << new_blocks[pw.insert_before].order
<< " for async stage " << stage_id;
}
}
......@@ -788,9 +1072,20 @@ private:
Map<String, Any> preserved_annotations;
for (const auto &kv : pipeline_loop_->annotations) {
const String &key = kv.first;
if (kv.first != tir::attr::software_pipeline_stage &&
kv.first != tir::attr::software_pipeline_order &&
kv.first != tir::attr::software_pipeline_async_stages) {
if (kv.first != stage_attr_key_ && kv.first != order_attr_key_ &&
kv.first != async_attr_key_) {
// Register pipeline rewrite splits the body into finer blocks than
// software_pipeline_* (shared-memory stages). Carrying shared
// pipeline annotations onto inner loops breaks a later
// InjectSoftwarePipeline pass (length mismatch); shared injection is
// applied afterward on the pre-split loop using tl_register_*.
if (stage_attr_key_ == "tl_register_pipeline_stage") {
if (kv.first == tir::attr::software_pipeline_stage ||
kv.first == tir::attr::software_pipeline_order ||
kv.first == tir::attr::software_pipeline_async_stages) {
continue;
}
}
preserved_annotations.Set(key, kv.second);
}
}
......@@ -817,6 +1112,13 @@ private:
Array<Block> ordered_stmts_;
std::map<int, AsyncStateGlobal> async_states;
std::vector<LetWrapper> loop_var_let_wrappers_;
String stage_attr_key_;
String order_attr_key_;
String async_attr_key_;
/*! See constructor; 0 means disabled (shared / non-register pipeline). */
int register_pipeline_min_versions_{0};
/*! Non-owning; when set, shared-memory bank counts follow software_pipeline_stage. */
const PipelineInfo *shared_buffer_version_pipeline_{nullptr};
};
/*!
......@@ -856,9 +1158,14 @@ void BuildDependencyGraph(const Array<Block> &blocks,
class PipelineInjector : private StmtExprMutator {
public:
static Stmt Inject(const PrimFunc &func) {
static Stmt Inject(const PrimFunc &func, String stage_attr_key,
String order_attr_key, String async_attr_key,
String pipeline_name) {
auto global_symbol = func->GetAttr<String>(tvm::attr::kGlobalSymbol);
PipelineInjector injector(global_symbol);
PipelineInjector injector(global_symbol, std::move(stage_attr_key),
std::move(order_attr_key),
std::move(async_attr_key),
std::move(pipeline_name));
for (const auto &kv : func->buffer_map) {
const Buffer &buffer = kv.second;
injector.buffer_data_to_buffer_.Set(buffer->data, buffer);
......@@ -867,8 +1174,165 @@ public:
}
private:
explicit PipelineInjector(Optional<String> global_symbol)
: global_symbol_(std::move(global_symbol)) {}
bool ShouldSplitRegisterPipelineBlock(const Stmt &child) const {
if (stage_attr_key_ != "tl_register_pipeline_stage") {
return false;
}
return ExtractRegisterInnerSeq(child, nullptr) != nullptr;
}
const SeqStmtNode *ExtractRegisterInnerSeq(
const Stmt &child, bool *has_unsupported_mma_loop) const {
Stmt wrapped = child;
while (true) {
if (wrapped.as<BlockRealizeNode>()) {
break;
}
if (const auto *attr = wrapped.as<AttrStmtNode>()) {
wrapped = attr->body;
continue;
}
if (const auto *let_stmt = wrapped.as<LetStmtNode>()) {
wrapped = let_stmt->body;
continue;
}
if (const auto *if_then_else = wrapped.as<IfThenElseNode>()) {
if (!if_then_else->else_case.defined()) {
wrapped = if_then_else->then_case;
continue;
}
}
return nullptr;
}
const auto *br = wrapped.as<BlockRealizeNode>();
if (br == nullptr || !is_one(br->predicate)) {
return nullptr;
}
if (!RegisterPipelineLikeBlock(br->block->body)) {
return nullptr;
}
Stmt current = br->block->body;
while (true) {
if (const auto *seq = current.as<SeqStmtNode>()) {
return seq;
}
if (const auto *inner_br = current.as<BlockRealizeNode>()) {
current = inner_br->block->body;
continue;
}
if (const auto *attr = current.as<AttrStmtNode>()) {
current = attr->body;
continue;
}
if (const auto *let_stmt = current.as<LetStmtNode>()) {
current = let_stmt->body;
continue;
}
if (const auto *for_stmt = current.as<ForNode>()) {
if (is_one(for_stmt->extent)) {
current = for_stmt->body;
continue;
}
if (has_unsupported_mma_loop != nullptr &&
RegisterPipelineLikeBlock(for_stmt->body)) {
*has_unsupported_mma_loop = true;
}
return nullptr;
}
if (const auto *if_then_else = current.as<IfThenElseNode>()) {
if (!if_then_else->else_case.defined()) {
current = if_then_else->then_case;
continue;
}
}
return nullptr;
}
}
bool RegisterPipelineLikeBlock(const Stmt &stmt) const {
class MmaDetector : public StmtExprVisitor {
public:
bool has_mma = false;
void VisitExpr_(const CallNode *op) final {
if (const auto *op_node = op->op.as<OpNode>()) {
if (op_node->name == "tl.tvm_mmac") {
has_mma = true;
}
}
StmtExprVisitor::VisitExpr_(op);
}
};
MmaDetector detector;
detector(stmt);
return detector.has_mma;
}
explicit PipelineInjector(Optional<String> global_symbol, String stage_attr_key,
String order_attr_key, String async_attr_key,
String pipeline_name)
: global_symbol_(std::move(global_symbol)),
stage_attr_key_(std::move(stage_attr_key)),
order_attr_key_(std::move(order_attr_key)),
async_attr_key_(std::move(async_attr_key)),
pipeline_name_(std::move(pipeline_name)) {}
/*!
* \brief Build fine-block pipeline info whose stages come from
* software_pipeline_stage (coarse per SeqStmt child), mapped through the same
* MMA inner-seq split as register pipeline planning.
*/
std::optional<PipelineInfo>
MaybeSharedVersionPipelineInfo(const ForNode *loop,
const PipelineInfo &register_pipeline_info,
const Array<Block> &original_order,
const SeqStmtNode *pipeline_body_seq) const {
if (stage_attr_key_ != "tl_register_pipeline_stage") {
return std::nullopt;
}
auto stage_any = loop->annotations.Get(tir::attr::software_pipeline_stage);
if (!stage_any) {
return std::nullopt;
}
auto coarse_stages = Downcast<Array<Integer>>(stage_any.value());
if (coarse_stages.size() != pipeline_body_seq->seq.size()) {
return std::nullopt;
}
std::vector<int> fine_to_coarse;
std::function<void(const Stmt &, int)> walk_coarse =
[&](const Stmt &stmt, int outer_idx) {
bool has_unsupported_mma_loop = false;
if (const auto *inner_seq =
ExtractRegisterInnerSeq(stmt, &has_unsupported_mma_loop)) {
for (const Stmt &inner_child : inner_seq->seq) {
walk_coarse(inner_child, outer_idx);
}
return;
}
if (has_unsupported_mma_loop) {
return;
}
fine_to_coarse.push_back(outer_idx);
};
for (size_t i = 0; i < pipeline_body_seq->seq.size(); ++i) {
walk_coarse(pipeline_body_seq->seq[i], static_cast<int>(i));
}
if (fine_to_coarse.size() != original_order.size()) {
return std::nullopt;
}
PipelineInfo sw_info;
for (size_t i = 0; i < original_order.size(); ++i) {
Block blk = original_order[i];
auto it = register_pipeline_info.find(blk);
if (it == register_pipeline_info.end()) {
return std::nullopt;
}
PipelineAnnotation pa = it->second;
pa.stage = coarse_stages[static_cast<size_t>(fine_to_coarse[i])]->value;
sw_info.emplace(blk, pa);
}
return sw_info;
}
/*!
* \brief Check the pipeline satisfies the following conditions:
......@@ -965,7 +1429,7 @@ private:
}
if (const auto *if_then_else = current.as<IfThenElseNode>()) {
ICHECK(!if_then_else->else_case.defined())
<< "InjectSoftwarePipeline: Can't handle the body of the loop "
<< pipeline_name_ << ": Can't handle the body of the loop "
"because the IfThenElse node has an else branch";
PrimExpr condition = if_then_else->condition;
Span span = if_then_else->span;
......@@ -1018,8 +1482,32 @@ private:
auto f_add_child = [&](const Stmt &child) {
original_order.push_back(MakeBlock(child, buffer_data_to_buffer_));
};
const bool split_like_register =
(stage_attr_key_ == "tl_register_pipeline_stage") ||
((stage_attr_key_ == tir::attr::software_pipeline_stage) &&
op->annotations.count("tl_register_pipeline_stage"));
std::function<void(const Stmt &)> add_register_components =
[&](const Stmt &stmt) {
bool has_unsupported_mma_loop = false;
if (const auto *inner_seq =
ExtractRegisterInnerSeq(stmt, &has_unsupported_mma_loop)) {
for (const Stmt &inner_child : inner_seq->seq) {
add_register_components(inner_child);
}
return;
}
if (has_unsupported_mma_loop) {
LOG(FATAL) << "ValueError: Register software pipeline injection does "
"not support splitting MMA blocks wrapped by loops "
"with extent > 1. Please skip register pipeline "
"planning for this loop or use ki extent == 1.";
}
f_add_child(stmt);
};
for (size_t i = 0; i < pipeline_body_seq->seq.size(); i++) {
const Stmt &child = pipeline_body_seq->seq[i];
size_t before_size = original_order.size();
const auto *nested_block_realize = child.as<BlockRealizeNode>();
if (nested_block_realize && is_one(nested_block_realize->predicate) &&
nested_block_realize->block->body->IsInstance<SeqStmtNode>()) {
......@@ -1031,13 +1519,73 @@ private:
buffer_data_to_buffer_.Set(buffer->data, buffer);
}
}
if (split_like_register) {
add_register_components(child);
continue;
}
f_add_child(child);
}
auto pipeline_stages = Downcast<Array<Integer>>(
op->annotations.at(tir::attr::software_pipeline_stage));
auto pipeline_orders = Downcast<Array<Integer>>(
op->annotations.at(tir::attr::software_pipeline_order));
if (stage_attr_key_ == "tl_register_pipeline_stage") {
RegisterPipelineBufferCollector collect_locals(&pipeline_allocs,
&buffer_data_to_buffer_);
collect_locals(pipeline_body_root);
}
Array<Integer> pipeline_stages =
Downcast<Array<Integer>>(op->annotations.at(stage_attr_key_));
Array<Integer> pipeline_orders =
Downcast<Array<Integer>>(op->annotations.at(order_attr_key_));
// RegisterPipelinePlanning may split MMA inner SeqStmt into more blocks
// than PipelinePlanning's software_pipeline_* entries (coarse stages).
// Map each fine block to its top-level SeqStmt child's shared stage and
// use tl_register_pipeline_order for per-block ordering / validation.
if (stage_attr_key_ == tir::attr::software_pipeline_stage &&
(pipeline_stages.size() != original_order.size() ||
pipeline_orders.size() != original_order.size()) &&
op->annotations.count("tl_register_pipeline_stage") &&
op->annotations.count("tl_register_pipeline_order")) {
auto tl_order_arr =
Downcast<Array<Integer>>(op->annotations.at("tl_register_pipeline_order"));
ICHECK_EQ(tl_order_arr.size(), original_order.size())
<< "tl_register_pipeline_order length must match blockized pipeline "
"body when expanding shared-memory pipeline annotations.";
ICHECK_EQ(pipeline_stages.size(), pipeline_body_seq->seq.size())
<< "software_pipeline_stage must have one entry per top-level "
"SeqStmt child when inner blocks are split for register pipeline.";
std::vector<int> fine_to_coarse;
std::function<void(const Stmt &, int)> walk_coarse =
[&](const Stmt &stmt, int outer_idx) {
bool has_unsupported_mma_loop = false;
if (const auto *inner_seq =
ExtractRegisterInnerSeq(stmt, &has_unsupported_mma_loop)) {
for (const Stmt &inner_child : inner_seq->seq) {
walk_coarse(inner_child, outer_idx);
}
return;
}
if (has_unsupported_mma_loop) {
LOG(FATAL) << "PipelineInjector(" << pipeline_name_
<< "): cannot expand shared pipeline stages: inner "
"MMA loop with extent > 1.";
}
fine_to_coarse.push_back(outer_idx);
};
for (size_t i = 0; i < pipeline_body_seq->seq.size(); ++i) {
walk_coarse(pipeline_body_seq->seq[i], static_cast<int>(i));
}
ICHECK_EQ(fine_to_coarse.size(), original_order.size())
<< "Fine/coarse pipeline mapping does not match blockized blocks.";
Array<Integer> expanded_stages;
Array<Integer> expanded_orders;
for (size_t i = 0; i < original_order.size(); ++i) {
int c = fine_to_coarse[i];
expanded_stages.push_back(pipeline_stages[static_cast<size_t>(c)]);
expanded_orders.push_back(tl_order_arr[i]);
}
pipeline_stages = expanded_stages;
pipeline_orders = expanded_orders;
}
CHECK_EQ(pipeline_stages.size(), original_order.size())
<< "PrimFunc " << global_symbol_ << " has original order "
<< original_order.Map(
......@@ -1052,8 +1600,7 @@ private:
<< " with different size";
std::unordered_set<int> pipeline_async_stages;
if (auto annot =
op->annotations.Get(tir::attr::software_pipeline_async_stages)) {
if (auto annot = op->annotations.Get(async_attr_key_)) {
for (auto s : Downcast<Array<Integer>>(annot.value())) {
pipeline_async_stages.insert(s->value);
}
......@@ -1063,9 +1610,6 @@ private:
int stage = static_cast<int>(pipeline_stages[i]->value);
bool is_async =
pipeline_async_stages.find(stage) != pipeline_async_stages.end();
printf("Block %s assigned to stage %d with order %d%s\n", original_order[i]->name_hint.c_str(),
stage, static_cast<int>(pipeline_orders[i]->value),
is_async ? " (async)" : " sync");
PipelineAnnotation stage_order{
stage,
/*order=*/static_cast<int>(pipeline_orders[i]->value), is_async,
......@@ -1075,10 +1619,32 @@ private:
ValidatePipelineBody(pipeline_info, original_order);
int register_pipeline_min_versions = 0;
if (stage_attr_key_ == "tl_register_pipeline_stage") {
register_pipeline_min_versions = 2;
if (auto anno = op->annotations.Get("num_register_stages")) {
if (const auto *imm = anno.value().as<IntImmNode>()) {
register_pipeline_min_versions = imm->value;
}
}
if (register_pipeline_min_versions < 2) {
register_pipeline_min_versions = 2;
}
}
std::optional<PipelineInfo> shared_version_pipeline =
MaybeSharedVersionPipelineInfo(op, pipeline_info, original_order,
pipeline_body_seq);
const PipelineInfo *shared_version_ptr =
shared_version_pipeline.has_value() ? &shared_version_pipeline.value()
: nullptr;
// Step 4: Rewrite the pipeline body.
Stmt pipeline = PipelineRewriter(buffer_data_to_buffer_, pipeline_allocs,
tvm::ffi::GetRef<For>(op), pipeline_info,
loop_var_let_wrappers)
loop_var_let_wrappers, stage_attr_key_,
order_attr_key_, async_attr_key_,
register_pipeline_min_versions,
shared_version_ptr)
.BuildPipeline();
auto apply_wrappers = [&](Stmt stmt) {
for (auto it = rewrap_fns.rbegin(); it != rewrap_fns.rend(); ++it) {
......@@ -1108,7 +1674,6 @@ private:
buffer_data_to_buffer_.erase(buffer->data);
}
}
LOG(INFO) << "Finished rewriting the pipeline loop with body:\n" << pipeline;
return pipeline;
}
......@@ -1128,13 +1693,12 @@ private:
for (const auto &buffer : op->alloc_buffers) {
buffer_data_to_buffer_.erase(buffer->data);
}
LOG(INFO) << "Rewriting blockddd " << block;
return block;
}
bool HasPipelineAnnotation(const ForNode *op) const {
auto it1 = op->annotations.find(tir::attr::software_pipeline_stage);
auto it2 = op->annotations.find(tir::attr::software_pipeline_order);
auto it1 = op->annotations.find(stage_attr_key_);
auto it2 = op->annotations.find(order_attr_key_);
bool has_stage = it1 != op->annotations.end();
bool has_order = it2 != op->annotations.end();
if (has_stage && has_order) {
......@@ -1142,17 +1706,23 @@ private:
}
if (has_stage) {
LOG(FATAL)
<< "ValueError: Stage of the software pipeline is not defined.";
<< "ValueError: Stage of pipeline(" << pipeline_name_
<< ") is not defined.";
}
if (has_order) {
LOG(FATAL)
<< "ValueError: Order of the software pipeline is not defined.";
<< "ValueError: Order of pipeline(" << pipeline_name_
<< ") is not defined.";
}
return false;
}
Map<Var, Buffer> buffer_data_to_buffer_;
Optional<String> global_symbol_;
String stage_attr_key_;
String order_attr_key_;
String async_attr_key_;
String pipeline_name_;
};
} // namespace software_pipeline
......@@ -1164,19 +1734,35 @@ tir::transform::Pass InjectSoftwarePipeline() {
using namespace tir::transform;
auto pass_func = [=](PrimFunc f, const IRModule &m, const PassContext &ctx) {
auto *fptr = f.CopyOnWrite();
fptr->body = software_pipeline::PipelineInjector::Inject(f);
fptr->body = software_pipeline::PipelineInjector::Inject(
f, tir::attr::software_pipeline_stage, tir::attr::software_pipeline_order,
tir::attr::software_pipeline_async_stages, "shared-software-pipeline");
fptr->body = ConvertSSA(std::move(fptr->body));
LOG(INFO) << "Finished injecting software pipeline for PrimFunc " << f->GetAttr<String>(tvm::attr::kGlobalSymbol).value_or("<unknown>")
<< ", the transformed body is:\n" << fptr->body;
return f;
};
return CreatePrimFuncPass(pass_func, 0, "tl.InjectSoftwarePipeline", {});
}
tir::transform::Pass InjectRegisterSoftwarePipeline() {
using namespace tir::transform;
auto pass_func = [=](PrimFunc f, const IRModule &m, const PassContext &ctx) {
auto *fptr = f.CopyOnWrite();
fptr->body = software_pipeline::PipelineInjector::Inject(
f, "tl_register_pipeline_stage", "tl_register_pipeline_order",
"tl_register_pipeline_async_stages", "register-software-pipeline");
fptr->body = ConvertSSA(std::move(fptr->body));
return f;
};
return CreatePrimFuncPass(pass_func, 0, "tl.InjectRegisterSoftwarePipeline",
{});
}
TVM_FFI_STATIC_INIT_BLOCK() {
namespace refl = tvm::ffi::reflection;
refl::GlobalDef().def("tl.transform.InjectSoftwarePipeline",
InjectSoftwarePipeline);
refl::GlobalDef().def("tl.transform.InjectRegisterSoftwarePipeline",
InjectRegisterSoftwarePipeline);
}
} // namespace tl
......
src/transform/lower_dcu_resource.cc
View file @ 44cc93c7
......@@ -66,10 +66,8 @@ class VariableKeeper : public tvm::tir::ExprMutator {
PrimExpr VisitExpr_(const tvm::tir::VarNode* op) override {
// 关键调试：打印每一个遇到的变量及其地址
if (keep_vars_.count(op)) {
LOG(INFO) << "[KEEP] Found var in list: " << op->name_hint << " (" << op << ")";
return GetRef<PrimExpr>(op);
} else {
LOG(INFO) << "[ERASE] Var not in list: " << op->name_hint << " (" << op << ")";
return tvm::tir::make_zero(op->dtype);
}
}
......@@ -115,7 +113,6 @@ CollectResult CollectResources(const Stmt& body) {
if (tag.find("threadIdx") != std::string::npos) {
tvm::tir::Var thread_var = iv->var;
LOG(INFO) << "Entering thread scope: " << tag << " with var " << thread_var->name_hint;
loop_vars_.insert(thread_var.get());
StmtExprVisitor::VisitStmt_(attr);
......@@ -154,12 +151,20 @@ CollectResult CollectResources(const Stmt& body) {
scope_stack_.pop_back();
}
void VisitStmt_(const BufferStoreNode* op) final {
LOG(INFO) << "Visiting BufferStore: " << op->buffer->name;
static const BufferLoadNode* PeelGlobalLoadValue(const PrimExpr& v) {
if (const auto* load = v.as<BufferLoadNode>()) {
return load;
}
if (const auto* cast = v.as<CastNode>()) {
return cast->value.as<BufferLoadNode>();
}
return nullptr;
}
void VisitStmt_(const BufferStoreNode* op) final {
Buffer dst = op->buffer;
if (IsSharedScope(dst) && op->value.defined() && in_async) {
if (const auto* load = op->value.as<BufferLoadNode>()) {
if (const auto* load = PeelGlobalLoadValue(op->value)) {
Buffer src = load->buffer;
if (IsGlobalScope(src)) {
const StmtNode* target = op;
......@@ -197,7 +202,6 @@ CollectResult CollectResources(const Stmt& body) {
for (const auto& idx : load->indices) {
PrimExpr filtered = keeper(idx);
for_var_only_indices.push_back(analyzer.Simplify(filtered));
LOG(INFO) << "ONLY Index: " << idx;
}
CopyInfo info{dst, src, op->indices, for_var_only_indices, GetRef<Stmt>(op)};
result.copies.push_back(info);
......@@ -209,10 +213,6 @@ CollectResult CollectResources(const Stmt& body) {
VariableEliminator eliminator(loop_vars_);
tvm::arith::Analyzer analyzer;
Array<PrimExpr> base_indices;
LOG(INFO) << loop_vars_.size() << " loop vars in context.";
for (const auto* var : loop_vars_) {
LOG(INFO) << "Loop Var: " << var->name_hint;
}
for (const auto& idx : load->indices) {
// 将所有外层循环变量 (k, i 等) 全部替换为 0
PrimExpr no_loops = eliminator(idx);
......@@ -227,7 +227,6 @@ CollectResult CollectResources(const Stmt& body) {
// 如果需要把 indices 的每个元素作为独立参数展开：
for (const auto& idx : base_indices) {
args.push_back(idx);
LOG(INFO) << "Clean Index: " << idx;
}
PrimExpr val = Call(DataType::Int(32, 4),
Op::Get("tl.make_dcu_resource"), args);
......@@ -236,18 +235,15 @@ CollectResult CollectResources(const Stmt& body) {
// 将这个绑定关系和 destination 的 shared buffer 绑死
result.shared_alloc_to_binding[src->name] = {var, val};
}
LOG(INFO) << "result.copies.size() = " << result.copies.size();
}
}
}
StmtExprVisitor::VisitStmt_(op);
}
};
LOG(INFO) << "Starting resource collection...";
Collector col;
col(body);
LOG(INFO) << "Finished resource collection. Found " << col.result.copies.size() << " copy(s).";
return col.result;
}
......@@ -355,14 +351,11 @@ PrimFunc LowerSharedGlobalCopy(PrimFunc f) {
auto* n = f.CopyOnWrite();
// 收集信息
LOG(INFO) << "Starting LowerSharedGlobalCopy transformation...";
auto res = CollectResources(n->body);
if (res.copies.empty()){
LOG(INFO) << "No shared-global copy patterns detected. Skipping transformation.";
return f;
}
LOG(INFO) << "Replaced " << res.copies.size() << " copy(s) with dcu_async_copy.";
// 注入res声明
Stmt injected = ResourceInjector::Run(n->body, res.shared_alloc_to_binding, res.inject_target);
......
src/transform/register_pipeline_planning.cc 0 → 100644
View file @ 44cc93c7
#include <tvm/ffi/reflection/registry.h>
#include <tvm/tir/builtin.h>
#include <tvm/tir/op.h>
#include <tvm/tir/stmt_functor.h>
#include <tvm/tir/transform.h>
#include <algorithm>
#include <string>
#include <utility>
#include <vector>
namespace tvm {
namespace tl {
using namespace tir;
using ffi::Array;
using ffi::String;
using ffi::Map;
using ffi::Any;
namespace {
constexpr const char* kRegisterPipelineStageAttr = "tl_register_pipeline_stage";
constexpr const char* kRegisterPipelineOrderAttr = "tl_register_pipeline_order";
constexpr const char* kRegisterPipelineAsyncStagesAttr =
"tl_register_pipeline_async_stages";
inline bool IsScopeOrPrefix(const String& scope, const char* prefix) {
std::string s = scope;
std::string p = prefix;
return s == p || (s.size() > p.size() && s.compare(0, p.size(), p) == 0 &&
s[p.size()] == '.');
}
inline bool IsLocalScope(const String& scope) {
return IsScopeOrPrefix(scope, "local");
}
inline bool IsSharedScope(const String& scope) {
return IsScopeOrPrefix(scope, "shared");
}
class RegisterPipelineClassifier : public StmtExprVisitor {
public:
static bool IsSharedToLocalCopy(const Stmt& stmt) {
RegisterPipelineClassifier classifier;
classifier(stmt);
return classifier.has_local_store_ && classifier.reads_shared_;
}
static bool HasMmaCompute(const Stmt& stmt) {
RegisterPipelineClassifier classifier;
classifier(stmt);
return classifier.has_mma_compute_;
}
static bool HasUnitExtentLoop(const Stmt& stmt) {
RegisterPipelineClassifier classifier;
classifier(stmt);
return classifier.has_unit_extent_loop_;
}
static bool HasGlobalToLocalCopy(const Stmt& stmt) {
RegisterPipelineClassifier classifier;
classifier(stmt);
return classifier.reads_global_;
}
static bool HasAnyLocalAccess(const Stmt& stmt) {
RegisterPipelineClassifier classifier;
classifier(stmt);
return classifier.reads_local_ || classifier.has_local_store_;
}
private:
void VisitStmt_(const ForNode* op) final {
if (is_one(op->extent)) {
has_unit_extent_loop_ = true;
}
StmtExprVisitor::VisitStmt_(op);
}
void VisitStmt_(const BufferStoreNode* op) final {
if (IsLocalScope(op->buffer.scope())) {
has_local_store_ = true;
bool old = in_local_store_value_;
in_local_store_value_ = true;
VisitExpr(op->value);
in_local_store_value_ = old;
return;
}
StmtExprVisitor::VisitStmt_(op);
}
void VisitExpr_(const BufferLoadNode* op) final {
if (in_local_store_value_ && IsSharedScope(op->buffer.scope())) {
reads_shared_ = true;
} else if (op->buffer.scope() == "global") {
reads_global_ = true;
} else if (IsLocalScope(op->buffer.scope())) {
reads_local_ = true;
}
StmtExprVisitor::VisitExpr_(op);
}
void VisitExpr_(const CallNode* op) final {
if (auto* op_node = op->op.as<OpNode>()) {
std::string op_name = op_node->name;
if ((op_name == "tl.tvm_mmac")) {
has_mma_compute_ = true;
}
StmtExprVisitor::VisitExpr_(op);
}
}
bool in_local_store_value_ = false;
bool has_local_store_ = false;
bool reads_shared_ = false;
bool reads_local_ = false;
bool has_mma_compute_ = false;
bool reads_global_ = false;
bool has_unit_extent_loop_ = false;
};
class RegisterPipelinePlanner : public StmtExprMutator {
public:
Stmt VisitStmt_(const ForNode* op) final {
For for_node = Downcast<For>(StmtExprMutator::VisitStmt_(op));
// Register pipeline is designed to refine an existing outer shared-memory
// pipeline loop. Do not run on arbitrary inner loops.
bool has_shared_pipeline_anno =
op->annotations.count(tir::attr::software_pipeline_stage) &&
op->annotations.count(tir::attr::software_pipeline_order);
if (!has_shared_pipeline_anno) {
return for_node;
}
int num_register_stages = 2;
if (auto num_reg_stages_anno = op->annotations.Get("num_register_stages")) {
if (const auto* imm = num_reg_stages_anno.value().as<IntImmNode>()) {
num_register_stages = imm->value;
}
}
if (num_register_stages <= 1) {
return for_node;
}
if (for_node->kind != ForKind::kSerial) {
return for_node;
}
const SeqStmtNode* seq = GetPipelineBodySeq(for_node->body);
if (seq == nullptr) {
return for_node;
}
std::vector<Stmt> components;
components.reserve(seq->size());
for (const Stmt& child : seq->seq) {
bool has_unsupported_mma_loop = false;
if (const auto* inner_seq =
ExtractSplittableInnerSeq(child, &has_unsupported_mma_loop)) {
for (const Stmt& inner : inner_seq->seq) {
components.push_back(inner);
}
} else {
// If MMA is wrapped by a loop with extent > 1, this pass cannot
// safely infer register pipeline stages. Keep the original loop.
if (has_unsupported_mma_loop) {
return for_node;
}
components.push_back(child);
}
}
const int n = static_cast<int>(components.size());
if (n == 0) {
return for_node;
}
std::vector<bool> is_shared_to_local(n, false);
std::vector<bool> has_mma_compute(n, false);
std::vector<bool> has_local_access(n, false);
int first_register_producer_idx = -1;
int first_compute_idx = -1;
for (int i = 0; i < n; ++i) {
const Stmt& s = components[i];
if (RegisterPipelineClassifier::IsSharedToLocalCopy(s)) {
is_shared_to_local[i] = true;
if (first_register_producer_idx == -1) {
first_register_producer_idx = i;
}
}
if (RegisterPipelineClassifier::HasMmaCompute(s)) {
has_mma_compute[i] = true;
if (first_compute_idx == -1) {
first_compute_idx = i;
}
}
has_local_access[i] = RegisterPipelineClassifier::HasAnyLocalAccess(s);
}
if (first_register_producer_idx == -1 || first_compute_idx == -1 ||
first_register_producer_idx >= first_compute_idx) {
return for_node;
}
int compute_stage = 1;
if (auto stage_anno = op->annotations.Get(kRegisterPipelineStageAttr)) {
if (auto old_stages = stage_anno.value().try_cast<Array<Integer>>()) {
for (const Integer& stage : old_stages.value()) {
compute_stage = std::max(compute_stage, static_cast<int>(stage->value));
}
}
} else if (auto stage_anno =
op->annotations.Get(tir::attr::software_pipeline_stage)) {
if (auto old_stages = stage_anno.value().try_cast<Array<Integer>>()) {
for (const Integer& stage : old_stages.value()) {
compute_stage = std::max(compute_stage, static_cast<int>(stage->value));
}
}
}
int register_stage = std::max(0, compute_stage - 1);
std::vector<Integer> orders(n, Integer(-1));
std::vector<Integer> stages(n, Integer(compute_stage));
if (auto order_anno = op->annotations.Get(kRegisterPipelineOrderAttr)) {
if (auto old_orders = order_anno.value().try_cast<Array<Integer>>()) {
if (old_orders.value().size() == components.size()) {
for (int i = 0; i < n; ++i) {
orders[i] = old_orders.value()[i];
}
}
}
} else if (auto order_anno =
op->annotations.Get(tir::attr::software_pipeline_order)) {
if (auto old_orders = order_anno.value().try_cast<Array<Integer>>()) {
if (old_orders.value().size() == components.size()) {
for (int i = 0; i < n; ++i) {
orders[i] = old_orders.value()[i];
}
}
}
}
for (int i = 0; i < n; ++i) {
if (orders[i]->value == -1) {
orders[i] = Integer(i);
}
if (i < first_register_producer_idx) {
stages[i] = Integer(0);
continue;
}
if (i < first_compute_idx) {
stages[i] = Integer(register_stage);
continue;
}
if (has_mma_compute[i]) {
stages[i] = Integer(compute_stage);
} else if (is_shared_to_local[i]) {
stages[i] = Integer(register_stage);
} else if (has_local_access[i] && i < first_compute_idx) {
stages[i] = Integer(register_stage);
} else {
stages[i] = Integer(compute_stage);
}
}
Map<String, Any> annotations;
for (const auto& kv : for_node->annotations) {
const String& key = kv.first;
// Keep num_register_stages so InjectRegisterSoftwarePipeline can size
// register ping-pong banks consistently with this pass.
if (key != kRegisterPipelineStageAttr && key != kRegisterPipelineOrderAttr &&
key != kRegisterPipelineAsyncStagesAttr) {
annotations.Set(key, kv.second);
}
}
annotations.Set(kRegisterPipelineStageAttr, Array<Integer>(stages));
annotations.Set(kRegisterPipelineOrderAttr, Array<Integer>(orders));
if (auto async_stages = op->annotations.Get(kRegisterPipelineAsyncStagesAttr)) {
annotations.Set(kRegisterPipelineAsyncStagesAttr, async_stages.value());
} else if (auto sw_async = op->annotations.Get(
tir::attr::software_pipeline_async_stages)) {
// InjectRegisterSoftwarePipeline only consults tl_register_pipeline_async_stages
// when wrapping async producers in async_scope. Without this, global→shared
// copies stay outside async_scope and passes such as LowerSharedGlobalCopy
// (which require in_async) never match.
annotations.Set(kRegisterPipelineAsyncStagesAttr, sw_async.value());
}
return For(for_node->loop_var, for_node->min, for_node->extent,
for_node->kind, for_node->body, for_node->thread_binding,
std::move(annotations));
}
private:
const SeqStmtNode* ExtractSplittableInnerSeq(
const Stmt& stmt, bool* has_unsupported_mma_loop) const {
const auto* br = stmt.as<BlockRealizeNode>();
if (!br || !is_one(br->predicate)) {
return nullptr;
}
if (!RegisterPipelineClassifier::HasMmaCompute(br->block->body)) {
return nullptr;
}
Stmt current = br->block->body;
while (true) {
if (const auto* seq = current.as<SeqStmtNode>()) {
return seq;
}
if (const auto* inner_br = current.as<BlockRealizeNode>()) {
current = inner_br->block->body;
continue;
}
if (const auto* attr = current.as<AttrStmtNode>()) {
current = attr->body;
continue;
}
if (const auto* let_stmt = current.as<LetStmtNode>()) {
current = let_stmt->body;
continue;
}
if (const auto* for_stmt = current.as<ForNode>()) {
if (is_one(for_stmt->extent)) {
current = for_stmt->body;
continue;
}
if (has_unsupported_mma_loop != nullptr &&
RegisterPipelineClassifier::HasMmaCompute(for_stmt->body)) {
*has_unsupported_mma_loop = true;
}
return nullptr;
}
if (const auto* if_then_else = current.as<IfThenElseNode>()) {
if (!if_then_else->else_case.defined()) {
current = if_then_else->then_case;
continue;
}
}
return nullptr;
}
}
const SeqStmtNode* GetPipelineBodySeq(const Stmt& stmt) const {
Stmt current = stmt;
while (true) {
if (const auto* seq = current.as<SeqStmtNode>()) {
return seq;
}
if (const auto* br = current.as<BlockRealizeNode>()) {
current = br->block->body;
continue;
}
if (const auto* attr = current.as<AttrStmtNode>()) {
current = attr->body;
continue;
}
if (const auto* let_stmt = current.as<LetStmtNode>()) {
current = let_stmt->body;
continue;
}
if (const auto* allocate = current.as<AllocateNode>()) {
current = allocate->body;
continue;
}
if (const auto* decl_buffer = current.as<DeclBufferNode>()) {
current = decl_buffer->body;
continue;
}
if (const auto* if_then_else = current.as<IfThenElseNode>()) {
if (!if_then_else->else_case.defined()) {
current = if_then_else->then_case;
continue;
}
}
return nullptr;
}
}
};
} // namespace
tir::transform::Pass RegisterPipelinePlanning() {
using namespace tir::transform;
auto pass_func = [=](PrimFunc f, const IRModule&, const PassContext&) {
auto* fptr = f.CopyOnWrite();
fptr->body = RegisterPipelinePlanner()(fptr->body);
return f;
};
return CreatePrimFuncPass(pass_func, 0, "tl.RegisterPipelinePlanning", {});
}
TVM_FFI_STATIC_INIT_BLOCK() {
namespace refl = tvm::ffi::reflection;
refl::GlobalDef().def("tl.transform.RegisterPipelinePlanning",
RegisterPipelinePlanning);
}
} // namespace tl
} // namespace tvm
tilelang/engine/phase.py
View file @ 44cc93c7
......@@ -201,6 +201,12 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
# if tma is not enabled, we can also do pipeline planning
# to get better performance with async copy
mod = tilelang.transform.PipelinePlanning()(mod)
mod = tilelang.transform.RegisterPipelinePlanning()(mod)
# Register pipeline must be injected before shared pipeline.
# Shared injection rewrites loops into prologue/body/epilogue blocks
# and loses the original statement granularity expected by
# tl_register_pipeline_stage/order annotations.
mod = tilelang.transform.InjectRegisterSoftwarePipeline()(mod)
mod = tilelang.transform.InjectSoftwarePipeline()(mod)
# warp_specialized pass will pack the if stmt into the block
# so we need to lower the opaque block first
......@@ -213,18 +219,28 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
mod = tilelang.transform.IfStmtBinding()(mod)
mod = tilelang.transform.PlanAndUpdateBufferAllocationLocation()(mod)
mod = tilelang.transform.PipelinePlanning()(mod)
mod = tilelang.transform.RegisterPipelinePlanning()(mod)
print("OptimizeForTarget")
print(mod)
mod = tilelang.transform.PipelinePlanning()(mod)
mod = tilelang.transform.InjectRegisterSoftwarePipeline()(mod)
print("OptimizeForTarget2")
print(mod)
mod = tilelang.transform.InjectSoftwarePipeline()(mod)
print("OptimizeForTarget2")
print(mod)
mod = tilelang.transform.MergeIfStmt()(mod)
if allow_fence_proxy(target=target):
# in hopper device, wgmma is an async proxy
# so we need to inject a fence proxy before it
mod = tilelang.transform.InjectFenceProxy()(mod)
print("OptimizeForTarget2.5")
print(mod)
mod = tilelang.transform.LowerOpaqueBlock()(mod)
mod = tilelang.transform.Simplify()(mod)
mod = tir.transform.NarrowDataType(32)(mod)
......@@ -234,6 +250,7 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
mod = tilelang.transform.ConfigIndexBitwidth()(mod)
mod = tir.transform.Simplify()(mod)
mod = tilelang.transform.VectorizeLoop(enable_vectorize=allow_vectorize(pass_ctx=pass_ctx))(mod)
mod = tilelang.transform.StorageRewrite()(mod)
mod = tir.transform.UnrollLoop()(mod)
......@@ -245,6 +262,7 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
mod = tir.transform.VerifyMemory()(mod)
mod = tir.transform.AnnotateEntryFunc()(mod)
# TODO(lei): This is a hack to make sure the
# thread level allreduce pass can be applied
# in TL. As Tl only use one thread dimension
......@@ -271,8 +289,7 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
mod = tilelang.transform.MergeSharedMemoryAllocations(enable_aggressive_merge=enable_aggressive_merge)(mod)
mod = tilelang.transform.ThreadSync("shared")(mod)
mod = tilelang.transform.ThreadSync("shared.dyn")(mod)
print("OptimizeForTarget2")
print(mod)
# Inject PTX async copy must behind the thread sync pass
# as ptx async copy won't be recognized as a valid buffer load
if not dcu_async_copy_supported(target):
......@@ -281,8 +298,7 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
# mod = tilelang.transform.InjectDSRead()(mod)
# mod = tilelang.transform.InjectDSRead()(mod)
print("222222222")
print(mod)
if allow_tma_and_warp_specialized(pass_ctx=pass_ctx, target=target):
mod = tilelang.transform.AnnotateWarpGroupRegAlloc()(mod)
......@@ -295,6 +311,8 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
if dcu_async_copy_supported(target):
print("--------------support dcu async copy------------------")
mod = tilelang.transform.LowerSharedGlobalCopy()(mod)
print("222222222")
print(mod)
mod = tilelang.transform.FixDCUWaitCount()(mod)
mod = tilelang.transform.InjectBLocalLayoutTransform()(mod)
print("InjectBLocalLayoutTransform ............")
......@@ -302,7 +320,12 @@ def OptimizeForTarget(mod: IRModule, target: Target) -> IRModule:
mod = tilelang.transform.InjectDSRead()(mod)
print("InjectDSRead ............")
print(mod)
mod = tilelang.transform.InsertAsyncMMAFence()(mod)
print("333333333")
print(mod)
# Register pipeline planning only writes software_pipeline annotations.
# We must inject after planning so prologue/body/epilogue are materialized.
# mod = tilelang.transform.RegisterPipelinePlanning()(mod)
# mod = tilelang.transform.InjectSoftwarePipeline()(mod)
# mod = tilelang.transform.SimplifyDCUAsyncCopy()(mod)
print("OptimizeForTarget3")
print(mod)
return mod
tilelang/language/ast/ir.py
View file @ 44cc93c7
......@@ -1901,6 +1901,8 @@ tvm_mfma_store = _dtype_forward(_tir_op.tvm_mfma_store)
tvm_rdna_wmma = _dtype_forward(_tir_op.tvm_rdna_wmma)
tvm_rdna_wmma_store = _dtype_forward(_tir_op.tvm_rdna_wmma_store)
make_dcu_resource = _dtype_forward(_tir_op.make_dcu_resource)
async_gld_fence = _dtype_forward(_tir_op.async_gld_fence)
wave_barrier = _dtype_forward(_tir_op.wave_barrier)
broadcast = Broadcast
ramp = Ramp
......@@ -2224,4 +2226,6 @@ __all__ = [
"Range",
"vscale",
"make_dcu_resource",
"async_gld_fence",
"wave_barrier"
]
tilelang/transform/__init__.py
View file @ 44cc93c7
......@@ -69,6 +69,17 @@ def InjectSoftwarePipeline():
return _ffi_api.InjectSoftwarePipeline() # type: ignore
def InjectRegisterSoftwarePipeline():
"""InjectRegisterSoftwarePipeline
Returns
-------
fpass : tvm.transform.Pass
The result pass
"""
return _ffi_api.InjectRegisterSoftwarePipeline() # type: ignore
def FrontendLegalize():
"""FrontendLegalize
......@@ -549,4 +560,12 @@ def SimplifyDCUAsyncCopy():
def FixDCUWaitCount():
"""FixDCUWaitCount"""
return _ffi_api.FixDCUWaitCount() # type: ignore
\ No newline at end of file
return _ffi_api.FixDCUWaitCount() # type: ignore
def RegisterPipelinePlanning():
"""RegisterPipelinePlanning"""
return _ffi_api.RegisterPipelinePlanning() # type: ignore
def InsertAsyncMMAFence():
"""InsertAsyncMMAFence"""
return _ffi_api.InsertAsyncMMAFence() # type: ignore
\ No newline at end of file
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